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Created April 18, 2010 19:33
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--- linux-source-2.6.26/drivers/net/via-velocity.h.1.14 2009-09-26 21:03:43.000000000 +0900
+++ linux-source-2.6.26/drivers/net/via-velocity.h 2009-10-05 23:52:13.000000000 +0900
@@ -303,6 +303,8 @@
#define MAC_REG_RDCSR_CLR 0x36
#define MAC_REG_RDBASE_LO 0x38
#define MAC_REG_RDINDX 0x3C
+#define MAC_REG_TQETMR 0x3E
+#define MAC_REG_RQETMR 0x3F
#define MAC_REG_TDBASE_LO 0x40
#define MAC_REG_RDCSIZE 0x50
#define MAC_REG_TDCSIZE 0x52
@@ -509,6 +511,7 @@
#define ISRCTL1_HCRLD 0x02
#define ISRCTL1_SCRLD 0x01
+
/*
* Bits in the TXE_SR register
*/
@@ -630,6 +633,10 @@
#define CAMCR_PS_CAM_DATA 0x80
#define CAMCR_PS_MAR 0x00
+#define CAMCR_PS_TSUPPTHR 0x40
+#define CAMCR_PS_RSUPPTHR 0x80
+#define CAMCR_PS_INTHOTMR 0x00
+
/*
* Bits in the MIICFG register
*/
@@ -1007,7 +1014,8 @@
volatile __le32 RDBaseLo; /* 0x38 */
volatile __le16 RDIdx; /* 0x3C */
- volatile __le16 reserved_3E;
+ volatile u8 TQETMR; /* 0x3E */
+ volatile u8 RQETMR; /* 0x3F */
volatile __le32 TDBaseLo[4]; /* 0x40 */
@@ -1493,6 +1501,12 @@
int rx_bandwidth_hi;
int rx_bandwidth_lo;
int rx_bandwidth_en;
+
+ int txque_timer; /* Tx queue empty defer delay timer */
+ int rxque_timer; /* Rx queue empty defer delay timer */
+ int tx_intsup; /* Tx interrupt suppression threshold */
+ int rx_intsup; /* Rx interrupt suppression threshold */
+
u32 flags;
};
--- linux-source-2.6.26/drivers/net/via-velocity.c.1.14b 2009-10-05 23:49:11.000000000 +0900
+++ linux-source-2.6.26/drivers/net/via-velocity.c 2009-10-05 23:52:13.000000000 +0900
@@ -366,6 +366,32 @@
VELOCITY_PARAM(int_works, "Number of packets per interrupt services");
+#define VELOCITY_ADAPTIVE_INTR
+
+#ifdef VELOCITY_ADAPTIVE_INTR
+
+#define TXQUE_TIMER_DEF 0x59
+#define TXQUE_TIMER_MIN 0x00
+#define TXQUE_TIMER_MAX 0xFF
+VELOCITY_PARAM(txque_timer, "Tx Queue Empty defer timer");
+
+#define RXQUE_TIMER_DEF 0x14
+#define RXQUE_TIMER_MIN 0x00
+#define RXQUE_TIMER_MAX 0xFF
+VELOCITY_PARAM(rxque_timer, "Rx Queue Empty defer timer");
+
+#define TX_INTSUP_DEF 0x1F
+#define TX_INTSUP_MIN 0x01
+#define TX_INTSUP_MAX 0x3F
+VELOCITY_PARAM(tx_intsup, "Tx Interrupt Suppression Threshold");
+
+#define RX_INTSUP_DEF 0x1F
+#define RX_INTSUP_MIN 0x01
+#define RX_INTSUP_MAX 0x3F
+VELOCITY_PARAM(rx_intsup, "Rx Interrupt Suppression Threshold");
+
+#endif /* VELOCITY_ADAPTIVE_INTR */
+
static int rx_copybreak = 200;
module_param(rx_copybreak, int, 0644);
MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
@@ -592,6 +618,12 @@
velocity_set_int_opt((int *) &opts->spd_dpx, speed_duplex[index], MED_LNK_MIN, MED_LNK_MAX, MED_LNK_DEF, "Media link mode", devname);
velocity_set_int_opt((int *) &opts->wol_opts, wol_opts[index], WOL_OPT_MIN, WOL_OPT_MAX, WOL_OPT_DEF, "Wake On Lan options", devname);
velocity_set_int_opt((int *) &opts->int_works, int_works[index], INT_WORKS_MIN, INT_WORKS_MAX, INT_WORKS_DEF, "Interrupt service works", devname);
+#ifdef VELOCITY_ADAPTIVE_INTR
+ velocity_set_int_opt((int*) &opts->txque_timer, txque_timer[index], TXQUE_TIMER_MIN, TXQUE_TIMER_MAX, TXQUE_TIMER_DEF,"Tx Queue Empty defer timer", devname);
+ velocity_set_int_opt((int*) &opts->rxque_timer, rxque_timer[index], RXQUE_TIMER_MIN, RXQUE_TIMER_MAX, RXQUE_TIMER_DEF,"Rx Queue Empty defer timer", devname);
+ velocity_set_int_opt((int*) &opts->tx_intsup, tx_intsup[index], TX_INTSUP_MIN, TX_INTSUP_MAX, TX_INTSUP_DEF,"Tx Interrupt Suppression Threshold", devname);
+ velocity_set_int_opt((int*) &opts->rx_intsup, rx_intsup[index], RX_INTSUP_MIN, RX_INTSUP_MAX, RX_INTSUP_DEF,"Rx Interrupt Suppression Threshold", devname);
+#endif /* VELOCITY_ADAPTIVE_INTR */
opts->numrx = (opts->numrx & ~3);
}
@@ -692,6 +724,34 @@
writew(vptr->options.numrx - 1, &regs->RDCSize);
}
+#ifdef VELOCITY_ADAPTIVE_INTR
+/**
+ * velocity_adaptive_init
+ * @vptr: velocity to program
+ */
+
+static void velocity_adaptive_init(struct velocity_info *vptr)
+{
+
+ struct mac_regs __iomem * regs = vptr->mac_regs;
+
+ /* Select TSUPPTHR / CAM mask*/
+ BYTE_REG_BITS_SET(CAMCR_PS_TSUPPTHR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+
+ writew(vptr->options.tx_intsup, &regs->ISRCTL);
+
+ /* Select RSUPPTHR / CAM data */
+ BYTE_REG_BITS_SET(CAMCR_PS_RSUPPTHR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+
+ writew(vptr->options.rx_intsup, &regs->ISRCTL);
+
+ /* Select mar */
+ BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
+
+ vptr->int_mask &= ~(ISR_PTXI | ISR_PTX0I | ISR_PTX1I | ISR_PTX2I | ISR_PTX3I | ISR_PRXI);
+}
+#endif
+
/**
* velocity_init_registers - initialise MAC registers
* @vptr: velocity to init
@@ -780,6 +840,10 @@
vptr->int_mask = INT_MASK_DEF;
+#ifdef VELOCITY_ADAPTIVE_INTR
+ velocity_adaptive_init(vptr);
+#endif
+
writel(vptr->rd_pool_dma, &regs->RDBaseLo);
writew(vptr->options.numrx - 1, &regs->RDCSize);
mac_rx_queue_run(regs);
@@ -1830,6 +1894,21 @@
} else {
BYTE_REG_BITS_ON(TESTCFG_HBDIS, &regs->TESTCFG);
}
+
+#ifdef VELOCITY_ADAPTIVE_INTR
+ if (vptr->rev_id >= REV_ID_VT3216_A0)
+ {
+ if ( (vptr->mii_status | VELOCITY_SPEED_1000) ||
+ (vptr->mii_status | VELOCITY_SPEED_100) )
+ {
+ writeb(vptr->options.txque_timer, &regs->TQETMR);
+ writeb(vptr->options.rxque_timer, &regs->RQETMR);
+ } else {
+ writeb(0x00, &regs->TQETMR);
+ writeb(0x00, &regs->RQETMR);
+ }
+ }
+#endif
}
/*
* Get link status from PHYSR0
@@ -2252,7 +2331,8 @@
rx_works = velocity_rx_srv(vptr, isr_status);
if (isr_status & (ISR_PTXI | ISR_PPTXI))
tx_works = velocity_tx_srv(vptr, isr_status);
-
+
+#ifndef VELOCITY_ADAPTIVE_INTR
if ((tx_works > vptr->options.int_works
|| rx_works > vptr->options.int_works)
&& net_ratelimit())
@@ -2260,6 +2340,7 @@
printk(KERN_WARNING "%s: excessive work at interrupt.\n",
dev->name);
}
+#endif
spin_unlock(&vptr->lock);
mac_enable_int(vptr->mac_regs);
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