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VSCode's Settings - Syncing
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// Place your key bindings in this file to override the defaultsauto[] | |
[ | |
{ | |
"key": "ctrl+d", | |
"command": "deleteFile" | |
}, | |
{ | |
"key": "ctrl+n d", | |
"command": "explorer.newFolder" | |
}, | |
{ | |
"key": "ctrl+n f", | |
"command": "explorer.newFile" | |
}, | |
{ | |
"key": "ctrl+r", | |
"command": "workbench.files.action.refreshFilesExplorer" | |
}, | |
{ | |
"key": "ctrl+shift+k", | |
"command": "workbench.action.focusActiveEditorGroup" | |
}, | |
{ | |
"key": "ctrl+shift+f", | |
"command": "filesExplorer.findInFolder", | |
"when": "explorerResourceIsFolder && filesExplorerFocus && foldersViewVisible && !inputFocus" | |
}, | |
{ | |
"key": "ctrl+shift+h", | |
"command": "filesExplorer.re", | |
"when": "explorerResourceIsFolder && filesExplorerFocus && foldersViewVisible && !inputFocus" | |
}, | |
{ | |
"key": "ctrl+shift+j", | |
"command": "revealInExplorer" | |
}, | |
{ | |
"key": "ctrl+shift+l", | |
"command": "workbench.action.terminal.focus", | |
"when": "terminal.active" | |
}, | |
{ | |
"key": "ctrl+l", | |
"command": "workbench.action.terminal.focusPreviousPane", | |
"when": "terminalFocus && terminalHasBeenCreated || terminalFocus && terminalProcessSupported" | |
}, | |
{ | |
"key": "ctrl+h", | |
"command": "workbench.action.terminal.focusNextPane", | |
"when": "terminalFocus && terminalHasBeenCreated || terminalFocus && terminalProcessSupported" | |
}, | |
{ | |
"key": "ctrl+shift+n", | |
"command": "workbench.action.terminal.split", | |
"when": "terminalFocus && terminalProcessSupported || terminalFocus && terminalWebExtensionContributedProfile" | |
}, | |
{ | |
"key": "ctrl+shift+n", | |
"command": "-workbench.action.newWindow" | |
}, | |
{ | |
"key": "ctrl+shift+5", | |
"command": "workbench.action.newWindow" | |
}, | |
{ | |
"key": "ctrl+shift+=", | |
"command": "editor.action.fontZoomIn" | |
}, | |
{ | |
"key": "ctrl+shift+-", | |
"command": "editor.action.fontZoomOut" | |
}, | |
{ | |
"key": "ctrl+shift+9", | |
"command": "workbench.action.terminal.fontZoomIn" | |
}, | |
{ | |
"key": "ctrl+shift+0", | |
"command": "workbench.action.terminal.fontZoomOut" | |
}, | |
{ | |
"key": "ctrl+i t", | |
"command": "command-runner.run", | |
"args": { "command": "\u000D${homedir}/.config/Code/User/snippets/createSVInclude.tcl ${fileDirname} tb" }, | |
"when": "editorLangId == systemverilog" | |
}, | |
{ | |
"key": "ctrl+i v", | |
"command": "command-runner.run", | |
"args": { "command": "${homedir}/.config/Code/User/snippets/createSVInclude.tcl ${fileDirname} vipSrc" }, | |
"when": "editorLangId == systemverilog" | |
}, | |
{ | |
"key": "ctrl+i u", | |
"command": "command-runner.run", | |
"args": { "command": "${homedir}/.config/Code/User/snippets/createSVInclude.tcl ${fileDirname} unitTest" }, | |
"when": "editorLangId == systemverilog" | |
}, | |
{ | |
"key": "ctrl+i r", | |
"command": "runCommands", | |
"args": { | |
"commands": [ | |
"workbench.action.terminal.focus", | |
{ | |
"command": "workbench.action.terminal.scrollUp", | |
"when": "terminalFocusInAny && terminalHasBeenCreated && !terminalAltBufferActive || terminalFocusInAny && terminalProcessSupported && !terminalAltBufferActive" | |
}, | |
{ | |
"command": "workbench.action.terminal.sendSequence", | |
"args": { | |
"text" : "\u000Dcd ${workspaceFolder}/sim/work_tb; ./run.tcl\u000D" | |
} | |
} | |
] | |
} | |
}, | |
{ | |
"key": "ctrl+i f", | |
"command": "runCommands", | |
"args": { | |
"commands": [ | |
"workbench.action.terminal.focus", | |
{ | |
"command": "workbench.action.terminal.scrollUp", | |
"when": "terminalFocusInAny && terminalHasBeenCreated && !terminalAltBufferActive || terminalFocusInAny && terminalProcessSupported && !terminalAltBufferActive" | |
}, | |
{ | |
"command": "workbench.action.terminal.sendSequence", | |
"args": { | |
"text" : "cd ${workspaceFolder}/sim;\u000D ./fastRun.tcl tbFormatting;\u000D cd -;\u000D" | |
} | |
} | |
] | |
} | |
}, | |
{ | |
"key": "ctrl+i l", | |
"command": "runCommands", | |
"args": { | |
"commands": [ | |
"workbench.action.terminal.focus", | |
{ | |
"command": "workbench.action.terminal.scrollUp", | |
"when": "terminalFocusInAny && terminalHasBeenCreated && !terminalAltBufferActive || terminalFocusInAny && terminalProcessSupported && !terminalAltBufferActive" | |
}, | |
{ | |
"command": "workbench.action.terminal.sendSequence", | |
"args": { | |
"text" : "cd ${workspaceFolder}/sim;\u000D ./fastRun.tcl tbLinting;\u000D cd -;\u000D" | |
} | |
} | |
] | |
} | |
}, | |
{ | |
"key": "ctrl+i g", | |
"command": "runCommands", | |
"args": { | |
"commands": [ | |
"workbench.action.terminal.focus", | |
{ | |
"command": "workbench.action.terminal.scrollUp", | |
"when": "terminalFocusInAny && terminalHasBeenCreated && !terminalAltBufferActive || terminalFocusInAny && terminalProcessSupported && !terminalAltBufferActive" | |
}, | |
{ | |
"command": "workbench.action.terminal.sendSequence", | |
"args": { | |
"text" : "\u000Dcd ${workspaceFolder}\u000D git status\u000d" | |
} | |
}, | |
"workbench.action.terminal.focus" | |
] | |
} | |
}, | |
{ | |
"key": "ctrl+q", | |
"command": "toggleVim" | |
}, | |
{ | |
"key": "ctrl+shift+m", | |
"command": "workbench.action.toggleMaximizedPanel" | |
}, | |
{ | |
"key": "shift+enter", | |
"when": "editorTextFocus && !editorReadonly", | |
"command": "editor.action.insertLineBefore", | |
}, | |
{ | |
"key": "ctrl+shift+o", | |
"command": "workbench.action.terminal.openFileLink", | |
"when": "terminalHasBeenCreated" | |
} | |
] |
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{ | |
"workbench.colorTheme": "Default Light Modern", | |
"window.zoomLevel": -2, | |
"autoSnippet.snippets": [ | |
{ | |
"pattern": "**/*.cpp", | |
"snippet": "body-template" | |
}, | |
{ | |
"language": "javascript", | |
"snippet": "template" | |
}, | |
{ | |
"language": "systemverilog", | |
"snippet": "systemverilog" | |
} | |
], | |
"editor.tabSize": 2, | |
"[systemverilog]": { | |
"editor.tabSize": 2, | |
"editor.rulers": [ | |
120 | |
] | |
}, | |
"files.associations": { | |
"*.v": "systemverilog", | |
"*.vh": "systemverilog", | |
"*.vi": "systemverilog", | |
"*.sv": "systemverilog", | |
"*.svh": "systemverilog", | |
"*.svi": "systemverilog", | |
"*.sva": "systemverilog", | |
"*.svp": "systemverilog", | |
"*.test": "tcl", | |
"*.source_bash": "shellscript" | |
}, | |
"explorer.confirmDragAndDrop": false, | |
"[tcl]": { | |
"editor.tabSize": 4, | |
"editor.rulers": [ | |
80 | |
] | |
}, | |
"[shellscript]": { | |
"editor.tabSize": 4, | |
"editor.rulers": [ | |
80 | |
] | |
}, | |
"systemverilogFormatter.commandLineArguments": "--column_limit 120 --indentation_spaces 16", | |
"editor.defaultFormatter": "bmpenuelas.systemverilog-formatter-vscode", | |
"unsaved-files.viewOnExplorer.enabled": true, | |
"files.exclude": { | |
"**/tmp/**": true, | |
"**/node_modules/**": true, | |
"**/.git/objects/**": true, | |
}, | |
"files.watcherExclude": { | |
"**/.git/objects/**": true, | |
"**/.git/subtree-cache/**": true, | |
"**/node_modules/**": true, | |
"**/tmp/**": true, | |
"**/dist/**": true | |
}, | |
"search.exclude": { | |
"**/node_modules/**": true, | |
"**/dist/**": true, | |
"**/tmp/**": true, | |
"**/.git/objects/**": true, | |
"**/.git/subtree-cache/**": true | |
}, | |
"extensions.autoCheckUpdates": false, | |
"extensions.autoUpdate": false, | |
"search.followSymlinks": false, | |
"syncing.excludedExtensions": [ | |
"*" | |
], | |
"git.enableSmartCommit": true, | |
"editor.minimap.enabled": false, | |
"vim.handleKeys": { | |
"<C-p>": false, | |
"<C-w>": false | |
}, | |
"vim.normalModeKeyBindings": [ | |
{ | |
"before": ["enter"], | |
"after": ["o", "escape"] | |
}, | |
{ | |
"before": ["space"], | |
"after": ["a", " ", "escape", "l"] | |
}, | |
{ | |
"before": ["ctrl+j"], | |
"after": ["ctrl+d"] | |
}, | |
{ | |
"before": ["ctrl+k"], | |
"after": ["ctrl+u"] | |
}, | |
{ | |
"before": ["<C-n>"], | |
"commands": [":nohl"] | |
}, | |
{ | |
"before": ["L"], | |
"after": ["$"] | |
}, | |
{ | |
"before": ["d","n"], | |
"after": [], | |
"commands": [ | |
{ | |
"command": "editor.action.joinLines", | |
"args": [] | |
} | |
] | |
}, | |
{ | |
"before": ["H"], | |
"after": ["^"] | |
}, | |
{ | |
"before": ["J"], | |
"after": [] | |
}, | |
{ | |
"before": ["u"], | |
"after": [], | |
"commands": [ | |
{ | |
"command": "undo", | |
"args": [] | |
} | |
] | |
}, | |
{ | |
"before": ["U"], | |
"after": [], | |
"commands": [ | |
{ | |
"command": "redo", | |
"args": [] | |
} | |
] | |
} | |
], | |
"vim.normalModeKeyBindingsNonRecursive": [ | |
], | |
"vim.visualModeKeyBindingsNonRecursive": [ | |
{ | |
"before": [ | |
"p", | |
], | |
"after": [ | |
"p", | |
"g", | |
"v", | |
"y" | |
] | |
}, | |
{ | |
"before": ["L"], | |
"after": ["$"] | |
}, | |
{ | |
"before": ["H"], | |
"after": ["^"] | |
}, | |
{ | |
"before": ["ctrl+j"], | |
"after": ["ctrl+d"] | |
}, | |
{ | |
"before": ["ctrl+k"], | |
"after": ["ctrl+u"] | |
} | |
], | |
"vim.visualModeKeyBindings": [ | |
{ | |
"before": [ | |
">" | |
], | |
"commands": [ | |
"editor.action.indentLines" | |
] | |
}, | |
{ | |
"before": [ | |
"<" | |
], | |
"commands": [ | |
"editor.action.outdentLines" | |
] | |
} | |
], | |
"vim.operatorPendingModeKeyBindings": [ | |
{ | |
"before": ["L"], | |
"after": ["$"] | |
}, | |
{ | |
"before": ["H"], | |
"after": ["^"] | |
} | |
], | |
"vim.insertModeKeyBindings": [ | |
{ | |
"before": ["k", "k"], | |
"after": ["<Esc>"] | |
}, | |
{ | |
"before": ["K", "K"], | |
"after": ["<Esc>"] | |
} | |
], | |
"vim.hlsearch": true, | |
"vim.useSystemClipboard": true, | |
"vim.autoindent": true, | |
"explorer.autoReveal": false, | |
"vim.highlightedyank.enable": true, | |
"vim.camelCaseMotion.enable": true, | |
"vim.leader": "m", | |
"editor.lineNumbers": "relative", | |
"terminal.integrated.env.linux": { | |
"SIM_SCRIPTS_PIPELINE_POST_CFG": "${workspaceFolder}/sim/scripts/cfg/vsCode.tcl" | |
}, | |
"terminal.integrated.scrollback": 100000, | |
"terminal.integrated.fontSize": 16 | |
} |
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#!/usr/bin/env tclsh | |
set params [dict create] | |
proc interpretParams {} { | |
dict set ::params includeFileDir [lindex $::argv 0] | |
dict set ::params contextType [lindex $::argv 1] | |
} | |
proc getRelativePath {initialDir} { | |
set searchDir $initialDir | |
set relativePath {} | |
while {![::dirContainesPackage $searchDir]} { | |
set relativePath [file join [file tail $searchDir] $relativePath] | |
set searchDir [file dirname $searchDir] | |
::assertNotTheRoot $searchDir | |
} | |
return [::adjustRelativePath $searchDir $relativePath] | |
} | |
proc dirContainesPackage {dir} { | |
set dirName [file tail $dir] | |
if {[dict get $::params contextType] eq "unitTest"} { | |
return [expr {[llength [glob -directory $dir -type f -- *_pkg.svh]]\ | |
== 1}] | |
} else { | |
return [expr {[llength [glob -nocomplain -directory $dir -- *.sv]] \ | |
== 1}] | |
} | |
} | |
proc assertNotTheRoot {dir} { | |
if {$dir == "/"} { | |
error "No package found" | |
} | |
} | |
proc adjustRelativePath {searchDir relativePath} { | |
if {[dict get $::params contextType] eq "vipSrc"} { | |
return $relativePath | |
} else { | |
return [file join [file tail $searchDir] $relativePath] | |
} | |
} | |
proc getSourceItemsWithRelativePath {dir relativePath} { | |
set sourceItems [::getSourceItems $dir] | |
set sourceItems [::getSourceItemsWithoutIncludeFile $sourceItems] | |
return [lmap sourceItem $sourceItems { | |
file join $relativePath [file tail $sourceItem] | |
}] | |
} | |
proc getSourceItems {dir} { | |
set result [list \ | |
{*}[glob -nocomplain -type d -directory $dir -- *] \ | |
{*}[glob -nocomplain -type f -directory $dir -- *.svh] | |
] | |
if {$result eq {}} { | |
error "Not found any files or dirs" | |
} | |
return $result | |
} | |
proc getSourceItemsWithoutIncludeFile {files} { | |
return [lmap file $files { | |
if {[file tail $file] eq "include.svh"} { | |
continue | |
} else { | |
string cat $file | |
} | |
}] | |
} | |
proc composeIncludeFile {filePath sourceItems} { | |
set file [open $filePath w+] | |
foreach sourceItem $sourceItems { | |
if {[::isDirectory $sourceItem]} { | |
puts $file [string cat `include { } \" $sourceItem /include.svh \"] | |
} else { | |
puts $file [string cat `include { } \" $sourceItem \"] | |
} | |
} | |
close $file | |
} | |
proc isDirectory {path} { | |
set tail [file tail $path] | |
return [expr {$tail == [file rootname $tail]}] | |
} | |
proc main {} { | |
::interpretParams | |
set relativePath [::getRelativePath [dict get $::params includeFileDir]] | |
set sourceItemsWithRelativePath [::getSourceItemsWithRelativePath \ | |
[dict get $::params includeFileDir] $relativePath] | |
::composeIncludeFile [file join [dict get $::params includeFileDir] \ | |
include.svh] $sourceItemsWithRelativePath | |
} | |
if {[catch {main} result ropts]} { | |
puts $ropts | |
exit 1 | |
} else { | |
exit 0 | |
} |
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{ | |
} |
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{ | |
"class": { | |
"scope": "systemverilog", | |
"prefix": "class", | |
"body": [ | |
"class ${TM_FILENAME_BASE};", | |
"\t$0", | |
"", | |
"\tstatic function ${TM_FILENAME_BASE} get_inst();", | |
"\t\t${TM_FILENAME_BASE} inst = new();", | |
"\t\treturn inst;", | |
"\tendfunction", | |
"endclass" | |
] | |
}, | |
"filename": { | |
"scope": "systemverilog", | |
"prefix": "filename", | |
"body": [ | |
"${TM_FILENAME_BASE}" | |
] | |
}, | |
"get_inst": { | |
"scope": "systemverilog", | |
"prefix": "get-inst", | |
"body": [ | |
"static function ${TM_FILENAME_BASE} get_inst();", | |
"\t${TM_FILENAME_BASE} inst = new();", | |
"\treturn inst;", | |
"endfunction" | |
] | |
}, | |
"file_header": { | |
"scope": "systemverilog", | |
"prefix": "file-header", | |
"body": [ | |
"`ifndef ${TM_FILENAME/(\\.)|(.)/${1:+_}${2:/upcase}/g}", | |
"`define ${TM_FILENAME/(\\.)|(.)/${1:+_}${2:/upcase}/g}", | |
"$0", | |
"`endif" | |
] | |
}, | |
"include_file": { | |
"scope": "systemverilog", | |
"prefix": "include-file", | |
"body": [ | |
"`include \"${RELATIVE_FILEPATH}\"" | |
] | |
}, | |
"task" : { | |
"scope": "systemverilog", | |
"prefix": "task", | |
"body": [ | |
"task ${2:task}();", | |
"\t$0", | |
"endtask" | |
] | |
}, | |
"virtual_task" : { | |
"scope": "systemverilog", | |
"prefix": "virtual-task", | |
"body": [ | |
"virtual task ${2:task}();", | |
"\t$0", | |
"endtask" | |
] | |
}, | |
"protected_task" : { | |
"scope": "systemverilog", | |
"prefix": "protected-task", | |
"body": [ | |
"protected task ${2:task}();", | |
"\t$0", | |
"endtask" | |
] | |
}, | |
"local_task" : { | |
"scope": "systemverilog", | |
"prefix": "local-task", | |
"body": [ | |
"local task ${2:task}();", | |
"\t$0", | |
"endtask" | |
] | |
}, | |
"local_virtual_task" : { | |
"scope": "systemverilog", | |
"prefix": "local-virtual-task", | |
"body": [ | |
"local virtual task ${2:task}();", | |
"\t$0", | |
"endtask" | |
] | |
}, | |
"virtual_protected_task" : { | |
"scope": "systemverilog", | |
"prefix": "virtual-protected-task", | |
"body": [ | |
"virtual protected task ${2:task}();", | |
"\t$0", | |
"endtask" | |
] | |
}, | |
"pure_task" : { | |
"scope": "systemverilog", | |
"prefix": "pure-task", | |
"body": [ | |
"pure virtual task ${2:task}();" | |
] | |
}, | |
"task_automatic": { | |
"scope": "systemverilog", | |
"prefix": "task-automatic", | |
"body": [ | |
"task automatic ${1:task}();", | |
"\t$0", | |
"endtask" | |
] | |
}, | |
"function" : { | |
"scope": "systemverilog", | |
"prefix": "function", | |
"body": [ | |
"function ${1:void} ${2:function}();", | |
"\t$0", | |
"endfunction" | |
] | |
}, | |
"local_function" : { | |
"scope": "systemverilog", | |
"prefix": "local-function", | |
"body": [ | |
"local function ${1:void} ${2:function}();", | |
"\t$0", | |
"endfunction" | |
] | |
}, | |
"virtual_function" : { | |
"scope": "systemverilog", | |
"prefix": "virtual-function", | |
"body": [ | |
"virtual function ${1:void} ${2:function}();", | |
"\t$0", | |
"endfunction" | |
] | |
}, | |
"virtual_protected_function" : { | |
"scope": "systemverilog", | |
"prefix": "virtual-protected-function", | |
"body": [ | |
"virtual protected function ${1:void} ${2:function}();", | |
"\t$0", | |
"endfunction" | |
] | |
}, | |
"local_virtual_function" : { | |
"scope": "systemverilog", | |
"prefix": "local-virtual-function", | |
"body": [ | |
"local virtual function ${1:void} ${2:function}();", | |
"\t$0", | |
"endfunction" | |
] | |
}, | |
"pure_function" : { | |
"scope": "systemverilog", | |
"prefix": "pure-function", | |
"body": [ | |
"pure virtual function ${1:void} ${2:function}();" | |
] | |
}, | |
"function-automatic": { | |
"scope": "systemverilog", | |
"prefix": "function-automatic", | |
"body": [ | |
"function automatic ${1:void} ${2:function}();", | |
"\t$0", | |
"endfunction" | |
] | |
}, | |
"pre_start" : { | |
"scope": "systemverilog", | |
"prefix": "pre-start", | |
"body": [ | |
"virtual task pre_start();", | |
"\tsuper.pre_start();", | |
"\t$0", | |
"endtask" | |
] | |
}, | |
"sequence_body" : { | |
"scope": "systemverilog", | |
"prefix": "sequence-body", | |
"body": [ | |
"task body();", | |
"\t$0", | |
"endtask" | |
] | |
}, | |
"post_start" : { | |
"scope": "systemverilog", | |
"prefix": "post-start", | |
"body": [ | |
"virtual task post_start();", | |
"\tsuper.post_start();", | |
"\t$0", | |
"endtask" | |
] | |
}, | |
"package": { | |
"scope": "systemverilog", | |
"prefix": "package", | |
"body": [ | |
"package ${TM_FILENAME_BASE};", | |
"\t$0", | |
"endpackage" | |
] | |
}, | |
"package_with_uvm": { | |
"scope": "systemverilog", | |
"prefix": "package-with-uvm", | |
"body": [ | |
"package ${TM_FILENAME_BASE};", | |
"\timport uvm_pkg::*;", | |
"", | |
"\t`include \"uvm_macros.svh\"", | |
"\t$0", | |
"endpackage" | |
] | |
}, | |
"begin-end": { | |
"scope": "systemverilog", | |
"prefix": "begin-end", | |
"body": [ | |
"begin", | |
"\t$0", | |
"end" | |
] | |
}, | |
"display": { | |
"scope": "systemverilog", | |
"prefix": "$display", | |
"body": [ | |
"\\$display(\"$1\", $0);" | |
] | |
}, | |
"sformatf": { | |
"scope": "systemverilog", | |
"prefix": "$sformatf", | |
"body": [ | |
"\\$sformatf(\"$1\", $0)" | |
] | |
}, | |
"case": { | |
"scope": "systemverilog", | |
"prefix": "case", | |
"body": [ | |
"case($1)", | |
"\t$0", | |
"\tdefault : begin", | |
"\t\t", | |
"\tend", | |
"endcase" | |
] | |
}, | |
"if": { | |
"scope": "systemverilog", | |
"prefix": "if", | |
"body": [ | |
"if ($1) begin", | |
"\t$0", | |
"end" | |
] | |
}, | |
"if-else": { | |
"scope": "systemverilog", | |
"prefix": "if-else", | |
"body": [ | |
"if($1) begin", | |
"\t$2", | |
"end", | |
"else begin", | |
"\t$3", | |
"end" | |
] | |
}, | |
"uvm_analysis_imp_default": { | |
"scope": "systemverilog", | |
"prefix": "uvm-analysis-imp-default", | |
"body": [ | |
"uvm_analysis_imp #(transaction_type, ${TM_FILENAME_BASE}) imp_name;", | |
"", | |
"imp_name = new(\"imp_name\", this);", | |
"", | |
"virtual function void write(transaction_type item);", | |
"\t", | |
"endfunction" | |
] | |
}, | |
"uvm_analysis_imp": { | |
"scope": "systemverilog", | |
"prefix": "uvm-analysis-imp", | |
"body": [ | |
"`uvm_analysis_imp_decl(_suffix)", | |
"", | |
"uvm_analysis_imp_suffix #(transaction_type, ${TM_FILENAME_BASE}) imp_name;", | |
"", | |
"imp_name = new(\"imp_name\", this);", | |
"", | |
"virtual function void write_suffix(transaction_type item);", | |
"\t", | |
"endfunction" | |
] | |
}, | |
"create_uvm_component": { | |
"scope": "systemverilog", | |
"prefix": "create-uvm-component", | |
"body": [ | |
"$1 = $0::type_id::create(\"$1\", this);" | |
] | |
}, | |
"create_uvm_object": { | |
"scope": "systemverilog", | |
"prefix": "create-uvm-object", | |
"body": [ | |
"$1 = $0::type_id::create(\"$1\");" | |
] | |
}, | |
"get_clone": { | |
"scope": "systemverilog", | |
"prefix": "get-clone", | |
"body": [ | |
"static function ${TM_FILENAME_BASE} get_clone(${TM_FILENAME_BASE} other);", | |
"\t${TM_FILENAME_BASE} clone;", | |
"\tassert(\\$cast(clone, other.clone()));", | |
"\treturn clone;", | |
"endfunction" | |
] | |
}, | |
"build_phase": { | |
"scope": "systemverilog", | |
"prefix": "build-phase", | |
"body": [ | |
"virtual function void build_phase(uvm_phase phase);", | |
"\tsuper.build_phase(phase);", | |
"\t$0", | |
"endfunction", | |
] | |
}, | |
"connect_phase": { | |
"scope": "systemverilog", | |
"prefix": "connect-phase", | |
"body": [ | |
"virtual function void connect_phase(uvm_phase phase);", | |
"\tsuper.connect_phase(phase);", | |
"\t$0", | |
"endfunction", | |
] | |
}, | |
"run_phase": { | |
"scope": "systemverilog", | |
"prefix": "run-phase", | |
"body": [ | |
"virtual task run_phase(uvm_phase phase);", | |
"\tsuper.run_phase(phase);", | |
"\t$0", | |
"endtask", | |
] | |
}, | |
"start_of_simulation_phase": { | |
"scope": "systemverilog", | |
"prefix": "start_of_simulation-phase", | |
"body": [ | |
"virtual function void start_of_simulation_phase(uvm_phase phase);", | |
"\tsuper.start_of_simulation_phase(phase);", | |
"\t$0", | |
"endfunction", | |
] | |
}, | |
"end_of_elaboration_phase": { | |
"scope": "systemverilog", | |
"prefix": "end_of_elaboration-phase", | |
"body": [ | |
"virtual function void end_of_elaboration_phase(uvm_phase phase);", | |
"\tsuper.end_of_elaboration_phase(phase);", | |
"\t$0", | |
"endfunction", | |
] | |
}, | |
"reset_phase": { | |
"scope": "systemverilog", | |
"prefix": "reset-phase", | |
"body": [ | |
"virtual task reset_phase(uvm_phase phase);", | |
"\tsuper.reset_phase(phase);", | |
"\t$0", | |
"endtask", | |
] | |
}, | |
"check_phase": { | |
"scope": "systemverilog", | |
"prefix": "check-phase", | |
"body": [ | |
"virtual function void check_phase(uvm_phase phase);", | |
"\tsuper.check_phase(phase);", | |
"\t$0", | |
"endfunction", | |
] | |
}, | |
"uvm_component": { | |
"scope": "systemverilog", | |
"prefix": "uvm-component", | |
"body": [ | |
"class ${TM_FILENAME_BASE} extends uvm_$1;", | |
"\t`uvm_component_utils($0::${TM_FILENAME_BASE})", | |
"", | |
"\tfunction new(string name = get_type_name(), uvm_component parent = null);", | |
"\t\tsuper.new(name, parent);", | |
"\tendfunction", | |
"", | |
"\tvirtual function void build_phase(uvm_phase phase);", | |
"\t\tsuper.build_phase(phase);", | |
"\tendfunction", | |
"", | |
"\tvirtual function void connect_phase(uvm_phase phase);", | |
"\t\tsuper.connect_phase(phase);", | |
"\tendfunction", | |
"", | |
"\tvirtual task run_phase(uvm_phase phase);", | |
"\t\tsuper.run_phase(phase);", | |
"\tendtask", | |
"endclass" | |
] | |
}, | |
"uvm_test": { | |
"scope": "systemverilog", | |
"prefix": "uvm-test", | |
"body": [ | |
"class ${TM_FILENAME_BASE} extends base;", | |
"\t`uvm_component_utils(test::${TM_FILENAME_BASE})", | |
"", | |
"\tfunction new(string name = get_type_name(), uvm_component parent = null);", | |
"\t\tsuper.new(name, parent);", | |
"\tendfunction", | |
"", | |
"\tvirtual protected task start_main_sequence();", | |
"\t\t${TM_FILENAME_BASE}_main_sequence main = ${TM_FILENAME_BASE}_main_sequence::type_id::create(\"main\");", | |
"\t\tmain.start(m_env.m_virtual_sequencer);", | |
"\tendtask", | |
"endclass", | |
"" | |
] | |
}, | |
"empty_test": { | |
"scope": "systemverilog", | |
"prefix": "empty-test", | |
"body": [ | |
"class ${TM_FILENAME_BASE} extends base;", | |
"\t`uvm_component_utils(test::${TM_FILENAME_BASE})", | |
"", | |
"\tfunction new(string name = get_type_name(), uvm_component parent = null);", | |
"\t\tsuper.new(name, parent);", | |
"\tendfunction", | |
"", | |
"\tvirtual protected task start_main_sequence();", | |
"\t\t`uvm_info(get_type_name(), \"Empty test\", UVM_LOW)", | |
"\tendtask", | |
"endclass", | |
"" | |
] | |
}, | |
"uvm_test_main_sequence": { | |
"scope": "systemverilog", | |
"prefix": "uvm-test-main-sequence", | |
"body": [ | |
"class ${TM_FILENAME_BASE} extends sequence_lib::sequence_base;", | |
"\t`uvm_object_utils(test::${TM_FILENAME_BASE})", | |
"", | |
"\tfunction new(string name = get_type_name());", | |
"\t\tsuper.new(name);", | |
"\tendfunction", | |
"", | |
"\ttask body();", | |
"\t\t`uvm_info(get_type_name(), \"Started!\", UVM_LOW)", | |
"\tendtask", | |
"endclass", | |
"" | |
] | |
}, | |
"uvm_component_utils": { | |
"scope": "systemverilog", | |
"prefix": "uvm-component-utils", | |
"body": [ | |
"`uvm_component_utils($0::${TM_FILENAME_BASE})" | |
] | |
}, | |
"uvm_component_constructor": { | |
"scope": "systemverilog", | |
"prefix": "uvm-component-constructor", | |
"body": [ | |
"function new(string name = get_type_name(), uvm_component parent = null);", | |
"\tsuper.new(name, parent);", | |
"endfunction" | |
] | |
}, | |
"uvm_object_constructor": { | |
"scope": "systemverilog", | |
"prefix": "uvm-object-constructor", | |
"body": [ | |
"function new(string name = get_type_name());", | |
"\tsuper.new(name);", | |
"endfunction" | |
] | |
}, | |
"uvm_object_utils": { | |
"scope": "systemverilog", | |
"prefix": "uvm-object-utils", | |
"body": [ | |
"`uvm_object_utils($0::${TM_FILENAME_BASE})" | |
] | |
}, | |
"uvm_object": { | |
"scope": "systemverilog", | |
"prefix": "uvm-object", | |
"body": [ | |
"class ${TM_FILENAME_BASE} extends ${1:uvm_object};", | |
"\t`uvm_object_utils($2::${TM_FILENAME_BASE})", | |
"", | |
"\t$3", | |
"", | |
"\tfunction new(string name = get_type_name());", | |
"\t\tsuper.new(name);", | |
"\tendfunction", | |
"", | |
"\tfunction bit do_compare(uvm_object rhs, uvm_comparer comparer);", | |
"\t\t${TM_FILENAME_BASE} _rhs;", | |
"", | |
"\t\tdo_compare = super.do_compare(rhs, comparer);", | |
"\t\tassert(\\$cast(_rhs, rhs));", | |
"\t\t$4", | |
"\tendfunction", | |
"", | |
"\tfunction void do_copy(uvm_object rhs);", | |
"\t\t${TM_FILENAME_BASE} _rhs;", | |
"", | |
"\t\tsuper.do_copy(rhs);", | |
"\t\tassert(\\$cast(_rhs, rhs));", | |
"\t\t$5", | |
"\tendfunction", | |
"", | |
"\tfunction void do_print(uvm_printer printer);", | |
"\t\tsuper.do_print(printer);", | |
"\t\t$0", | |
"\tendfunction", | |
"", | |
"\tfunction string convert2string();", | |
"\t\treturn this.sprint();", | |
"\tendfunction", | |
"endclass" | |
] | |
}, | |
"do_compare" : { | |
"scope": "systemverilog", | |
"prefix": "do-compare", | |
"body": [ | |
"virtual function bit do_compare(uvm_object rhs, uvm_comparer comparer);", | |
"\t${TM_FILENAME_BASE} _rhs;", | |
"", | |
"\tdo_compare = super.do_compare(rhs, comparer);", | |
"\tassert(\\$cast(_rhs, rhs));", | |
"\t$0", | |
"endfunction" | |
] | |
}, | |
"compare_field" : { | |
"scope": "systemverilog", | |
"prefix": "compare-field", | |
"body": [ | |
"do_compare &= comparer.compare_field(\"$1\", $1, _rhs.$1, \\$bits($1), UVM_${0:HEX});" | |
] | |
}, | |
"compare_field_dec" : { | |
"scope": "systemverilog", | |
"prefix": "compare-field-dec", | |
"body": [ | |
"do_compare &= comparer.compare_field(\"$0\", $0, _rhs.$0, \\$bits($0), UVM_DEC);" | |
] | |
}, | |
"compare_field_bin" : { | |
"scope": "systemverilog", | |
"prefix": "compare-field-bin", | |
"body": [ | |
"do_compare &= comparer.compare_field(\"$0\", $0, _rhs.$0, \\$bits($0), UVM_BIN);" | |
] | |
}, | |
"compare_field_array": { | |
"scope": "systemverilog", | |
"prefix": "compare-field-array", | |
"body": [ | |
"do_compare &= compare_$1(_rhs, comparer);", | |
"virtual protected function bit compare_$1(${TM_FILENAME_BASE} _rhs, uvm_comparer comparer);", | |
"\tcompare_$1 = comparer.compare_field(\"$1_size()\", $1.size(), _rhs.$1.size(), 32, UVM_DEC);", | |
"\tforeach ($1[i]) begin", | |
"\t\tcompare_$1 &= comparer.compare_field(\\$sformatf(\"$1[%0d]\", i), $1[i], _rhs.$1[i], \\$bits($1[i]), UVM_${0:HEX});", | |
"\tend", | |
"endfunction" | |
] | |
}, | |
"compare_object" : { | |
"scope": "systemverilog", | |
"prefix": "compare-object", | |
"body": [ | |
"do_compare &= comparer.compare_object(\"$0\", $0, _rhs.${0});" | |
] | |
}, | |
"compare_string" : { | |
"scope": "systemverilog", | |
"prefix": "compare-string", | |
"body": [ | |
"do_compare &= comparer.compare_string(\"$0\", $0, _rhs.$0);" | |
] | |
}, | |
"compare_enum" : { | |
"scope": "systemverilog", | |
"prefix": "compare-enum", | |
"body": [ | |
"do_compare &= comparer.compare_string(\"$0\", $0.name(), _rhs.$0.name());" | |
] | |
}, | |
"do_copy" : { | |
"scope": "systemverilog", | |
"prefix": "do-copy", | |
"body": [ | |
"virtual function void do_copy(uvm_object rhs);", | |
"\t${TM_FILENAME_BASE} _rhs;", | |
"", | |
"\tsuper.do_copy(rhs);", | |
"\tassert(\\$cast(_rhs, rhs));", | |
"\t$0", | |
"endfunction" | |
] | |
}, | |
"copy_field" : { | |
"scope": "systemverilog", | |
"prefix": "copy-field", | |
"body": [ | |
"$0 = _rhs.${0};" | |
] | |
}, | |
"copy_object" : { | |
"scope": "systemverilog", | |
"prefix": "copy-object", | |
"body": [ | |
"$0.copy(_rhs.${0});" | |
] | |
}, | |
"do_print": { | |
"scope": "systemverilog", | |
"prefix": "do-print", | |
"body": [ | |
"virtual function void do_print(uvm_printer printer);", | |
"\tsuper.do_print(printer);", | |
"\t$0", | |
"endfunction" | |
] | |
}, | |
"print_field": { | |
"scope": "systemverilog", | |
"prefix": "print-field", | |
"body": [ | |
"printer.print_field(\"$1\", $1, \\$bits($1), UVM_${0:HEX});" | |
] | |
}, | |
"print_field_bin": { | |
"scope": "systemverilog", | |
"prefix": "print-field-bin", | |
"body": [ | |
"printer.print_field(\"$0\", $0, \\$bits($0), UVM_BIN);" | |
] | |
}, | |
"print_field_dec": { | |
"scope": "systemverilog", | |
"prefix": "print-field-dec", | |
"body": [ | |
"printer.print_field(\"$0\", $0, \\$bits($0), UVM_DEC);" | |
] | |
}, | |
"print_real": { | |
"scope": "systemverilog", | |
"prefix": "print-real", | |
"body": [ | |
"printer.print_real(\"$0\", $0);" | |
] | |
}, | |
"print_field_array": { | |
"scope": "systemverilog", | |
"prefix": "print-field-array", | |
"body": [ | |
"print_$1(printer);", | |
"virtual protected function void print_$1(uvm_printer printer);", | |
"\tprinter.print_field(\"$1_size\", $1.size(), 32, UVM_DEC);", | |
"\tforeach ($1[i]) begin", | |
"\t\tprinter.print_field(\\$sformatf(\"$1[%0d]\", i), $1[i], \\$bits($1[i]), UVM_${0:HEX});", | |
"\tend", | |
"endfunction" | |
] | |
}, | |
"print_enum": { | |
"scope": "systemverilog", | |
"prefix": "print-enum", | |
"body": [ | |
"printer.print_string(\"$0\", ${0}.name());" | |
] | |
}, | |
"print_object": { | |
"scope": "systemverilog", | |
"prefix": "print-object", | |
"body": [ | |
"printer.print_object(\"$0\", $0);" | |
] | |
}, | |
"print_time": { | |
"scope": "systemverilog", | |
"prefix": "print-time", | |
"body": [ | |
"printer.print_time(\"$0\", $0);" | |
] | |
}, | |
"print_string": { | |
"scope": "systemverilog", | |
"prefix": "print-string", | |
"body": [ | |
"printer.print_string(\"$0\", $0);" | |
] | |
}, | |
"do_pack": { | |
"scope": "systemverilog", | |
"prefix": "do-pack", | |
"body": [ | |
"virtual function void do_pack(uvm_packer packer);", | |
"\tsuper.do_pack(pack);", | |
"\t$0", | |
"endfunction" | |
] | |
}, | |
"pack_object": { | |
"scope": "systemverilog", | |
"prefix": "pack-object", | |
"body": [ | |
"packer.pack_object($0);" | |
] | |
}, | |
"pack_field_int": { | |
"scope": "systemverilog", | |
"prefix": "pack-field-int", | |
"body": [ | |
"packer.pack_field_int($0, \\$bits($0));" | |
] | |
}, | |
"uvm_sequence": { | |
"scope": "systemverilog", | |
"prefix": "uvm-sequence", | |
"body": [ | |
"class ${TM_FILENAME_BASE} extends ${1:uvm_sequence};", | |
"\t`uvm_object_utils($2::${TM_FILENAME_BASE})", | |
"\t`uvm_declare_p_sequencer($3)", | |
"", | |
"\tfunction new(string name = get_type_name());", | |
"\t\tsuper.new(name);", | |
"\tendfunction", | |
"", | |
"\ttask body();", | |
"\t\t$0", | |
"\tendtask", | |
"endclass" | |
] | |
}, | |
"`uvm_fatal": { | |
"scope": "systemverilog", | |
"prefix": "`uvm-fatal", | |
"body": [ | |
"`uvm_fatal(get_type_name(), $0)" | |
] | |
}, | |
"`uvm_error": { | |
"scope": "systemverilog", | |
"prefix": "`uvm-error", | |
"body": [ | |
"`uvm_error(get_type_name(), $0)" | |
] | |
}, | |
"`uvm_info": { | |
"scope": "systemverilog", | |
"prefix": "`uvm-info", | |
"body": [ | |
"`uvm_info(get_type_name(), $1, ${0:UVM_LOW})" | |
] | |
}, | |
"for_uint32_t": { | |
"scope": "systemverilog", | |
"prefix": "for-uint32_t", | |
"body": [ | |
"for(util::uint32_t ${1:i} = 0; ${1:i} < $0; ${1:i}++) begin", | |
"\t", | |
"end" | |
] | |
}, | |
"foreach": { | |
"scope": "systemverilog", | |
"prefix": "foreach", | |
"body": [ | |
"foreach($1) begin", | |
"\t$0", | |
"end" | |
] | |
}, | |
"repeat": { | |
"scope": "systemverilog", | |
"prefix": "repeat", | |
"body": [ | |
"repeat($1) begin", | |
"\t$0", | |
"end" | |
] | |
}, | |
"always": { | |
"scope": "systemverilog", | |
"prefix": "always", | |
"body": [ | |
"always @($1) begin", | |
"end" | |
] | |
}, | |
"module": { | |
"scope": "systemverilog", | |
"prefix": "module", | |
"body": [ | |
"module ${TM_FILENAME_BASE} #(", | |
"\t$1", | |
") (", | |
"\t$2", | |
");", | |
"\t$3", | |
"endmodule" | |
] | |
}, | |
"interface": { | |
"scope": "systemverilog", | |
"prefix": "interface", | |
"body": [ | |
"interface ${TM_FILENAME_BASE} #(", | |
"\t$1", | |
") (", | |
"\t$2", | |
");", | |
"\t$0", | |
"endinterface" | |
] | |
}, | |
"initial": { | |
"scope": "systemverilog", | |
"prefix": "initial", | |
"body": [ | |
"initial begin", | |
"\t$0", | |
"end" | |
] | |
}, | |
"forever": { | |
"scope": "systemverilog", | |
"prefix": "forever", | |
"body": [ | |
"forever begin", | |
"\t$0", | |
"end" | |
] | |
}, | |
"randomize": { | |
"scope": "systemverilog", | |
"prefix": "randomize", | |
"body": [ | |
"assert(${0}.randomize());" | |
] | |
}, | |
"std_randomize": { | |
"scope": "systemverilog", | |
"prefix": "std-randomize", | |
"body": [ | |
"assert(std::randomize(${0}));" | |
] | |
}, | |
"always_comb": { | |
"scope": "systemverilog", | |
"prefix": "always-comb", | |
"body": [ | |
"always_comb begin", | |
"\t$0", | |
"end" | |
] | |
} | |
} |
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{ | |
"for": { | |
"scope": "tcl", | |
"prefix": "for", | |
"body": [ | |
"for {set ${1:i} 0} {\\$i < ${2:length}} {incr i} {", | |
"\t$0", | |
"}" | |
] | |
}, | |
"if": { | |
"scope": "tcl", | |
"prefix": "if", | |
"body": [ | |
"if {$1} {", | |
"\t$0", | |
"}" | |
] | |
}, | |
"if_else": { | |
"scope": "tcl", | |
"prefix": "if-else", | |
"body": [ | |
"if {$1} {", | |
"\t$2", | |
"} else {", | |
"\t$0", | |
"}" | |
] | |
}, | |
"Simulation": { | |
"scope": "tcl", | |
"prefix": "simulation-cfg", | |
"body": [ | |
"set Simulation [\\$Cfg get cadence.simulator.simulation]", | |
"", | |
"\\$Simulation set $0", | |
"", | |
"unset Simulation" | |
] | |
}, | |
"DesignCompilation": { | |
"scope": "tcl", | |
"prefix": "design-compilation-cfg", | |
"body": [ | |
"set DesignCompilation [\\$Cfg get cadence.simulator.designCompilation]", | |
"", | |
"\\$DesignCompilation set $0", | |
"", | |
"unset DesignCompilation" | |
] | |
}, | |
"ModelsCompilation": { | |
"scope": "tcl", | |
"prefix": "models-compilation-cfg", | |
"body": [ | |
"set ModelsCompilation [\\$Cfg get cadence.simulator.modelsCompilation]", | |
"", | |
"\\$ModelsCompilation set $0", | |
"", | |
"unset ModelsCompilation" | |
] | |
}, | |
"TbCompilation": { | |
"scope": "tcl", | |
"prefix": "tb-compilation-cfg", | |
"body": [ | |
"set TbCompilation [\\$Cfg get cadence.simulator.tbCompilation]", | |
"", | |
"\\$TbCompilation set $0", | |
"", | |
"unset TbCompilation" | |
] | |
}, | |
"TbElab": { | |
"scope": "tcl", | |
"prefix": "tb-elab-cfg", | |
"body": [ | |
"set TbElab [\\$Cfg get cadence.simulator.tbElab]", | |
"", | |
"\\$TbElab set $0", | |
"", | |
"unset TbElab" | |
] | |
}, | |
"VmanagerSession": { | |
"scope": "tcl", | |
"prefix": "vmanager-session-cfg", | |
"body": [ | |
"set VmanagerSession [\\$Cfg get cadence.mdv.vmanager.session]", | |
"", | |
"\\$VmanagerSession set $0", | |
"", | |
"unset VmanagerSession" | |
] | |
}, | |
"class": { | |
"scope": "tcl", | |
"prefix": "class", | |
"body": [ | |
"oo::class create ${TM_FILENAME_BASE} {", | |
"\tsuperclass $1", | |
"\t$0", | |
"}" | |
] | |
}, | |
"method": { | |
"scope": "tcl", | |
"prefix": "method", | |
"body": [ | |
"method $0 {} {", | |
"\t", | |
"}" | |
] | |
}, | |
"constructor": { | |
"scope": "tcl", | |
"prefix": "constructor", | |
"body": [ | |
"constructor {$1} {", | |
"\t$0", | |
"}" | |
] | |
}, | |
"namespace": { | |
"scope": "tcl", | |
"prefix": "namespace", | |
"body": [ | |
"namespace eval ${TM_DIRECTORY/^.+[\\/\\\\]+(.*)$/$1/} {", | |
"\tforeach class {", | |
"\t\t$1", | |
"\t} {", | |
"\t\tsource [file join [file dirname [info script]] \\${class}.tcl]", | |
"\t}", | |
"", | |
"\tforeach dir {", | |
"\t\t$0", | |
"\t} {", | |
"\t\t::utils::sourceDir [file join [file dirname [info script]] \\$dir]", | |
"\t}", | |
"}" | |
] | |
}, | |
"namespace-class": { | |
"scope": "tcl", | |
"prefix": "namespace-class", | |
"body": [ | |
"foreach class {", | |
"\t$0", | |
"} {", | |
"\tsource [file join [file dirname [info script]] \\${class}.tcl]", | |
"}", | |
] | |
}, | |
"namespace-procedure": { | |
"scope": "tcl", | |
"prefix": "namespace-procedure", | |
"body": [ | |
"foreach procedure {", | |
"\t$0", | |
"} {", | |
"\tsource [file join [file dirname [info script]] \\${procedure}.tcl]", | |
"}", | |
] | |
}, | |
"namespace-dir": { | |
"scope": "tcl", | |
"prefix": "namespace-dir", | |
"body": [ | |
"foreach dir {", | |
"\t$0", | |
"} {", | |
"\t::utils::sourceDir [file join [file dirname [info script]] \\$dir]", | |
"}", | |
] | |
}, | |
"filename": { | |
"scope": "tcl", | |
"prefix": "filename", | |
"body": [ | |
"${TM_FILENAME_BASE}" | |
] | |
}, | |
} |
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