MemTest.scala

import Chisel._

class MemTest(mem_width: Int = 8, ram_size: Int = 64) extends Module {

  val io = new Bundle {
    val read_value = Bits(width = mem_width).asOutput
    val write_value = Bits(width = mem_width).asInput
    val w_addr = Bits(width = mem_width).asInput
    val r_addr = Bits(width = mem_width).asInput
    val write_enable = Bool(INPUT)
  }

  val ram = Mem(Bits(width = mem_width), ram_size)
  val out = Reg(Bits(width = mem_width))

  io.read_value := out
  when(io.write_enable) {
    ram(io.w_addr) := io.write_value
  }
  when(Bool(true)) {
    out := ram(io.r_addr)
  }
}

object Run {
  def main(args: Array[String]) {
    chiselMain(args, () => Module(new MemTest))
  }
}