gcc port of mspg2xx3_ta_01.asm for the msp430g2553 chip

makefile

#
# Makefile - for TI sample msp430g2xx3_ta_01.asm ported to msp430-gcc
#
# Author: Rick Kimball
# email: rick@kimballsoftware.com
# Version: 1.00 Initial version 10/19/2011

MCU=msp430g2553
CC=msp430-gcc
CXX=msp430-g++
CFLAGS=-mmcu=$(MCU) -Os -Wall -I.
CXXFLAGS=$(CFLAGS)
LDFLAGS=-Wl,-Map,$(TARGET)/$(APP).map -nostdlib -nostartfiles
APP=ta_01
TARGET=.

all: $(TARGET)/$(APP).elf

$(TARGET)/$(APP).elf:  $(TARGET)/$(APP).o
	$(CC) $(CFLAGS) \
		$(TARGET)/$(APP).o \
		$(LDFLAGS) \
		-o $(TARGET)/$(APP).elf
	msp430-objdump -DS $(TARGET)/$(APP).elf >$(TARGET)/$(APP).lss
	msp430-size $(TARGET)/$(APP).elf

$(TARGET)/$(APP).o: $(APP).s
	$(CC) -mmcu=$(MCU) -c -x assembler-with-cpp -Wa,-al=$(TARGET)/$(APP).lss -o $@ $<

install: all
	mspdebug --force-reset rf2500 "prog $(TARGET)/$(APP).elf"

debug:
	msp430-gdb --command=gdb.cmds $(TARGET)/$(APP).elf

clean:
	rm -f $(TARGET)/$(APP).o $(TARGET)/$(APP).elf $(TARGET)/$(APP).lss $(TARGET)/$(APP).map

ta_01.s

;*******************************************************************************
;   MSP430G2xx3 Demo - Timer_A, Toggle P1.0, CCR0 Cont. Mode ISR, DCO SMCLK
;
;   Description: Toggle P1.0 using software and TA_0 ISR. Toggles every
;   1000 SMCLK cycles. SMCLK provides clock source for TACLK.
;   During the TA_0 ISR, P1.0 is toggled and 1000 clock cycles are added to
;   CCR0. TA_0 ISR is triggered every 1000 cycles. CPU is normally off and
;   used only during TA_ISR.
;   ACLK = n/a, MCLK = SMCLK = TACLK = default DCO
;
;                MSP430G2xx3
;             -----------------
;         /|\|              XIN|-
;          | |                 |
;          --|RST          XOUT|-
;            |                 |
;            |             P1.0|-->LED
;
;   D. Dang
;   Texas Instruments Inc.
;   December 2010
;   Built with Code Composer Essentials Version: 4.2.0
; 
;   10/19/2001 Rick Kimball tweaked to work with msp430-gcc
;*******************************************************************************

#include <msp430.h>
#define PC r0  			; gcc doesn't know about PC,SP, or SR
#define SP r1
#define SR r2

            .equ P1_0_MASK,0b00000001       ; P1.0 bit mask
            .equ MATCHCNT,1000              ;
;------------------------------------------------------------------------------
            .text                           ; Program Start
;------------------------------------------------------------------------------
RESET:      mov.w   #__stack,SP             ; Initialize stackpointer (SP == R1)
StopWDT:    mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupP1:    bis.b   #P1_0_MASK,&P1DIR       ; P1.0 output
SetupC0:    mov.w   #CCIE,&CCTL0            ; CCR0 interrupt enabled
            mov.w   #MATCHCNT,&CCR0         ;
SetupTA:    mov.w   #TASSEL_2+MC_2,&TACTL   ; SMCLK, contmode
                                            ;                                           
Mainloop:   bis.w   #CPUOFF+GIE,SR          ; CPU off, interrupts enabled (SR == R2)
            nop                             ; Required only for debugger
                                            ;
;-------------------------------------------------------------------------------
TA0_ISR:;   Toggle P1.0
;-------------------------------------------------------------------------------
            xor.b   #P1_0_MASK,&P1OUT       ; Toggle P1.0
            add.w   #MATCHCNT,&CCR0         ; Add Offset to CCR0
            reti                            ;           

;------------------------------------------------------------------------------
NON_ISR:;   Unexpected ISR handler
;-------------------------------------------------------------------------------
            reti

;------------------------------------------------------------------------------
;           Interrupt Vectors
;------------------------------------------------------------------------------
            .section ".vectors", "ax", @progbits
            .word NON_ISR    ;0xffe0 slot 0
            .word NON_ISR    ;0xffe2 slot 1
            .word NON_ISR    ;0xffe4 slot 2
            .word NON_ISR    ;0xffe6 slot 3
            .word NON_ISR    ;0xffe8 slot 4
            .word NON_ISR    ;0xffea slot 5
            .word NON_ISR    ;0xffec slot 6
            .word NON_ISR    ;0xffee slot 7
            .word NON_ISR    ;0xfff0 slot 8
            .word TA0_ISR    ;0xfff2 slot 9
            .word NON_ISR    ;0xfff4 slot 10
            .word NON_ISR    ;0xfff6 slot 11
            .word NON_ISR    ;0xfff8 slot 12
            .word NON_ISR    ;0xfffa slot 13
            .word NON_ISR    ;0xfffc slot 14
            .word RESET      ;0xfffe slot 15
            .end