commands.txt

[clever@amd-nixos:~/apps/audiorig]$ ./iverilog/bin/iverilog testbench.v wiznet_control.v wiznet_parallel.v 
[clever@amd-nixos:~/apps/audiorig]$ ls -ltrh
-rwxr-xr-x 1 clever users  35K Nov  4 19:51 a.out
[clever@amd-nixos:~/apps/audiorig]$ ./a.out
-rw-r--r-- 1 clever users  25M Nov  4 19:52 simple.vcd
[clever@amd-nixos:~/apps/audiorig]$ nix-build '<nixpkgs>' -A gtkwave -o gtkwave
[clever@amd-nixos:~/apps/audiorig]$ ./gtkwave/bin/gtkwave simple.vcd 

https://imgur.com/a/dJnf9tU

testbench.v

`timescale 1ns / 1ns
module testbench ();
	initial
     begin
        $dumpfile("simple.vcd");
        $dumpvars(0, main);
        //$monitor("state is %b, counter is %b, sub_state:%b.", state,counter,sub_state);
        #10004000 $finish; // just over 10ms
     end
	
reg clk = 0;
	
always begin
   #10  clk = ~clk; // Toggle clock every 10 ticks
end

wiznet_control main(
	.clk(clk)
);
endmodule