Created
April 16, 2011 02:23
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ding! ding! ding!
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| /* iverilog output 0.9.2 | |
| ding! ding! | |
| ding! | |
| ding! ding! | |
| ding! | |
| */ | |
| /* vcs output | |
| ding! | |
| ding! ding! | |
| */ | |
| /* expected (?) | |
| ding! | |
| ding! ding! | |
| ding! | |
| */ | |
| module m; | |
| wire [3:0] x; | |
| reg [3:0] y; | |
| assign #0 x = y; | |
| always @(y == 4'b1010) | |
| $display("ding!"); | |
| always @(x == 4'b1010) | |
| $display("ding! ding!"); | |
| initial | |
| begin | |
| #1; | |
| y = 4'b0000; | |
| #1; | |
| y = 4'b1010; | |
| y = 4'b1111; | |
| end | |
| endmodule |
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