Atheros ART power limit bypass, linux regulatory will be applied (e.g.: iw phy phy0 set txpower fixed 3100)

800-ath9k-bypass-eeprom-power.patch

--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -5142,6 +5142,11 @@ static void ar9003_hw_set_power_per_rate
 	scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
 						antenna_reduction);
 
+	minCtlPower = (u8) min(MAX_RATE_POWER, scaledPower);
+	for (i = 0; i < ar9300RateSize; i++)
+		pPwrArray[i] = (u8) minCtlPower;
+	return;
+
 	if (is2ghz) {
 		/* Setup for CTL modes */
 		/* CTL_11B, CTL_11G, CTL_2GHT20 */

ar9003_eeprom_power_mod.c

static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
					       struct ath9k_channel *chan,
					       u8 *pPwrArray, u16 cfgCtl,
					       u8 antenna_reduction,
					       u16 powerLimit)
{
	struct ath_common *common = ath9k_hw_common(ah);
	struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
	u16 twiceMaxEdgePower;
	int i;
	u16 scaledPower = 0, minCtlPower;
	static const u16 ctlModesFor11a[] = {
		CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
	};
	static const u16 ctlModesFor11g[] = {
		CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
		CTL_11G_EXT, CTL_2GHT40
	};
	u16 numCtlModes;
	const u16 *pCtlMode;
	u16 ctlMode, freq;
	struct chan_centers centers;
	u8 *ctlIndex;
	u8 ctlNum;
	u16 twiceMinEdgePower;
	bool is2ghz = IS_CHAN_2GHZ(chan);

	ath9k_hw_get_channel_centers(ah, chan, &centers);
	scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
						antenna_reduction);
  
  	minCtlPower = (u8) min(MAX_RATE_POWER, scaledPower);   // [MOD]
	for (i = 0; i < ar9300RateSize; i++)                   // [MOD]
		pPwrArray[i] = (u8) minCtlPower;               // [MOD]
	return;                                                // [MOD]
  
	if (is2ghz) {

// [...]

kmod-ath9k_5.4.52+5.8-1-1_mips_24kc.ipk is working fine, but some channels on 5 ghz are only 14 dBm
44, 48, 52, 56, 60, 64
is there a way to fix that?