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May 29, 2016 02:43
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#include "nrf24l01.h" | |
#define _XTAL_FREQ 16000000 | |
void nrf24l01_initialize(unsigned char config, | |
unsigned char opt_rx_active_mode, | |
unsigned char en_aa, | |
unsigned char en_rxaddr, | |
unsigned char setup_aw, | |
unsigned char setup_retr, | |
unsigned char rf_ch, | |
unsigned char rf_setup, | |
unsigned char * rx_addr_p0, | |
unsigned char * rx_addr_p1, | |
unsigned char rx_addr_p2, | |
unsigned char rx_addr_p3, | |
unsigned char rx_addr_p4, | |
unsigned char rx_addr_p5, | |
unsigned char * tx_addr, | |
unsigned char rx_pw_p0, | |
unsigned char rx_pw_p1, | |
unsigned char rx_pw_p2, | |
unsigned char rx_pw_p3, | |
unsigned char rx_pw_p4, | |
unsigned char rx_pw_p5) | |
{ | |
unsigned char data[5]; | |
data[0] = en_aa; | |
nrf24l01_write_register(nrf24l01_EN_AA, data, 1); | |
data[0] = en_rxaddr; | |
nrf24l01_write_register(nrf24l01_EN_RXADDR, data, 1); | |
data[0] = setup_aw; | |
nrf24l01_write_register(nrf24l01_SETUP_AW, data, 1); | |
data[0] = setup_retr; | |
nrf24l01_write_register(nrf24l01_SETUP_RETR, data, 1); | |
data[0] = rf_ch; | |
nrf24l01_write_register(nrf24l01_RF_CH, data, 1); | |
data[0] = rf_setup; | |
nrf24l01_write_register(nrf24l01_RF_SETUP, data, 1); | |
if(rx_addr_p0 != NULL) | |
nrf24l01_set_rx_addr(rx_addr_p0, 5, 0); | |
else | |
{ | |
data[0] = nrf24l01_RX_ADDR_P0_B0_DEFAULT_VAL; | |
data[1] = nrf24l01_RX_ADDR_P0_B1_DEFAULT_VAL; | |
data[2] = nrf24l01_RX_ADDR_P0_B2_DEFAULT_VAL; | |
data[3] = nrf24l01_RX_ADDR_P0_B3_DEFAULT_VAL; | |
data[4] = nrf24l01_RX_ADDR_P0_B4_DEFAULT_VAL; | |
nrf24l01_set_rx_addr(data, 5, 0); | |
} | |
if(rx_addr_p1 != NULL) | |
nrf24l01_set_rx_addr(rx_addr_p1, 5, 1); | |
else | |
{ | |
data[0] = nrf24l01_RX_ADDR_P1_B0_DEFAULT_VAL; | |
data[1] = nrf24l01_RX_ADDR_P1_B1_DEFAULT_VAL; | |
data[2] = nrf24l01_RX_ADDR_P1_B2_DEFAULT_VAL; | |
data[3] = nrf24l01_RX_ADDR_P1_B3_DEFAULT_VAL; | |
data[4] = nrf24l01_RX_ADDR_P1_B4_DEFAULT_VAL; | |
nrf24l01_set_rx_addr(data, 5, 1); | |
} | |
data[0] = rx_addr_p2; | |
nrf24l01_set_rx_addr(data, 1, 2); | |
data[0] = rx_addr_p3; | |
nrf24l01_set_rx_addr(data, 1, 3); | |
data[0] = rx_addr_p4; | |
nrf24l01_set_rx_addr(data, 1, 4); | |
data[0] = rx_addr_p5; | |
nrf24l01_set_rx_addr(data, 1, 5); | |
if(tx_addr != NULL) | |
nrf24l01_set_tx_addr(tx_addr, 5); | |
else | |
{ | |
data[0] = nrf24l01_TX_ADDR_B0_DEFAULT_VAL; | |
data[1] = nrf24l01_TX_ADDR_B1_DEFAULT_VAL; | |
data[2] = nrf24l01_TX_ADDR_B2_DEFAULT_VAL; | |
data[3] = nrf24l01_TX_ADDR_B3_DEFAULT_VAL; | |
data[4] = nrf24l01_TX_ADDR_B4_DEFAULT_VAL; | |
nrf24l01_set_tx_addr(data, 5); | |
} | |
data[0] = rx_pw_p0; | |
nrf24l01_write_register(nrf24l01_RX_PW_P0, data, 1); | |
data[0] = rx_pw_p1; | |
nrf24l01_write_register(nrf24l01_RX_PW_P1, data, 1); | |
data[0] = rx_pw_p2; | |
nrf24l01_write_register(nrf24l01_RX_PW_P2, data, 1); | |
data[0] = rx_pw_p3; | |
nrf24l01_write_register(nrf24l01_RX_PW_P3, data, 1); | |
data[0] = rx_pw_p4; | |
nrf24l01_write_register(nrf24l01_RX_PW_P4, data, 1); | |
data[0] = rx_pw_p5; | |
nrf24l01_write_register(nrf24l01_RX_PW_P5, data, 1); | |
if((config & nrf24l01_CONFIG_PWR_UP) != 0) | |
nrf24l01_power_up_param(opt_rx_active_mode, config); | |
else | |
nrf24l01_power_down_param(config); | |
} | |
void nrf24l01_initialize_debug(bool rx, unsigned char p0_payload_width, bool enable_auto_ack) | |
{ | |
unsigned char config; | |
unsigned char en_aa; | |
config = nrf24l01_CONFIG_DEFAULT_VAL | nrf24l01_CONFIG_PWR_UP; | |
if(enable_auto_ack != false) | |
en_aa = nrf24l01_EN_AA_ENAA_P0; | |
else | |
en_aa = nrf24l01_EN_AA_ENAA_NONE; | |
if(rx == true) | |
config = config | nrf24l01_CONFIG_PRIM_RX; | |
nrf24l01_initialize(config, | |
true, | |
en_aa, | |
nrf24l01_EN_RXADDR_DEFAULT_VAL, | |
nrf24l01_SETUP_AW_DEFAULT_VAL, | |
nrf24l01_SETUP_RETR_DEFAULT_VAL, | |
nrf24l01_RF_CH_DEFAULT_VAL, | |
nrf24l01_RF_SETUP_DEFAULT_VAL, | |
NULL, | |
NULL, | |
nrf24l01_RX_ADDR_P2_DEFAULT_VAL, | |
nrf24l01_RX_ADDR_P3_DEFAULT_VAL, | |
nrf24l01_RX_ADDR_P4_DEFAULT_VAL, | |
nrf24l01_RX_ADDR_P5_DEFAULT_VAL, | |
NULL, | |
p0_payload_width, | |
nrf24l01_RX_PW_P1_DEFAULT_VAL, | |
nrf24l01_RX_PW_P2_DEFAULT_VAL, | |
nrf24l01_RX_PW_P3_DEFAULT_VAL, | |
nrf24l01_RX_PW_P4_DEFAULT_VAL, | |
nrf24l01_RX_PW_P5_DEFAULT_VAL); | |
} | |
void nrf24l01_initialize_debug_lite(bool rx, unsigned char p0_payload_width) | |
{ | |
unsigned char config; | |
config = nrf24l01_CONFIG_DEFAULT_VAL; | |
if(rx != false) | |
config |= nrf24l01_CONFIG_PRIM_RX; | |
nrf24l01_write_register(nrf24l01_RX_PW_P0, &p0_payload_width, 1); | |
nrf24l01_power_up_param(true, config); | |
} | |
void nrf24l01_power_up(bool rx_active_mode) | |
{ | |
unsigned char config; | |
nrf24l01_read_register(nrf24l01_CONFIG, &config, 1); | |
if((config & nrf24l01_CONFIG_PWR_UP) != 0) | |
return; | |
config |= nrf24l01_CONFIG_PWR_UP; | |
nrf24l01_write_register(nrf24l01_CONFIG, &config, 1); | |
__delay_ms(1.5); | |
if((config & nrf24l01_CONFIG_PRIM_RX) == 0) | |
nrf24l01_clear_ce(); | |
else | |
{ | |
if(rx_active_mode != false) | |
nrf24l01_set_ce(); | |
else | |
nrf24l01_clear_ce(); | |
} | |
} | |
void nrf24l01_power_up_param(bool rx_active_mode, unsigned char config) | |
{ | |
unsigned char test, test2; | |
config |= nrf24l01_CONFIG_PWR_UP; | |
nrf24l01_write_register(nrf24l01_CONFIG, &config, 1); | |
__delay_us(1.5); | |
if((config & nrf24l01_CONFIG_PRIM_RX) == 0) | |
nrf24l01_clear_ce(); | |
else | |
{ | |
if(rx_active_mode != false) | |
nrf24l01_set_ce(); | |
else | |
nrf24l01_clear_ce(); | |
} | |
} | |
void nrf24l01_power_down() | |
{ | |
unsigned char config; | |
nrf24l01_read_register(nrf24l01_CONFIG, &config, 1); | |
if((config & nrf24l01_CONFIG_PWR_UP) == 0) | |
return; | |
config &= (~nrf24l01_CONFIG_PWR_UP); | |
nrf24l01_write_register(nrf24l01_CONFIG, &config, 1); | |
nrf24l01_clear_ce(); | |
} | |
void nrf24l01_power_down_param(unsigned char config) | |
{ | |
config &= (~nrf24l01_CONFIG_PWR_UP); | |
nrf24l01_write_register(nrf24l01_CONFIG, &config, 1); | |
nrf24l01_clear_ce(); | |
} | |
void nrf24l01_set_as_rx(bool rx_active_mode) | |
{ | |
unsigned char config; | |
unsigned char status; | |
status = nrf24l01_read_register(0, &config, 1); | |
if((config & nrf24l01_CONFIG_PRIM_RX) != 0) | |
return; | |
config |= nrf24l01_CONFIG_PRIM_RX; | |
nrf24l01_write_register(nrf24l01_CONFIG, &config, 1); | |
if(rx_active_mode != false) | |
nrf24l01_set_ce(); | |
else | |
nrf24l01_clear_ce(); | |
} | |
void nrf24l01_set_as_rx_param(bool rx_active_mode, unsigned char config) | |
{ | |
config |= nrf24l01_CONFIG_PRIM_RX; | |
if((config & nrf24l01_CONFIG_PWR_UP) != 0) | |
nrf24l01_power_up_param(rx_active_mode, config); | |
else | |
nrf24l01_power_down_param(config); | |
} | |
void nrf24l01_rx_standby_to_active() | |
{ | |
nrf24l01_set_ce(); | |
} | |
void nrf24l01_rx_active_to_standby() | |
{ | |
nrf24l01_clear_ce(); | |
} | |
void nrf24l01_set_as_tx() | |
{ | |
unsigned char config; | |
nrf24l01_read_register(nrf24l01_CONFIG, &config, 1); | |
if((config & nrf24l01_CONFIG_PRIM_RX) == 0) | |
return; | |
config &= (~nrf24l01_CONFIG_PRIM_RX); | |
nrf24l01_write_register(nrf24l01_CONFIG, &config, 1); | |
nrf24l01_clear_ce(); | |
} | |
void nrf24l01_set_as_tx_param(unsigned char config) | |
{ | |
config &= ~(nrf24l01_CONFIG_PRIM_RX); | |
if((config & nrf24l01_CONFIG_PWR_UP) != 0) | |
nrf24l01_power_up_param(false, config); | |
else | |
nrf24l01_power_down_param(config); | |
} | |
unsigned char nrf24l01_write_register(unsigned char regnumber, unsigned char * data, unsigned int len) | |
{ | |
return nrf24l01_execute_command(nrf24l01_W_REGISTER | (regnumber & nrf24l01_W_REGISTER_DATA), data, len, false); | |
} | |
unsigned char nrf24l01_read_register(unsigned char regnumber, unsigned char * data, unsigned int len) | |
{ | |
return nrf24l01_execute_command(regnumber & nrf24l01_R_REGISTER_DATA, data, len, true); | |
} | |
unsigned char nrf24l01_write_tx_payload(unsigned char * data, unsigned int len, bool transmit) | |
{ | |
unsigned char status; | |
status = nrf24l01_execute_command(nrf24l01_W_TX_PAYLOAD, data, len, false); | |
if(transmit == true) | |
nrf24l01_transmit(); | |
return status; | |
} | |
unsigned char nrf24l01_read_rx_payload(unsigned char * data, unsigned int len) | |
{ | |
unsigned char status; | |
nrf24l01_clear_ce(); | |
status = nrf24l01_execute_command(nrf24l01_R_RX_PAYLOAD, data, len, true); | |
nrf24l01_set_ce(); | |
return status; | |
} | |
unsigned char nrf24l01_flush_tx() | |
{ | |
return nrf24l01_execute_command(nrf24l01_FLUSH_TX, NULL, 0, true); | |
} | |
unsigned char nrf24l01_flush_rx() | |
{ | |
return nrf24l01_execute_command(nrf24l01_FLUSH_RX, NULL, 0, true); | |
} | |
unsigned char nrf24l01_reuse_tx_pl() | |
{ | |
return nrf24l01_execute_command(nrf24l01_REUSE_TX_PL, NULL, 0, true); | |
} | |
unsigned char nrf24l01_nop() | |
{ | |
return nrf24l01_execute_command(nrf24l01_NOP, NULL, 0, true); | |
} | |
void nrf24l01_transmit() | |
{ | |
nrf24l01_set_ce(); | |
__delay_us(10); | |
nrf24l01_clear_ce(); | |
} | |
void nrf24l01_clear_ce() | |
{ | |
nrf24l01_CE_IOREGISTER &= ~nrf24l01_CE_PINMASK; | |
} | |
void nrf24l01_set_ce() | |
{ | |
nrf24l01_CE_IOREGISTER |= nrf24l01_CE_PINMASK; | |
} | |
bool nrf24l01_ce_pin_active() | |
{ | |
if((nrf24l01_CE_IOREGISTER & nrf24l01_CE_PINMASK) != 0) | |
return true; | |
else | |
return false; | |
} | |
void nrf24l01_clear_csn() | |
{ | |
nrf24l01_CSN_IOREGISTER &= ~nrf24l01_CSN_PINMASK; | |
} | |
void nrf24l01_set_csn() | |
{ | |
nrf24l01_CSN_IOREGISTER |= nrf24l01_CSN_PINMASK; | |
} | |
bool nrf24l01_csn_pin_active() | |
{ | |
if((nrf24l01_CSN_IOREGISTER & nrf24l01_CSN_PINMASK) != 0) | |
return true; | |
else | |
return false; | |
} | |
void nrf24l01_set_tx_addr(unsigned char * address, unsigned int len) | |
{ | |
nrf24l01_write_register(nrf24l01_TX_ADDR, address, len); | |
} | |
void nrf24l01_set_rx_addr(unsigned char * address, unsigned int len, unsigned char rxpipenum) | |
{ | |
if(rxpipenum > 5) | |
return; | |
nrf24l01_write_register(nrf24l01_RX_ADDR_P0 + rxpipenum, address, len); | |
} | |
void nrf24l01_set_rx_pw(unsigned char payloadwidth, unsigned char rxpipenum) | |
{ | |
if((rxpipenum > 5) || (payloadwidth > 32)) | |
return; | |
nrf24l01_write_register(nrf24l01_RX_PW_P0 + rxpipenum, &payloadwidth, 1); | |
} | |
unsigned char nrf24l01_get_rx_pw(unsigned char rxpipenum) | |
{ | |
unsigned char data; | |
if((rxpipenum > 5)) | |
return 0; | |
nrf24l01_read_register(nrf24l01_RX_PW_P0 + rxpipenum, &data, 1); | |
return data; | |
} | |
unsigned char nrf24l01_get_config() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_CONFIG, &data, 1); | |
return data; | |
} | |
void nrf24l01_set_config(unsigned char config) | |
{ | |
nrf24l01_write_register(nrf24l01_CONFIG, &config, 1); | |
} | |
unsigned char nrf24l01_get_rf_ch() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_RF_CH, &data, 1); | |
return data; | |
} | |
void nrf24l01_set_rf_ch(unsigned char channel) | |
{ | |
unsigned char data; | |
data = channel & ~nrf24l01_RF_CH_RESERVED; | |
nrf24l01_write_register(nrf24l01_RF_CH, &data, 1); | |
} | |
unsigned char nrf24l01_get_observe_tx() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_OBSERVE_TX, &data, 1); | |
return data; | |
} | |
unsigned char nrf24l01_get_plos_cnt() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_OBSERVE_TX, &data, 1); | |
return ((data & nrf24l01_OBSERVE_TX_PLOS_CNT) >> 4); | |
} | |
void nrf24l01_clear_plos_cnt() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_RF_CH, &data, 1); | |
nrf24l01_write_register(nrf24l01_RF_CH, &data, 1); | |
} | |
void nrf24l01_clear_plos_cnt_param(unsigned char rf_ch) | |
{ | |
nrf24l01_write_register(nrf24l01_RF_CH, &rf_ch, 1); | |
} | |
unsigned char nrf24l01_get_arc_cnt() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_OBSERVE_TX, &data, 1); | |
return (data & nrf24l01_OBSERVE_TX_ARC_CNT); | |
} | |
bool nrf24l01_aa_enabled(unsigned char rxpipenum) | |
{ | |
unsigned char data; | |
if(rxpipenum > 5) | |
return false; | |
nrf24l01_read_register(nrf24l01_EN_AA, &data, 1); | |
return (data & (0x01 << rxpipenum)); | |
} | |
void nrf24l01_aa_enable(unsigned char rxpipenum) | |
{ | |
unsigned char data; | |
if(rxpipenum > 5) | |
return; | |
nrf24l01_read_register(nrf24l01_EN_AA, &data, 1); | |
if((data & (0x01 << rxpipenum)) != 0) | |
return; | |
data |= 0x01 << rxpipenum; | |
nrf24l01_write_register(nrf24l01_EN_AA, &data, 1); | |
} | |
void nrf24l01_aa_disable(unsigned char rxpipenum) | |
{ | |
unsigned char data; | |
if(rxpipenum > 5) | |
return; | |
nrf24l01_read_register(nrf24l01_EN_AA, &data, 1); | |
if((data & (0x01 << rxpipenum)) == 0) | |
return; | |
data &= ~(0x01 << rxpipenum); | |
nrf24l01_write_register(nrf24l01_EN_AA, &data, 1); | |
} | |
bool nrf24l01_rx_pipe_enabled(unsigned char rxpipenum) | |
{ | |
unsigned char data; | |
if((rxpipenum > 5)) | |
return false; | |
nrf24l01_read_register(nrf24l01_EN_RXADDR, &data, 1); | |
return (data & (0x01 << rxpipenum)); | |
} | |
void nrf24l01_rx_pipe_enable(unsigned char rxpipenum) | |
{ | |
unsigned char data; | |
if(rxpipenum > 5) | |
return; | |
nrf24l01_read_register(nrf24l01_EN_RXADDR, &data, 1); | |
if((data & (0x01 << rxpipenum)) != 0) | |
return; | |
data |= 0x01 << rxpipenum; | |
nrf24l01_write_register(nrf24l01_EN_RXADDR, &data, 1); | |
} | |
void nrf24l01_rx_pipe_disable(unsigned char rxpipenum) | |
{ | |
unsigned char data; | |
if(rxpipenum > 5) | |
return; | |
nrf24l01_read_register(nrf24l01_EN_RXADDR, &data, 1); | |
if((data & (0x01 << rxpipenum)) == 0) | |
return; | |
data &= ~(0x01 << rxpipenum); | |
nrf24l01_write_register(nrf24l01_EN_RXADDR, &data, 1); | |
} | |
bool nrf24l01_cd_active() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_CD, &data, 1); | |
return data; | |
} | |
unsigned char nrf24l01_get_fifo_status() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_FIFO_STATUS, &data, 1); | |
return data; | |
} | |
unsigned char nrf24l01_get_status() | |
{ | |
return nrf24l01_nop(); | |
} | |
bool nrf24l01_fifo_tx_reuse() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_FIFO_STATUS, &data, 1); | |
return (bool)(data & nrf24l01_FIFO_STATUS_TX_REUSE); | |
} | |
bool nrf24l01_fifo_tx_full() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_FIFO_STATUS, &data, 1); | |
return (bool)(data & nrf24l01_FIFO_STATUS_TX_FULL); | |
} | |
bool nrf24l01_fifo_tx_empty() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_FIFO_STATUS, &data, 1); | |
return (bool)(data & nrf24l01_FIFO_STATUS_TX_EMPTY); | |
} | |
bool nrf24l01_fifo_rx_full() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_FIFO_STATUS, &data, 1); | |
return (bool)(data & nrf24l01_FIFO_STATUS_RX_FULL); | |
} | |
bool nrf24l01_fifo_rx_empty() | |
{ | |
unsigned char data; | |
nrf24l01_read_register(nrf24l01_FIFO_STATUS, &data, 1); | |
return (bool)(data & nrf24l01_FIFO_STATUS_RX_EMPTY); | |
} | |
bool nrf24l01_irq_pin_active() | |
{ | |
if((nrf24l01_IRQ_IOREGISTER & nrf24l01_IRQ_PINMASK) != 0) | |
return false; | |
else | |
return true; | |
} | |
bool nrf24l01_irq_rx_dr_active() | |
{ | |
return (nrf24l01_get_status() & nrf24l01_STATUS_RX_DR); | |
} | |
bool nrf24l01_irq_tx_ds_active() | |
{ | |
return (nrf24l01_get_status() & nrf24l01_STATUS_TX_DS); | |
} | |
bool nrf24l01_irq_max_rt_active() | |
{ | |
return (nrf24l01_get_status() & nrf24l01_STATUS_MAX_RT); | |
} | |
void nrf24l01_irq_clear_all() | |
{ | |
unsigned char data = nrf24l01_STATUS_RX_DR | nrf24l01_STATUS_TX_DS | nrf24l01_STATUS_MAX_RT; | |
nrf24l01_write_register(nrf24l01_STATUS, &data, 1); | |
} | |
void nrf24l01_irq_clear_rx_dr() | |
{ | |
unsigned char data = nrf24l01_STATUS_RX_DR; | |
nrf24l01_write_register(nrf24l01_STATUS, &data, 1); | |
} | |
void nrf24l01_irq_clear_tx_ds() | |
{ | |
unsigned char data = nrf24l01_STATUS_TX_DS; | |
nrf24l01_write_register(nrf24l01_STATUS, &data, 1); | |
} | |
void nrf24l01_irq_clear_max_rt() | |
{ | |
unsigned char data = nrf24l01_STATUS_MAX_RT; | |
nrf24l01_write_register(nrf24l01_STATUS, &data, 1); | |
} | |
unsigned char nrf24l01_get_rx_pipe() | |
{ | |
return nrf24l01_get_rx_pipe_from_status(nrf24l01_get_status()); | |
} | |
unsigned char nrf24l01_get_rx_pipe_from_status(unsigned char status) | |
{ | |
return ((status & 0xE) >> 1); | |
} | |
void nrf24l01_clear_flush() | |
{ | |
nrf24l01_flush_rx(); | |
nrf24l01_flush_tx(); | |
nrf24l01_irq_clear_all(); | |
} | |
void nrf24l01_get_all_registers(unsigned char * data) | |
{ | |
unsigned int outer; | |
unsigned int inner; | |
unsigned int dataloc = 0; | |
unsigned char buffer[5]; | |
for(outer = 0; outer <= 0x17; outer++) | |
{ | |
nrf24l01_read_register(outer, buffer, 5); | |
for(inner = 0; inner < 5; inner++) | |
{ | |
if(inner >= 1 && (outer != 0x0A && outer != 0x0B && outer != 0x10)) | |
break; | |
data[dataloc] = buffer[inner]; | |
dataloc++; | |
} | |
} | |
} | |
unsigned char nrf24l01_execute_command(unsigned char instruction, unsigned char * data, unsigned int len, bool copydata) | |
{ | |
unsigned char status; | |
nrf24l01_clear_csn(); | |
status = instruction; | |
nrf24l01_spi_send_read(&status, 1, true); | |
nrf24l01_spi_send_read(data, len, copydata); | |
nrf24l01_set_csn(); | |
return status; | |
} | |
void nrf24l01_spi_send_read(unsigned char * data, unsigned int len, bool copydata) | |
{ | |
unsigned int count; | |
unsigned char tempbyte; | |
for(count = 0; count < len; count++) | |
{ | |
if(copydata != false) | |
data[count] = spi_send_read_byte(data[count]); | |
else | |
{ | |
tempbyte = data[count]; | |
spi_send_read_byte(tempbyte); | |
} | |
} | |
} | |
#include <plib/spi.h> | |
#include <p18f452.h> | |
unsigned char spi1_send_read_byte(unsigned char byte) | |
{ | |
SSPBUF = byte; | |
while(!SSP1STATbits.BF); | |
return SSPBUF; | |
} | |
#include <stdio.h> | |
#include <stdlib.h> | |
#include <xc.h> | |
#include "spi1.h" | |
#include "nrf24l01.h" | |
#include <p18F26K22.h> | |
#define _XTAL_FREQ 16000000 | |
#pragma config FOSC = INTIO67 | |
#pragma config PLLCFG = OFF | |
#pragma config PRICLKEN = OFF | |
#pragma config FCMEN = OFF | |
#pragma config PWRTEN = OFF | |
#pragma config BOREN = ON | |
#pragma config BORV = 220 | |
#pragma config WDTEN = OFF | |
#pragma config WDTPS = 32768 | |
#pragma config CCP2MX = PORTB3 | |
#pragma config PBADEN = OFF | |
#pragma config CCP3MX = PORTB5 | |
#pragma config HFOFST = OFF | |
#pragma config T3CMX = PORTC0 | |
#pragma config P2BMX = PORTC0 | |
#pragma config MCLRE = EXTMCLR | |
#pragma config LVP = OFF | |
#pragma config XINST = OFF | |
#pragma config CP0 = OFF | |
#pragma config CP1 = OFF | |
#pragma config CP2 = OFF | |
#pragma config CP3 = OFF | |
#pragma config CPB = OFF | |
#pragma config CPD = OFF | |
#pragma config WRT0 = ON | |
#pragma config WRT1 = ON | |
#pragma config WRT2 = ON | |
#pragma config WRT3 = ON | |
#pragma config WRTC = ON | |
#pragma config WRTB = ON | |
#pragma config WRTD = ON | |
#pragma config EBTR0 = OFF | |
#pragma config EBTR1 = OFF | |
#pragma config EBTR2 = OFF | |
#pragma config EBTR3 = OFF | |
#pragma config EBTRB = OFF | |
void Initialise(void); | |
void InitialiseIO(void); | |
void testingByte(unsigned char); | |
void main() | |
{ | |
unsigned char data[5]={0,0,0,0,0}; | |
unsigned char fifo; | |
unsigned char rxPipe; | |
Initialise(); | |
while(1){ | |
nrf24l01_flush_rx(); | |
nrf24l01_flush_tx(); | |
nrf24l01_irq_clear_all(); | |
while(!nrf24l01_irq_rx_dr_active()){LATAbits.LATA1=1;} | |
LATAbits.LATA1=0; | |
nrf24l01_read_rx_payload(&data, 3); | |
nrf24l01_irq_clear_all(); | |
LATAbits.LATA2=1; | |
while(1); | |
} | |
} | |
void Initialise(){ | |
unsigned char data; | |
InitialiseIO(); | |
SSPSTAT = 0xC0; //SPI Bus mode 0,0 | |
SSPCON1 = 0x20; //Enable SSP, Fosc/16 | |
nrf24l01_initialize_debug(true,3,true); //initialise 24l01 to the debug config as RX, 1 data byte, and auto-ack disabled | |
LATAbits.LATA0=1; | |
for (int i=0;i<25;i++)__delay_ms(20); | |
LATAbits.LATA0=0; | |
for (int i=0;i<25;i++)__delay_ms(20); | |
} | |
void InitialiseIO(){ | |
OSCCON=0B11110000; //sets the IRCF selecting the 16MHz INTOSC and SCS=primary clock | |
OSCCON2=0B00000000; //sets MFIOSEL=0 and PRISD=0 turn off external osc drive circuit | |
LATA=0; | |
TRISA=0; | |
TRISB0=1; | |
TRISCbits.TRISC1=0; | |
DDRCbits.RC2 = 0; //Define CS as Output | |
DDRCbits.RC3 = 0; //Define SCK as Output | |
DDRCbits.RC4 = 1; //Define SDI as Input | |
DDRCbits.RC5 = 0; //Define SDO as Output | |
PORTC=0x04;//SET CSN bit | |
ANSELA=0; | |
ANSELB=0; | |
ANSELC=0; | |
} | |
void testingByte(unsigned char temp){ | |
if((temp&0x01)!=0){LATAbits.LATA7=1;} | |
if((temp&0x02)!=0){LATAbits.LATA6=1;} | |
if((temp&0x04)!=0){LATAbits.LATA5=1;} | |
if((temp&0x08)!=0){LATAbits.LATA4=1;} | |
if((temp&0x10)!=0){LATAbits.LATA3=1;} | |
if((temp&0x20)!=0){LATAbits.LATA2=1;} | |
if((temp&0x40)!=0){LATAbits.LATA1=1;} | |
if((temp&0x80)!=0){LATAbits.LATA0=1;} | |
} | |
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