flash_glitch.v

`timescale 1ns / 1ps

module test1(
    input clk_leeched,
    output glitch_out,
    output led_out,
    input glitch_en
    );
    
    reg[8:0] r;
    reg glitch_out_r;
    reg led_out_r;
    reg[8:0] glitch_next_8_bytes;
    
    assign glitch_out = glitch_out_r;
    assign led_out = led_out_r;
    
    initial
    begin
        r <= 0;
        glitch_out_r <= 0;
        led_out_r <= 0;
        glitch_next_8_bytes <= 0;
    end
    
    always @(posedge clk_leeched)
    begin
        if (glitch_en == 1)
        begin
            r <= r + 1;
        end
        if (r == (25 + 36 * 8) && glitch_next_8_bytes == 0)
        begin
            glitch_next_8_bytes <= 20;
        end
        if (glitch_next_8_bytes > 1)
        begin
            glitch_out_r <= glitch_en;
            glitch_next_8_bytes <= glitch_next_8_bytes - 1;
        end
        else
        begin
            glitch_out_r <= 0;
        end
    end
    
    always @(posedge glitch_out_r)
    begin
        led_out_r <= 1 - led_out_r;
    end
    
endmodule