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Blackbox spec for dual-port block RAM
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY blockramwrapper IS
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR;
data_b : IN STD_LOGIC_VECTOR;
q_a : OUT STD_LOGIC_VECTOR;
wren_b : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR;
data_a : IN STD_LOGIC_VECTOR;
q_b : OUT STD_LOGIC_VECTOR
);
END blockramwrapper;
ARCHITECTURE SYN OF blockramwrapper IS
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR;
data_b : IN STD_LOGIC_VECTOR;
q_a : OUT STD_LOGIC_VECTOR;
wren_b : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR;
data_a : IN STD_LOGIC_VECTOR;
q_b : OUT STD_LOGIC_VECTOR
);
END COMPONENT;
BEGIN
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => address_reg_b,
clock_enable_input_a => clock_enable_input_a,
clock_enable_input_b => clock_enable_input_b,
clock_enable_output_a => clock_enable_output_a,
clock_enable_output_b => clock_enable_output_b,
indata_reg_b => indata_reg_b,
intended_device_family => intended_device_family,
lpm_type => lpm_type,
numwords_a => numwords_a,
numwords_b => numwords_b,
operation_mode => operation_mode,
outdata_aclr_a => outdata_aclr_a,
outdata_aclr_b => outdata_aclr_b,
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_b,
power_up_uninitialized => power_up_uninitialized,
ram_block_type => ram_block_type,
read_during_write_mode_mixed_ports => read_during_write_mode_mixed_ports,
read_during_write_mode_port_a => read_during_write_mode_port_a,
read_during_write_mode_port_b => read_during_write_mode_port_b,
widthad_a => widthad_a,
widthad_b => widthad_b,
width_a => width_a,
width_b => width_b,
width_byteena_a => width_byteena_a,
width_byteena_b => width_byteena_b,
wrcontrol_wraddress_reg_b => wrcontrol_wraddress_reg_b
)
PORT MAP (
clock0 => clock0,
wren_a => wren_a,
address_b => address_b,
data_b => data_b,
wren_b => wren_b,
address_a => address_a,
data_a => data_a,
q_a => q_a,
q_b => q_b
);
END SYN;
[ { "BlackBox" :
{ "name" : "Toolbox.Blockram2p.blockram2p'"
, "type" :
"blockram2p' :: ( BitPack a -- LIT[0]
, BitPack b -- LIT[1]
, KnownNat (BitSize a) -- LIT[2]
, KnownNat (BitSize b) -- LIT[3]
, KnownNat logaw -- LIT[4]
, KnownNat logbw -- LIT[5]
, KnownNat aaw -- LIT[6]
, KnownNat baw -- LIT[7]
, KnownNat memw -- LIT[8]
, ((2 ^ logaw) ~ BitSize a) -- LIT[9]
, ((2 ^ logbw) ~ BitSize b) -- LIT[10]
, KnownNat (2 ^ aaw) -- LIT[11]
, KnownNat (2 ^ baw) -- LIT[12]
, (memw ~ ((2 ^ aaw) * BitSize a)) -- LIT[13]
, (memw ~ ((2 ^ baw) * BitSize b))) -- LIT[14]
=> Signal (Unsigned aaw) -- aAddr, ARG[15]
-> Signal a -- aDIn, ARG[16]
-> Signal Bool -- aWrEn, ARG[17]
-> Signal (Unsigned baw) -- bAddr, ARG[18]
-> Signal b -- bDIn, ARG[19]
-> Signal Bool -- bWrEn, ARG[20]
-> Signal (a, b)"
, "templateD" :
"~GENSYM[~COMPNAME_blockram2p][0]: block
signal ~GENSYM[qA][1] : std_logic_vector(~SIZE[~TYP[16]]-1 downto 0);
signal ~GENSYM[qB][2] : std_logic_vector(~SIZE[~TYP[19]]-1 downto 0);
signal ~GENSYM[wren_a][3] : std_logic_vector(0 downto 0);
signal ~GENSYM[wren_b][4] : std_logic_vector(0 downto 0);
begin
~GENSYM[blockram2p_inst][5] : entity blockramwrapper
generic map (
address_reg_b => \"CLOCK0\",
clock_enable_input_a => \"BYPASS\",
clock_enable_input_b => \"BYPASS\",
clock_enable_output_a => \"BYPASS\",
clock_enable_output_b => \"BYPASS\",
indata_reg_b => \"CLOCK0\",
intended_device_family => \"Cyclone IV E\",
lpm_type => \"altsyncram\",
numwords_a => ~LIT[11],
numwords_b => ~LIT[12],
operation_mode => \"BIDIR_DUAL_PORT\",
outdata_aclr_a => \"NONE\",
outdata_aclr_b => \"NONE\",
outdata_reg_a => \"CLOCK0\",
outdata_reg_b => \"CLOCK0\",
power_up_uninitialized => \"FALSE\",
ram_block_type => \"M9K\",
read_during_write_mode_mixed_ports => \"OLD_DATA\",
read_during_write_mode_port_a => \"OLD_DATA\",
read_during_write_mode_port_b => \"OLD_DATA\",
widthad_a => ~LIT[6],
widthad_b => ~LIT[7],
width_a => ~LIT[2],
width_b => ~LIT[3],
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => \"CLOCK0\"
)
port map (
clock0 => ~CLKO,
wren_a => ~SYM[3](0),
address_b => ~TOBV[~ARG[18]][~TYP[18]],
data_b => ~TOBV[~ARG[19]][~TYP[19]],
wren_b => ~SYM[4](0),
address_a => ~TOBV[~ARG[15]][~TYP[15]],
data_a => ~TOBV[~ARG[16]][~TYP[16]],
q_a => ~SYM[1],
q_b => ~SYM[2]
);
~SYM[3] <= ~TOBV[~ARG[17]][~TYP[17]];
~SYM[4] <= ~TOBV[~ARG[20]][~TYP[20]];
~RESULT <= (~FROMBV[~SYM[1]][~TYP[16]]
,~FROMBV[~SYM[2]][~TYP[19]]);
end block;"
}
}
]
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