ecp5-scan.py

#!/usr/bin/env python3
import sys

from migen import *
from migen.build.generic_platform import Pins, IOStandard
from migen.build.lattice import LatticePlatform


class Platform(LatticePlatform):
    default_clk_name = "clk25"
    default_clk_period = 1e9/25e6

    def __init__(self):
        _io_v7_0 = [
            # clock
            ("clk25", 0, Pins("P6"), IOStandard("LVCMOS33")),
        ]
        LatticePlatform.__init__(self, "LFE5U-25F-6BG256C", _io_v7_0, toolchain="trellis")
        self.toolchain.build_template[1] += " --package CABGA256"


def load():
    import os
    f = open("build/openocd.cfg", "w")
    f.write(
"""
interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0x0c08 0x0f1b
reset_config none
adapter_khz 5000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
""")
    f.close()
    os.system("openocd -f build/openocd.cfg -c \"transport select jtag; init; svf build/top.svf; exit\"")
    exit()


class UartSender(Module):
    def __init__(self, pin, bytes, baud_rate=115200):
        bits = 0
        for (i, byte) in enumerate(bytes):
            byte_bits = (1 << 10) | (1 << 9) | (byte << 1)
            bits |= (byte_bits << (11 * i))
        n = 11 * len(bytes)

        divisor = 25_000_000 // baud_rate

        rx_counter = Signal(max=divisor)
        self.rx_strobe = rx_strobe = Signal()
        self.comb += rx_strobe.eq(rx_counter == 0)
        self.sync += \
            If(rx_counter == 0,
               rx_counter.eq(divisor - 1)
               ).Else(
                rx_counter.eq(rx_counter - 1)
            )

        tx_shiftreg = Signal(max=bits)
        tx_counter = Signal(max=n)

        self.submodules.tx_fsm = FSM(reset_state="IDLE")
        self.tx_fsm.act("IDLE",
            pin.eq(1),
            NextValue(tx_shiftreg, bits),
            NextValue(tx_counter, n),
            NextState("SEND")
        )

        self.tx_fsm.act("SEND",
            pin.eq(tx_shiftreg[0]),
            If(tx_counter==0,
                NextState("IDLE")
            ).Elif(self.rx_strobe,
                NextValue(tx_shiftreg, tx_shiftreg >> 1),
                NextValue(tx_counter, tx_counter - 1),
            )
        )


class TopModule(Module):
    def __init__(self, platform, ports):
        ext = []
        for port in ports:
            if "=" in port:
                port = port.split("=")[0]
                ext.append(("sig_" + port, 0, Pins(port), IOStandard("LVCMOS33")))
            else:
                ext.append(("tx_" + port, 0, Pins(port), IOStandard("LVCMOS33")))
        platform.add_extension(ext)

        for port in ports:
            if "=" in port:
                a = port.split("=")
                p = platform.request("sig_" + a[0])
                self.comb += p.eq(int(a[1]))
            else:
                tx = platform.request("tx_" + port)
                self.submodules += UartSender(tx, port.encode("ascii") + b"\r\n")


def main():
    if len(sys.argv) < 2:
        print("Usage: %s <port1> [<port2> ...]", sys.argv[0])
        return
    ports = sys.argv[1:]

    platform = Platform()
    top = TopModule(platform, ports)
    #platform.build(top)
    load()


if __name__ == "__main__":
    main()