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| meatmanek@cm4:~ $ python3 ./sn65dsi83_i2c.py | |
| REG0A : 10000111 | |
| PLL_EN_STAT: 1 PLL enabled | |
| LVDS_CLK_RANGE: 011 87.5 MHz ≤ LVDS_CLK < 112.5 MHz | |
| HS_CLK_SRC: 1 LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock | |
| REG0B : 00010000 | |
| DSI_CLK_DIVIDER: 00010 Divide by 3 | |
| REFCLK_MULTIPLIER: 00 LVDS clock = source clock (default) | |
| REG0D : 00000001 | |
| PLL_EN: 1 PLL enabled | |
| REG10 : 00100110 | |
| CHA_DSI_LANES: 00 Four lanes are enabled | |
| SOT_ERR_TOL_DIS: 0 Single bit errors are tolerated for the start of transaction SoT leader sequence (default) | |
| REG11 : 00000000 | |
| CHA_DSI_DATA_EQ: 00 No equalization (default) | |
| CHA_DSI_CLK_EQ: 00 No equalization (default) | |
| REG12 : 00111100 | |
| CHA_DSI_CLK_RANGE: 00111100 300 MHz <= DSI clock < 305 MHz | |
| REG18 : 00011010 | |
| DE_NEG_POLARITY: 0 DE is positive polarity driven ‘1’ during active pixel transmission on LVDS (default) | |
| HS_NEG_POLARITY: 0 HS is positive polarity driven ‘1’ during corresponding sync conditions | |
| VS_NEG_POLARITY: 0 VS is positive polarity driven ‘1’ during corresponding sync conditions | |
| CHA_24BPP_MODE: 1 Force 24bpp; LVDS channel A lane 4 (B_Y3P/N) is enabled | |
| CHA_24BPP_FORMAT1: 1 LVDS channel B lane A_Y3P/N transmits the 2 least significant bits (LSB) per color; Format 1 | |
| REG19 : 00000101 | |
| CHA_LVDS_VOCM: 0 LVDS Channel A common mode output voltage: 1.2V (default) | |
| CHA_LVDS_VOD_SWING: 01 LVDS differential output voltage: (default) | |
| 100 Ω 200 Ω | |
| min. typ. max. min. typ. max. | |
| data 215 293 392 200 271 365 | |
| clock 168 229 315 156 211 295 | |
| REG1A : 00000011 | |
| CHA_REVERSE_LVDS: 0 Normal LVDS Channel A pin order. | |
| CHA_LVDS_TERM: 1 200Ω differential termination (default) | |
| REG1B : 00000000 | |
| CHA_LVDS_CM_ADJUST: 0 No change to common mode voltage (default) | |
| REG20 : 00000000 | |
| REG21 : 00000100 | |
| CHA_ACTIVE_LINE_LENGTH_LOW: 00000000 | |
| CHA_ACTIVE_LINE_LENGTH_HIGH: 0100 | |
| CHA_ACTIVE_LINE_LENGTH: 010000000000 1024 pixels of the active horizontal line that are received on DSI Channel A and output to LVDS | |
| Channel A | |
| REG24 : 00000000 | |
| REG25 : 00000011 | |
| CHA_VERTICAL_DISPLAY_SIZE_LOW: 00000000 | |
| CHA_VERTICAL_DISPLAY_SIZE_HIGH: 0011 | |
| CHA_VERTICAL_DISPLAY_SIZE: 001100000000 TEST PATTERN GENERATION PURPOSE ONLY. Vertical display size in lines = 768 | |
| REG28 : 00100001 | |
| REG29 : 00000000 | |
| CHA_SYNC_DELAY_LOW: 00100001 | |
| CHA_SYNC_DELAY_HIGH: 0000 | |
| CHA_SYNC_DELAY: 000000100001 33 pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the | |
| LVDS interface. The delay specified by this field is in addition to the pipeline and synchronization | |
| delays in the SN65DSI83-Q1. The additional delay is approximately 10 pixel clocks. The Sync delay must | |
| be programmed to at least 32 pixel clocks to ensure proper operation. | |
| REG2C : 01000000 | |
| REG2D : 00000001 | |
| CHA_HSYNC_PULSE_WIDTH_LOW: 01000000 | |
| CHA_HSYNC_PULSE_WIDTH_HIGH: 01 | |
| CHA_HSYNC_PULSE_WIDTH: 0101000000 HSync Pulse Width = 320 pixel clocks | |
| REG30 : 00001010 | |
| REG31 : 00000000 | |
| CHA_VSYNC_PULSE_WIDTH_LOW: 00001010 | |
| CHA_VSYNC_PULSE_WIDTH_HIGH: 00 | |
| CHA_VSYNC_PULSE_WIDTH: 0000001010 VSync Pulse Width = 10 lines | |
| REG34 : 11100000 | |
| CHA_HORIZONTAL_BACK_PORCH: 11100000 224 pixel clocks between the end of the HSync Pulse and the start of the active video data (LVDS) | |
| REG36 : 00000110 | |
| CHA_VERTICAL_BACK_PORCH: 00000110 TEST PATTERN GENERATION PURPOSE ONLY. 6 lines between the end of the VSync Pulse and the start of the | |
| active video data | |
| REG38 : 00000100 | |
| CHA_HORIZONTAL_FRONT_PORCH: 00000100 TEST PATTERN GENERATION PURPOSE ONLY. 4 pixel clocks between the end of the active video data and the | |
| start of the HSync Pulse | |
| REG3A : 00010000 | |
| CHA_VERTICAL_FRONT_PORCH: 00010000 TEST PATTERN GENERATION PURPOSE ONLY. 16 lines between the end of the active video data and the start | |
| of the VSync Pulse | |
| REG3C : 00000000 | |
| CHA_TEST_PATTERN: 0 Disable Channel A test pattern | |
| REGE0 : 00000000 | |
| IRQ_EN: 0 IRQ output is high-impedance (default) | |
| REGE1 : 00000000 | |
| CHA_SYNCH_ERR_EN: 0 CHA_SYNCH_ERR is masked | |
| CHA_CRC_ERR_EN: 0 CHA_CRC_ERR is masked | |
| CHA_UNC_ECC_ERR_EN: 0 CHA_UNC_ECC_ERR is masked | |
| CHA_COR_ECC_ERR_EN: 0 CHA_COR_ECC_ERR is masked | |
| CHA_LLP_ERR_EN: 0 CHA_LLP_ERR is masked | |
| CHA_SOT_BIT_ERR_EN: 0 CHA_SOT_BIT_ERR is masked | |
| PLL_UNLOCK_EN: 0 PLL_UNLOCK is masked | |
| REGE5 : 00000000 | |
| CHA_SYNCH_ERR: 0 | |
| CHA_CRC_ERR: 0 | |
| CHA_UNC_ECC_ERR: 0 | |
| CHA_COR_ECC_ERR: 0 | |
| CHA_LLP_ERR: 0 | |
| CHA_SOT_BIT_ERR: 0 | |
| PLL_UNLOCK: 0 |
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