Altera FPGA: Output of command in this comment: https://github.com/ikwzm/FPGA-SoC-Linux/issues/2#issuecomment-281081132

altera-hps2fpga.dts

/dts-v1/;
/ {
	fpga-bridge@0 {
		target-path = "/soc";
		__overlay__ {
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			hps_fpgabridge0: fpgabridge@0 {
				compatible = "altr,socfpga-hps2fpga-bridge";
				label = "hps2fpga";
				resets = <33 96>;
				reset-names = "hps2fpga";
				clocks = <3>;
			};
		};
	};
	fpga-bridge@1 {
		target-path = "/soc";
		__overlay__ {
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			hps_fpgabridge1: fpgabridge@1 {
				compatible = "altr,socfpga-lwhps2fpga-bridge";
				label = "lwhps2fpga";
				resets = <33 97>;
				reset-names = "lwhps2fpga";
				clocks = <3>;
			};
		};
	};
	fpga-bridge@2 {
		target-path = "/soc";
		__overlay__ {
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			hps_fpgabridge2: fpgabridge@2 {
				compatible = "altr,socfpga-fpga2hps-bridge";
				label = "fpga2hps";
				resets = <33 98>;
				reset-names = "fpga2hps";
				clocks = <3>;
			};
		};
        };
	fpga-bridge@3 {
		target-path = "/soc";
		__overlay__ {
			#address-cells = <0x1>;
			#size-cells = <0x1>;
                        l3regs@0xff800000 {
                                compatible = "altr,l3regs", "syscon";
                                reg = <0xff800000 0x1000>;
        		};
                };
	};
};