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@Fxlr8

Fxlr8/jspininfo.c Secret

Created Jul 4, 2018
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#include "jspininfo.h"
const JshPinInfo pinInfo[JSH_PIN_COUNT] = {
/* PA0 */ { JSH_PORTA, JSH_PIN0+0, JSH_ANALOG12|JSH_ANALOG_CH0, { 0, 0, 0 } },
/* PA1 */ { JSH_PORTA, JSH_PIN0+1, JSH_ANALOG12|JSH_ANALOG_CH1, { JSH_AF0|JSH_TIMER2|JSH_TIMER_CH2/* 2 Uses */, 0, 0 } },
/* PA2 */ { JSH_PORTA, JSH_PIN0+2, JSH_ANALOG12|JSH_ANALOG_CH2, { JSH_AF0|JSH_USART2|JSH_USART_TX/* 1 Uses */, JSH_AF0|JSH_TIMER2|JSH_TIMER_CH3/* 2 Uses */, 0 } },
/* PA3 */ { JSH_PORTA, JSH_PIN0+3, JSH_ANALOG12|JSH_ANALOG_CH3, { JSH_AF0|JSH_USART2|JSH_USART_RX/* 1 Uses */, JSH_AF0|JSH_TIMER2|JSH_TIMER_CH4/* 2 Uses */, 0 } },
/* PA4 */ { JSH_PORTA, JSH_PIN0+4, JSH_ANALOG12|JSH_ANALOG_CH4, { JSH_AF0|JSH_USART2|JSH_USART_CK/* 1 Uses */, 0, 0 } },
/* PA5 */ { JSH_PORTA, JSH_PIN0+5, JSH_ANALOG12|JSH_ANALOG_CH5, { JSH_AF0|JSH_SPI1|JSH_SPI_SCK/* 2 Uses */, 0, 0 } },
/* PA6 */ { JSH_PORTA, JSH_PIN0+6, JSH_ANALOG12|JSH_ANALOG_CH6, { JSH_AF0|JSH_TIMER3|JSH_TIMER_CH1/* 2 Uses */, JSH_AF0|JSH_SPI1|JSH_SPI_MISO/* 2 Uses */, 0 } },
/* PA7 */ { JSH_PORTA, JSH_PIN0+7, JSH_ANALOG12|JSH_ANALOG_CH7, { JSH_AF0|JSH_SPI1|JSH_SPI_MOSI/* 2 Uses */, JSH_AF0|JSH_TIMER3|JSH_TIMER_CH2/* 2 Uses */, JSH_AF1|JSH_TIMER1|JSH_TIMER_CH1|JSH_TIMER_NEGATED/* 3 Uses */ } },
/* PA8 */ { JSH_PORTA, JSH_PIN0+8, JSH_ANALOG_NONE, { JSH_AF0|JSH_USART1|JSH_USART_CK/* 1 Uses */, JSH_AF0|JSH_TIMER1|JSH_TIMER_CH1/* 3 Uses */, 0 } },
/* PA9 */ { JSH_PORTA, JSH_PIN0+9, JSH_ANALOG_NONE, { JSH_AF0|JSH_USART1|JSH_USART_TX/* 2 Uses */, JSH_AF0|JSH_TIMER1|JSH_TIMER_CH2/* 3 Uses */, 0 } },
/* PA10 */ { JSH_PORTA, JSH_PIN0+10, JSH_ANALOG_NONE, { JSH_AF0|JSH_USART1|JSH_USART_RX/* 2 Uses */, JSH_AF0|JSH_TIMER1|JSH_TIMER_CH3/* 3 Uses */, 0 } },
/* PA11 */ { JSH_PORTA, JSH_PIN0+11, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER1|JSH_TIMER_CH4/* 1 Uses */, 0, 0 } },
/* PA12 */ { JSH_PORTA, JSH_PIN0+12, JSH_ANALOG_NONE, { 0, 0, 0 } },
/* PA13 */ { JSH_PORTA, JSH_PIN0+13, JSH_ANALOG_NONE, { 0, 0, 0 } },
/* PA14 */ { JSH_PORTA, JSH_PIN0+14, JSH_ANALOG_NONE, { 0, 0, 0 } },
/* PA15 */ { JSH_PORTA, JSH_PIN0+15, JSH_ANALOG_NONE, { 0, 0, 0 } },
/* PB0 */ { JSH_PORTB, JSH_PIN0+0, JSH_ANALOG12|JSH_ANALOG_CH8, { JSH_AF0|JSH_TIMER3|JSH_TIMER_CH3/* 1 Uses */, JSH_AF1|JSH_TIMER1|JSH_TIMER_CH2|JSH_TIMER_NEGATED/* 3 Uses */, 0 } },
/* PB1 */ { JSH_PORTB, JSH_PIN0+1, JSH_ANALOG12|JSH_ANALOG_CH9, { JSH_AF0|JSH_TIMER3|JSH_TIMER_CH4/* 1 Uses */, JSH_AF1|JSH_TIMER1|JSH_TIMER_CH3|JSH_TIMER_NEGATED/* 3 Uses */, 0 } },
/* PB2 */ { JSH_PORTB, JSH_PIN0+2, JSH_ANALOG_NONE, { 0, 0, 0 } },
/* PB3 */ { JSH_PORTB, JSH_PIN0+3, JSH_ANALOG_NONE, { JSH_AF1|JSH_TIMER2|JSH_TIMER_CH2/* 2 Uses */, JSH_AF1|JSH_SPI1|JSH_SPI_SCK/* 2 Uses */, 0 } },
/* PB4 */ { JSH_PORTB, JSH_PIN0+4, JSH_ANALOG_NONE, { JSH_AF1|JSH_TIMER3|JSH_TIMER_CH1/* 2 Uses */, JSH_AF1|JSH_SPI1|JSH_SPI_MISO/* 2 Uses */, 0 } },
/* PB5 */ { JSH_PORTB, JSH_PIN0+5, JSH_ANALOG_NONE, { JSH_AF1|JSH_TIMER3|JSH_TIMER_CH2/* 2 Uses */, JSH_AF1|JSH_SPI1|JSH_SPI_MOSI/* 2 Uses */, 0 } },
/* PB6 */ { JSH_PORTB, JSH_PIN0+6, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER4|JSH_TIMER_CH1/* 1 Uses */, JSH_AF0|JSH_I2C1|JSH_I2C_SCL/* 2 Uses */, JSH_AF1|JSH_USART1|JSH_USART_TX/* 2 Uses */ } },
/* PB7 */ { JSH_PORTB, JSH_PIN0+7, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER4|JSH_TIMER_CH2/* 1 Uses */, JSH_AF0|JSH_I2C1|JSH_I2C_SDA/* 2 Uses */, JSH_AF1|JSH_USART1|JSH_USART_RX/* 2 Uses */ } },
/* PB8 */ { JSH_PORTB, JSH_PIN0+8, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER4|JSH_TIMER_CH3/* 1 Uses */, JSH_AF1|JSH_I2C1|JSH_I2C_SCL/* 2 Uses */, 0 } },
/* PB9 */ { JSH_PORTB, JSH_PIN0+9, JSH_ANALOG_NONE, { JSH_AF0|JSH_TIMER4|JSH_TIMER_CH4/* 1 Uses */, JSH_AF1|JSH_I2C1|JSH_I2C_SDA/* 2 Uses */, 0 } },
/* PB10 */ { JSH_PORTB, JSH_PIN0+10, JSH_ANALOG_NONE, { JSH_AF0|JSH_USART3|JSH_USART_TX/* 1 Uses */, JSH_AF0|JSH_I2C2|JSH_I2C_SCL/* 1 Uses */, JSH_AF1|JSH_TIMER2|JSH_TIMER_CH3/* 2 Uses */ } },
/* PB11 */ { JSH_PORTB, JSH_PIN0+11, JSH_ANALOG_NONE, { JSH_AF0|JSH_USART3|JSH_USART_RX/* 1 Uses */, JSH_AF0|JSH_I2C2|JSH_I2C_SDA/* 1 Uses */, JSH_AF1|JSH_TIMER2|JSH_TIMER_CH4/* 2 Uses */ } },
/* PB12 */ { JSH_PORTB, JSH_PIN0+12, JSH_ANALOG_NONE, { JSH_AF0|JSH_USART3|JSH_USART_CK/* 1 Uses */, 0, 0 } },
/* PB13 */ { JSH_PORTB, JSH_PIN0+13, JSH_ANALOG_NONE, { JSH_AF0|JSH_SPI2|JSH_SPI_SCK/* 1 Uses */, JSH_AF0|JSH_TIMER1|JSH_TIMER_CH1|JSH_TIMER_NEGATED/* 3 Uses */, 0 } },
/* PB14 */ { JSH_PORTB, JSH_PIN0+14, JSH_ANALOG_NONE, { JSH_AF0|JSH_SPI2|JSH_SPI_MISO/* 1 Uses */, JSH_AF0|JSH_TIMER1|JSH_TIMER_CH2|JSH_TIMER_NEGATED/* 3 Uses */, 0 } },
/* PB15 */ { JSH_PORTB, JSH_PIN0+15, JSH_ANALOG_NONE, { JSH_AF0|JSH_SPI2|JSH_SPI_MOSI/* 1 Uses */, JSH_AF0|JSH_TIMER1|JSH_TIMER_CH3|JSH_TIMER_NEGATED/* 3 Uses */, 0 } },
/* PC13 */ { JSH_PORTC, JSH_PIN0+13, JSH_ANALOG_NONE, { 0, 0, 0 } },
/* PC14 */ { JSH_PORTC, JSH_PIN0+14, JSH_ANALOG_NONE, { 0, 0, 0 } },
/* PC15 */ { JSH_PORTC, JSH_PIN0+15, JSH_ANALOG_NONE, { 0, 0, 0 } },
/* PD0 */ { JSH_PORTD, JSH_PIN0+0, JSH_ANALOG_NONE, { 0, 0, 0 } },
/* PD1 */ { JSH_PORTD, JSH_PIN0+1, JSH_ANALOG_NONE, { 0, 0, 0 } },
};
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