Log info from SDK 2017.4 and SDK 2016.3

zynq10.txt

# Execution of FSBL in during programming flash (SDK 2017.4)
Xilinx First Stage Boot Loader 
Release 2017.4  Feb 22 2018-18:30:28
Devcfg driver initialized 
Silicon Version 3.1
Boot mode is QSPI
Single Flash Information
FlashID=0x20 0xBA 0x19
MICRON 256M Bits
QSPI is in single flash connection
QSPI is in 4-bit mode
QSPI Init Done 
Flash Base Address: 0xFC000000
Reboot status register: 0x60500000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 3
Partition Number: 1
Header Dump
Image Word Len: 0x0007F2E8
Data Word Len: 0x0007F2E8
Partition Word Len:0x0007F2E8
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000065D0
Partition Attr: 0x00000020
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFE7BF06
Bitstream
In FsblHookBeforeBitstreamDload function 
PCAP:StatusReg = 0x40000A30
PCAP:device ready
PCAP:Clear done
Level Shifter Value = 0xA 
Devcfg Status register = 0x40000A30 
PCAP:Fabric is Initialized done
PCAP register dump:
PCAP CTRL 0xF8007000: 0x4C00E07F
PCAP LOCK 0xF8007004: 0x0000001A
PCAP CONFIG 0xF8007008: 0x00000508
PCAP ISR 0xF800700C: 0x0802000B
PCAP IMR 0xF8007010: 0xFFFFFFFF
PCAP STATUS 0xF8007014: 0x50000F30
PCAP DMA SRC ADDR 0xF8007018: 0x00100001
PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF
PCAP DMA SRC LEN 0xF8007020: 0x0007F2E8
PCAP DMA DEST LEN 0xF8007024: 0x0007F2E8
PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF
PCAP MBOOT 0xF800702C: 0x0000C000
PCAP SW ID 0xF8007030: 0x00000000
PCAP UNLOCK 0xF8007034: 0x757BDF0D
PCAP MCTRL 0xF8007080: 0x30800100

DMA Done ! 

FPGA Done ! 
In FsblHookAfterBitstreamDload function 
Partition Number: 2
Header Dump
Image Word Len: 0x000176F2
Data Word Len: 0x000176F2
Partition Word Len:0x000176F2
Load Addr: 0x04000000
Exec Addr: 0x04000000
Partition Start: 0x000858C0
Partition Attr: 0x00000010
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xF7F33FF8
Application
Handoff Address: 0x04000000
In FsblHookBeforeHandoff function 
SUCCESSFUL_HANDOFF

# Command of flashing (SDK 2017.4) with Verify check
cmd /C program_flash -f C:\Users\vldmr\Desktop\firmware\boot.bin -offset 0 -flash_type \
qspi_single -fsbl \
C:\Projects\zynq_eth_arm_2017_05_05_1_N\zynq_eth_arm_2017_05_05_1_N\zynq_eth_arm_2017_05_05_1_N.sdk\fsbl2\Debug\fsbl2.elf \
-verify -cable type xilinx_tcf url TCP:127.0.0.1:3121 
WARNING: %XILINX% contains multiple entries. Setting
         %XIL_PA_NO_XILINX_OVERRIDE% to 1.
 
WARNING: %XIL_PA_NO_XILINX_OVERRIDE% is set to 1.
         When %XIL_PA_NO_XILINX_OVERRIDE% is enabled
         %XILINX%, %MYXILINX%, and %PATH% must be manually set.

****** Xilinx Program Flash
****** Program Flash v2017.4.1 (64-bit)
  **** SW Build 2117270 on Tue Jan 30 15:32:00 MST 2018
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Connecting to hw_server @ TCP:127.0.0.1:3121

WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-DLC9LP-00000000000000
	Device 0: jsn-DLC9LP-00000000000000-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.
f probe 0 0 0


Performing Erase Operation...
Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 1 sec.
Performing Program Operation...
0%...10%...100%
Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 83 sec.
Performing Verify Operation...
0%...INFO: [Xicom 50-44] Elapsed time = 3 sec.
Verify Operation unsuccessful.

ERROR: Flash Operation Failed

# Try flash in SDK 2016.3 with Verify check
cmd /C program_flash -f C:\Users\vldmr\Desktop\firmware\boot.bin -offset 0 -flash_type \
qspi_single -verify -cable type xilinx_tcf url TCP:127.0.0.1:3121 
WARNING: %XILINX% contains multiple entries. Setting
         %XIL_PA_NO_XILINX_OVERRIDE% to 1.
 
WARNING: %XIL_PA_NO_XILINX_OVERRIDE% is set to 1.
         When %XIL_PA_NO_XILINX_OVERRIDE% is enabled
         %XILINX%, %MYXILINX%, and %PATH% must be manually set.

****** Xilinx Program Flash
****** Program Flash v2016.3 (64-bit)
  **** SW Build 1682563 on Mon Oct 10 19:07:27 MDT 2016
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

Connecting to hw_server @ TCP:127.0.0.1:3121

WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-DLC9LP-00000000000000
	Device 0: jsn-DLC9LP-00000000000000-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.
f probe 0 0 0
Performing Erase Operation...
Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 141 sec.
Performing Program Operation...
0%...10%...100%
Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 87 sec.
Performing Verify Operation...
0%...10%...20%...30%...100%
INFO: [Xicom 50-44] Elapsed time = 108 sec.
Verify Operation successful.

Flash Operation Successful