Created
March 1, 2021 05:00
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| /dts-v1/; | |
| / { | |
| #address-cells = <0x02>; | |
| model = "cavium,rhino_itus7x"; | |
| #size-cells = <0x02>; | |
| interrupt-parent = <0x01>; | |
| compatible = "cavium,rhino_itus7x"; | |
| soc@0 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| compatible = "simple-bus"; | |
| ranges; | |
| dma-engine@1180000000108 { | |
| interrupts = <0x00 0x3f>; | |
| compatible = "cavium,octeon-5750-bootbus-dma"; | |
| reg = <0x11800 0x108 0x00 0x08>; | |
| }; | |
| mdio@1180000001800 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "cavium,octeon-3860-mdio"; | |
| reg = <0x11800 0x1800 0x00 0x40>; | |
| ethernet-phy@3 { | |
| marvell,reg-init = <0x00 0x10 0xff9f 0x60 0x02 0x15 0xffcf 0x00 0x00 0x00 0x7fff 0x8000>; | |
| interrupts = <0x07 0x08>; | |
| interrupt-parent = <0x02>; | |
| compatible = "marvell,88e1118"; | |
| reg = <0x03>; | |
| phandle = <0x06>; | |
| linux,phandle = <0x06>; | |
| cavium,qlm-trim = "0,qsgmii"; | |
| }; | |
| ethernet-phy@1 { | |
| marvell,reg-init = <0x00 0x10 0xff9f 0x60 0x02 0x15 0xffcf 0x00 0x00 0x00 0x7fff 0x8000>; | |
| interrupts = <0x07 0x08>; | |
| interrupt-parent = <0x02>; | |
| compatible = "marvell,88e1118"; | |
| reg = <0x01>; | |
| phandle = <0x04>; | |
| linux,phandle = <0x04>; | |
| cavium,qlm-trim = "0,qsgmii"; | |
| }; | |
| ethernet-phy@2 { | |
| marvell,reg-init = <0x00 0x10 0xff9f 0x60 0x02 0x15 0xffcf 0x00 0x00 0x00 0x7fff 0x8000>; | |
| interrupts = <0x07 0x08>; | |
| interrupt-parent = <0x02>; | |
| compatible = "marvell,88e1118"; | |
| reg = <0x02>; | |
| phandle = <0x05>; | |
| linux,phandle = <0x05>; | |
| cavium,qlm-trim = "0,qsgmii"; | |
| }; | |
| ethernet-phy@0 { | |
| marvell,reg-init = <0x00 0x10 0xff9f 0x60 0x02 0x15 0xffcf 0x00 0x00 0x00 0x7fff 0x8000>; | |
| interrupts = <0x07 0x08>; | |
| interrupt-parent = <0x02>; | |
| compatible = "marvell,88e1118"; | |
| reg = <0x00>; | |
| phandle = <0x03>; | |
| linux,phandle = <0x03>; | |
| cavium,qlm-trim = "0,qsgmii"; | |
| }; | |
| }; | |
| serial@1180000000c00 { | |
| interrupts = <0x00 0x23>; | |
| clock-frequency = <0x23c34600>; | |
| current-speed = <0x1c200>; | |
| compatible = "cavium,octeon-3860-uart\0ns16550"; | |
| reg = <0x11800 0xc00 0x00 0x400>; | |
| reg-shift = <0x03>; | |
| }; | |
| mmc@1180000002000 { | |
| #address-cells = <0x01>; | |
| interrupts = <0x01 0x13 0x00 0x3f>; | |
| #size-cells = <0x00>; | |
| compatible = "cavium,octeon-6130-mmc"; | |
| reg = <0x11800 0x2000 0x00 0x100 0x11800 0x168 0x00 0x20>; | |
| mmc-slot@2 { | |
| spi-max-frequency = <0x18cba80>; | |
| voltage-ranges = <0xce4 0xce4>; | |
| compatible = "cavium,octeon-6130-mmc-slot"; | |
| cavium,bus-max-width = <0x08>; | |
| power-gpios = <0x02 0x08 0x00>; | |
| reg = <0x02>; | |
| }; | |
| mmc-slot@0 { | |
| bus-width = <0x08>; | |
| spi-max-frequency = <0x18cba80>; | |
| voltage-ranges = <0xce4 0xce4>; | |
| compatible = "cavium,octeon-6130-mmc-slot"; | |
| cavium,bus-max-width = <0x08>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| interrupt-controller@107000000e600 { | |
| cavium,max-bits = <0x04>; | |
| interrupts = <0x02 0x10>; | |
| interrupt-parent = <0x01>; | |
| compatible = "cavium,octeon-7130-cib"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x10700 0xe600 0x00 0x08 0x10700 0xe700 0x00 0x08>; | |
| interrupt-controller; | |
| }; | |
| i2c@1180000001000 { | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x2d>; | |
| #size-cells = <0x00>; | |
| clock-frequency = <0x186a0>; | |
| compatible = "cavium,octeon-3860-twsi"; | |
| reg = <0x11800 0x1000 0x00 0x200>; | |
| avr@68 { | |
| interrupts = <0x11 0x08>; | |
| interrupt-parent = <0x02>; | |
| compatible = "atmel,24c256"; | |
| reg = <0x68>; | |
| }; | |
| tlv-eeprom@56 { | |
| compatible = "microchip,24c256"; | |
| pagesize = <0x40>; | |
| reg = <0x56>; | |
| }; | |
| }; | |
| interrupt-controller@107000000e900 { | |
| cavium,max-bits = <0x0b>; | |
| interrupts = <0x01 0x11>; | |
| interrupt-parent = <0x01>; | |
| compatible = "cavium,octeon-7130-cib"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x10700 0xe900 0x00 0x08 0x10700 0xeb00 0x00 0x08>; | |
| interrupt-controller; | |
| }; | |
| ocla0@11800A8000000 { | |
| interrupts = <0x08 0x01 0x09 0x01>; | |
| interrupt-parent = <0x07>; | |
| compatible = "cavium,octeon-7130-ocla"; | |
| reg = <0x11800 0xa8000000 0x00 0x500000>; | |
| }; | |
| interrupt-controller@107000000e200 { | |
| cavium,max-bits = <0x0c>; | |
| interrupts = <0x01 0x34>; | |
| interrupt-parent = <0x01>; | |
| compatible = "cavium,octeon-7130-cib"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x10700 0xe200 0x00 0x08 0x10700 0xe300 0x00 0x08>; | |
| interrupt-controller; | |
| }; | |
| bootbus@1180000000000 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x01>; | |
| compatible = "cavium,octeon-3860-bootbus"; | |
| ranges = <0x00 0x00 0x10000 0x10000000 0x00 0x01 0x00 0x10000 0x20000000 0x00 0x02 0x00 0x10000 0x30000000 0x00 0x03 0x00 0x10000 0x40000000 0x00 0x04 0x00 0x10000 0x50000000 0x00 0x05 0x00 0x10000 0x60000000 0x00 0x06 0x00 0x10000 0x70000000 0x00 0x07 0x00 0x10000 0x80000000 0x00>; | |
| reg = <0x11800 0x00 0x00 0x200>; | |
| cavium,cs-config@0 { | |
| cavium,t-rd-hld = <0x23>; | |
| cavium,ale-mode = <0x01>; | |
| cavium,t-rd-dly = <0x00>; | |
| cavium,t-adr = <0x14>; | |
| cavium,t-wait = <0x12c>; | |
| cavium,t-oe = <0x3c>; | |
| compatible = "cavium,octeon-3860-bootbus-config"; | |
| cavium,t-we = <0x2d>; | |
| cavium,t-page = <0x23>; | |
| cavium,cs-index = <0x00>; | |
| cavium,bus-width = <0x08>; | |
| cavium,t-ce = <0x3c>; | |
| cavium,t-ale = <0x22>; | |
| cavium,t-wr-hld = <0x2d>; | |
| cavium,t-pause = <0x00>; | |
| }; | |
| }; | |
| dma-engine@1180000000100 { | |
| interrupts = <0x00 0x3f>; | |
| compatible = "cavium,octeon-5750-bootbus-dma"; | |
| reg = <0x11800 0x100 0x00 0x08>; | |
| }; | |
| interrupt-controller@107000000e800 { | |
| cavium,max-bits = <0x0b>; | |
| interrupts = <0x01 0x21>; | |
| interrupt-parent = <0x01>; | |
| compatible = "cavium,octeon-7130-cib"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x10700 0xe800 0x00 0x08 0x10700 0xea00 0x00 0x08>; | |
| interrupt-controller; | |
| }; | |
| uctl@118006c000000 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| compatible = "cavium,octeon-7130-sata-uctl"; | |
| ranges; | |
| reg = <0x11800 0x6c000000 0x00 0x100>; | |
| }; | |
| interrupt-controller@107000000e400 { | |
| cavium,max-bits = <0x06>; | |
| interrupts = <0x01 0x3f>; | |
| interrupt-parent = <0x01>; | |
| compatible = "cavium,octeon-7130-cib"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x10700 0xe400 0x00 0x08 0x10700 0xe500 0x00 0x08>; | |
| interrupt-controller; | |
| }; | |
| serial@1180000000800 { | |
| interrupts = <0x00 0x22>; | |
| clock-frequency = <0x23c34600>; | |
| current-speed = <0x1c200>; | |
| compatible = "cavium,octeon-3860-uart\0ns16550"; | |
| reg = <0x11800 0x800 0x00 0x400>; | |
| reg-shift = <0x03>; | |
| }; | |
| interrupt-controller@1070000000000 { | |
| compatible = "cavium,octeon-3860-ciu"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x10700 0x00 0x00 0x7000>; | |
| phandle = <0x01>; | |
| linux,phandle = <0x01>; | |
| interrupt-controller; | |
| }; | |
| interrupt-controller@107000000ec00 { | |
| cavium,max-bits = <0x0f>; | |
| interrupts = <0x02 0x11>; | |
| interrupt-parent = <0x01>; | |
| compatible = "cavium,octeon-7130-cib"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x10700 0xec00 0x00 0x08 0x10700 0xee00 0x00 0x08>; | |
| phandle = <0x07>; | |
| linux,phandle = <0x07>; | |
| interrupt-controller; | |
| }; | |
| pip@11800a0000000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "cavium,octeon-3860-pip"; | |
| reg = <0x11800 0xa0000000 0x00 0x2000>; | |
| interface@0 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "cavium,octeon-3860-pip-interface"; | |
| reg = <0x00>; | |
| cavium,qlm-trim = "0,qsgmii"; | |
| ethernet@3 { | |
| local-mac-address = [2c 26 5f 80 14 3f]; | |
| compatible = "cavium,octeon-3860-pip-port"; | |
| reg = <0x03>; | |
| phy-handle = <0x06>; | |
| }; | |
| ethernet@1 { | |
| local-mac-address = [2c 26 5f 80 14 3d]; | |
| compatible = "cavium,octeon-3860-pip-port"; | |
| reg = <0x01>; | |
| phy-handle = <0x04>; | |
| }; | |
| ethernet@2 { | |
| local-mac-address = [2c 26 5f 80 14 3e]; | |
| compatible = "cavium,octeon-3860-pip-port"; | |
| reg = <0x02>; | |
| phy-handle = <0x05>; | |
| }; | |
| ethernet@0 { | |
| local-mac-address = [2c 26 5f 80 14 3c]; | |
| compatible = "cavium,octeon-3860-pip-port"; | |
| reg = <0x00>; | |
| phy-handle = <0x03>; | |
| }; | |
| }; | |
| }; | |
| gpio-controller@1070000000800 { | |
| gpio-controller; | |
| interrupts = <0x00 0x10 0x00 0x11 0x00 0x12 0x00 0x13 0x00 0x14 0x00 0x15 0x00 0x16 0x00 0x17 0x00 0x18 0x00 0x19 0x00 0x1a 0x00 0x1b 0x00 0x1c 0x00 0x1d 0x00 0x1e 0x00 0x1f>; | |
| compatible = "cavium,octeon-3860-gpio"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x10700 0x800 0x00 0x100>; | |
| phandle = <0x02>; | |
| #gpio-cells = <0x02>; | |
| linux,phandle = <0x02>; | |
| interrupt-controller; | |
| }; | |
| interrupt-controller@107000000e000 { | |
| cavium,max-bits = <0x17>; | |
| interrupts = <0x01 0x18>; | |
| interrupt-parent = <0x01>; | |
| compatible = "cavium,octeon-7130-cib"; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x10700 0xe000 0x00 0x08 0x10700 0xe100 0x00 0x08>; | |
| interrupt-controller; | |
| }; | |
| }; | |
| gpio-leds { | |
| compatible = "gpio-leds"; | |
| d1 { | |
| label = "Yellow"; | |
| default-state = "keep"; | |
| gpios = <0x02 0x0b 0x00>; | |
| }; | |
| }; | |
| aliases { | |
| smi0 = "/soc@0/mdio@1180000001800"; | |
| uart0 = "/soc@0/serial@1180000000800"; | |
| emmc = "/soc@0/mmc@1180000002000"; | |
| pip = "/soc@0/pip@11800a0000000"; | |
| uart1 = "/soc@0/serial@1180000000c00"; | |
| twsi0 = "/soc@0/i2c@1180000001000"; | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x00 0x00 0x00 0x10000000 0x00 0x20000000 0x00 0x30000000>; | |
| }; | |
| }; |
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