RAM32X1D_vivado_1slice.v

/*
CLBLM_R_X3Y39.SLICEL_X1.PRECYINIT.C0
CLBLM_R_X3Y39.SLICEM_X0.CLUT.RAM
CLBLM_R_X3Y39.SLICEM_X0.CLUT.SMALL
CLBLM_R_X3Y39.SLICEM_X0.COUTMUX.O5
CLBLM_R_X3Y39.SLICEM_X0.DLUT.RAM
CLBLM_R_X3Y39.SLICEM_X0.DLUT.SMALL
CLBLM_R_X3Y39.SLICEM_X0.DOUTMUX.O5
CLBLM_R_X3Y39.SLICEM_X0.PRECYINIT.C0
CLBLM_R_X3Y39.SLICEM_X0.WEMUX.CE
*/

module top(
    input [4:0] wraddr,
    input [4:0] rdaddr,
    input we,
    input clk,
    input di,
    input di2,
    output [1:0] spo,
    output [1:0] dpo);
    RAM32X1D dram1 (
        .D(di),
        .DPRA0(rdaddr[0]),
        .DPRA1(rdaddr[1]),
        .DPRA2(rdaddr[2]),
        .DPRA3(rdaddr[3]),
        .DPRA4(rdaddr[4]),
        // .DPRA5(rdaddr[5]),
        .A0(wraddr[0]),
        .A1(wraddr[1]),
        .A2(wraddr[2]),
        .A3(wraddr[3]),
        .A4(wraddr[4]),
        //.A5(wraddr[5]),
        .WCLK(clk),
        .WE(we),
        .SPO(spo[0]),
        .DPO(dpo[0])
    );
    RAM32X1D dram2 (
        .D(di2),
        .DPRA0(rdaddr[0]),
        .DPRA1(rdaddr[1]),
        .DPRA2(rdaddr[2]),
        .DPRA3(rdaddr[3]),
        .DPRA4(rdaddr[4]),
        // .DPRA5(rdaddr[5]),
        .A0(wraddr[0]),
        .A1(wraddr[1]),
        .A2(wraddr[2]),
        .A3(wraddr[3]),
        .A4(wraddr[4]),
        // .A5(wraddr[5]),
        .WCLK(clk),
        .WE(we),
        .SPO(spo[1]),
        .DPO(dpo[1])
    );
endmodule