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KennethWilke / Makefile
Created October 19, 2017 18:09
Vivado SystemVerilog Makefile
XVLOG_FILES=xvlog.log xvlog.pb xsim.dir/
XELAB_FILES=webtalk*.log webtalk*.jou xelab.log xelab.pb .Xil/
XSIM_FILES=xsim*.log xsim*.jou work.top.wdb
all: xsim.dir/
xsim.dir/: *.sv
@echo "Parsing HDL"
@xvlog --sv *.sv
@echo "Elaborating design"
#!/usr/bin/env python
import paramiko
import sys
# LSHW parsing
def ls_parse_branch(lines, depth=1):
data = {}
while len(lines):
line = lines.pop(0)
if line[depth:].startswith(' ') and ':' in line:
kwilke@kbawx:/tmp$ python test.py http://suchprogramming.com
ERROR: http://suchprogramming.com has content type "text/html; charset=UTF-8"
kwilke@kbawx:/tmp$ python test.py http://suchprogramming.com/wp-content/uploads/2016/03/parity.png
OK!
ages = {'John': 23,
'Bailey': 36,
'George': 12}
for name, age in ages.iteritems():
print "{0} is {1} years old".format(name, age)
import sys
times_to_run = int(sys.argv[1])
times_ran = 0
for i in range(0, times_to_run):
times_ran += 1
print "Did it {0} times!".format(times_ran)