nix log /nix/store/vml5wihyx788b3k8n55n7m7ay5kgs5r0-libresoc-versa-ecp5-20210924.drv

gistfile1.txt

unpacking sources
unpacking source archive /nix/store/6yd499dr51339dcx4yqa8kr397irx217-florent
source root is florent
patching sources
patching script interpreter paths in .
./versa_ecp5.py: interpreter directive changed from "#!/usr/bin/env python3" to "/nix/store/1g54cwl6m78rgrqsnn1pp29dbvldpvsd-python3-3.9.6/bin/python3"
./sim.py: interpreter directive changed from "#!/usr/bin/env python3" to "/nix/store/1g54cwl6m78rgrqsnn1pp29dbvldpvsd-python3-3.9.6/bin/python3"
./ls180soc.py: interpreter directive changed from "#!/usr/bin/env python3" to "/nix/store/1g54cwl6m78rgrqsnn1pp29dbvldpvsd-python3-3.9.6/bin/python3"
configuring
building
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2021-09-24 20:57:28)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : LFE5UM-45F-8BG381C.
INFO:SoC:System clock: 55.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 4.0KiB Address Space, 2048B Paging, big Ordering (Up to 8 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 4.0KiB Address Space, 2048B Paging, big Ordering (Up to 8 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0xc0000000, Size: 0x10000000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:cpu_bus0 Bus converted from Wishbone 64-bit to Wishbone 32-bit.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 Bus converted from Wishbone 64-bit to Wishbone 32-bit.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCBusHandler:cpu_bus2 added as Bus Master.
INFO:SoCCSRHandler:cpu CSR allocated at Location 1.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00010000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00010000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 2.
INFO:SoCCSRHandler:uart_phy CSR allocated at Location 3.
INFO:SoCCSRHandler:uart CSR allocated at Location 4.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 5.
INFO:ECP5PLL:Creating ECP5PLL.
INFO:ECP5PLL:Registering Single Ended ClkIn of 100.00MHz.
INFO:ECP5PLL:Creating ClkOut0 sys2x_i of 110.00MHz (+-10000.00ppm).
INFO:ECP5PLL:Creating ClkOut1 init of 25.00MHz (+-10000.00ppm).
INFO:SoCCSRHandler:ddrphy CSR allocated at Location 6.
INFO:SoCCSRHandler:sdram CSR allocated at Location 7.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x08000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
ERROR:SoCCSRHandler:Not enough Locations.
ERROR:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 4.0KiB Address Space, 2048B Paging, big Ordering (Up to 8 Locations).
CSR Locations: (8)
- ctrl           : 0
- cpu            : 1
- identifier_mem : 2
- uart_phy       : 3
- uart           : 4
- timer0         : 5
- ddrphy         : 6
- sdram          : 7
Traceback (most recent call last):
  File "/build/florent/./versa_ecp5.py", line 154, in <module>
    main()
  File "/build/florent/./versa_ecp5.py", line 129, in main
    soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
  File "/build/florent/./versa_ecp5.py", line 36, in __init__
    versa_ecp5.BaseSoC.__init__(self,
  File "/nix/store/d8w5ci2gp3d36g6g7z7gl0h3nwnfldii-python3.9-litex-boards-1781be166aee867421e0d943f6a62c3397524563/lib/python3.9/site-packages/litex_boards/targets/versa_ecp5.py", line 127, in __init__
    self.add_csr("leds")
  File "/nix/store/svdpbrygiy9zy0p3alf2j89b2fwa8sr7-python3.9-litex-pkg-42d8fc226a4f4e8dfef104257a95f98eb9b10da7/lib/python3.9/site-packages/litex/soc/integration/soc_core.py", line 194, in add_csr
    self.csr.add(csr_name, csr_id, use_loc_if_exists=use_loc_if_exists)
  File "/nix/store/svdpbrygiy9zy0p3alf2j89b2fwa8sr7-python3.9-litex-pkg-42d8fc226a4f4e8dfef104257a95f98eb9b10da7/lib/python3.9/site-packages/litex/soc/integration/soc.py", line 434, in add
    n = self.alloc(name)
  File "/nix/store/svdpbrygiy9zy0p3alf2j89b2fwa8sr7-python3.9-litex-pkg-42d8fc226a4f4e8dfef104257a95f98eb9b10da7/lib/python3.9/site-packages/litex/soc/integration/soc.py", line 465, in alloc
    raise
RuntimeError: No active exception to reraise