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@Lerc
Created November 22, 2014 00:28
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switch (instruction & 0xf000) {
case 0x0000: { //nop movw muls mulsu fmul fmuls fmulsu cpc sbc add
switch (instruction & 0x0c00) {
case 0x0000: {
switch (instruction & 0xff00) {
case 0x0000: { //nop
}
case 0x0100: { //movw
}
case 0x0200: { //muls
}
case 0x0300: { //mulsu, fmul, fmuls, fmulsu
}
}
}
case 0x0400: { //cpc
}
case 0x0800: { //sbc
}
case 0x0c00: { //add
}
}
}
case 0x1000: { //cpse cp sub adc
switch (instruction & 0x0c00) {
case 0x0000: { //cpse
}
case 0x0400: { //cp
}
case 0x0800: { //sub
}
case 0x0c00: { //adc
}
}
}
case 0x2000: { //and eor or mov
switch (instruction & 0x0c00) {
case 0x0000: { //and
}
case 0x0400: { //eor
}
case 0x0800: { //or
}
case 0x0c00: { //mov
}
}
}
case 0x3000: { //cpi
}
case 0x4000: { //sbci
}
case 0x5000: { //subi
}
case 0x6000: { //ori
}
case 0x7000: { //andi
}
case 0x8000 | 0xa000: { // ldd std
}
case 0xb000: { //in out
}
case 0xc000: { //rjmp
}
case 0xd000: { //rcall
}
case 0xe000: { //ldi
}
case 0xf000: { // bld bst sbrc sbrs +conditional branches
}
case 0x9000: {
switch (instruction & 0xfe00) {
case 0x9000: { //lds ld lpm elpm pop
}
case 0x9200: { //sts st push
}
case 0x9400: { // com neg swap inc asr lsr ror dec jmp call bset
// ijmp eijmp bclr ret icall reti eicall sleep break
// wdr lpm R0,Z elpm R0 spm
switch (instruction & 0xfe0f) {
case 0x9200: { //com
}
case 0x9201: { //neg
}
case 0x9202: { //swap
}
case 0x9203: { //inc
}
case 0x9204: { // no instruction for this !?!
}
case 0x9205: { //asr
}
case 0x9206: { //lsr
}
case 0x9207: { //ror
}
case 0x9208: { // bset bclr ret reti sleep break wdr lpm R0,Z elpm R0 spm
}
case 0x9209: { // ijmp eijmp icall eicall
}
case 0x920A: { // dec
}
case 0x920C | 0x920D: { // jmp
}
case 0x920E | 0x920F: { // call
}
}
}
case 0x9600: { // addiw sbiw
}
case 0x9800: { // cbi sbic
}
case 0x9a00: { // sbi sbis
}
case 0x9c00: { // mul
}
}
}
default: {
throw "shouldn't happen";
}
}
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