Organization: CircuitVerse.org
Project: Client-Side Verilog Synthesis
Contributor: Priyank
Mentors: Vivek Ray, Harsh Rao, Nihal
Traditionally, hardware synthesis relies on heavy backend infrastructure, making scaling difficult and real-time feedback slow. The objective of this project was to migrate the Verilog synthesis pipeline completely to the client side. By leveraging WebAssembly (via Yosys) and asynchronous Web Workers, this project enables fast, secure, and offline-capable Verilog compilation directly within the user's browser, eliminating server bottlenecks.
Throughout the summer, I architected the Web Worker communication layer, refactored global DOM states into robust Pinia stores, implemented strict lifecycle and memory-leak guards for the WASM engine, and established a comprehensive suite of Vitest parity tests to ensure the structural consistency of the compiled output.
Below is the complete list of issues and pull requests addressed during the GSoC coding period:
| Task Description | Issue | Pull Request(s) |
|---|---|---|
| Feature: Introduce Client Side Verilog Synthesis via Web Worker for Tauri Desktop | #1058 | #1111 |
| refactor: migrate Tauri environment detection from internals to official isTauri API | #1059 | #1111 |
| chore(synthesis): Add parity tests for Yosys WASM pipeline output | #1135 | #1150 |
| refactor: Migrate Verilog terminal output from window global + DOM to Pinia store | #1054 | #1055 |
| Feature: Add timeout guard for client-side Verilog synthesis worker | #1083 | #1105 |
| Feature: Add VFS Guard for client-side Verilog synthesis output validation | #1085 | #1112 |
| Improve error handling in client-side synthesis to show human-readable syntax errors | #1113 | #1116 |
| Feature: Synthesis worker lifecycle management (prevent WASM memory growth) | #1123 | #1124 |
| Introduce Verilog terminal in /v1 to use Pinia stores instead of DOM globals | #1125 | #1126, #1167 |
| Add comprehensive contributor guide for Client-Side Verilog Synthesis | #1179 | #273 |