XBus controller in Verilog

xbus.sv

-module XBus(uid, ioclk, data);

input [3:0] uid;
input ioclk;
inout [1:0] data;

reg write = 0;
reg [10:0] writeData = 0;

reg ready = 0;
reg [10:0] readData = 0;

reg _idle = 1;
reg _init = 0;
reg _arbitrate = 0;
reg _write = 0;
reg _read = 0;

reg [0:3] _step = 0;
reg _arbFail = 0;
reg _arbData = 0;

assign data[0] = (
	_init |
	(_arbitrate & uid[3 - (_step & 3)]) |
	(_write & writeData[10 - _step])
) ? 1'b1 : 1'bz;

assign data[1] = (
	_init | _read | ready
) ? 1'b1 : 1'bz;

always @(posedge ioclk) begin
	if (_read) begin
		readData = (readData << 1) | data[0];
		if (_step == 14) begin
			ready = 1;
			_read = 0;
			_idle = 1;
		end else _step = _step + 1;
	end else if (_write) begin
		if (_step == 10) begin
			_write = 0;
			_idle = 1;
			write = 0;
		end else _step = _step + 1;
	end else if (_arbitrate) begin
		if (_step == 3) begin
			_arbitrate = 0;
			if (_arbFail) begin
				_arbFail = 0;
				_step = 4;
				_read = 1;
			end else begin
				_step = 0;
				_write = 1;
			end
		end else begin
			if (data[0] ^ uid[3 - (_step & 3)]) _arbFail = 1;
			_step = _step + 1;
		end
	end else if (_init) begin
		_init = 0;
		_arbitrate = 1;
	end else if (_idle) begin
		if (write & ~data[1]) begin
			_idle = 0;
			_init = 1;
			_step = 0;
		end else if (data[0]) begin
			_idle = 0;
			_read = 1;
			_step = 0;
		end
	end
end

endmodule