gistfile1.txt

entity s2mm is
   Port (
      clk: in std_logic;
      rst: in std_logic;
      
      s_ready: out std_logic;
      s_valid: in std_logic;
      s_data: in std_logic_vector(39 downto 0);
      
      mm_ena: out std_logic := '0';
      mm_wea: out std_logic := '0';
      mm_addra: out std_logic_vector(16 downto 0) := (others => '0');
      mm_dina: out std_logic_vector(39 downto 0) := (others => '0')
   );
end s2mm;

architecture Behavioral of s2mm is
   signal addra : unsigned(17 downto 0) := (others => '0');
   signal s_ready_sig : std_logic;
begin
   s_ready_sig <= not addra(17);
   s_ready <= s_ready_sig;
   
   process(clk)
   begin
      if rising_edge(clk) then
         mm_ena <= '0';
         mm_wea <= '0';
         if rst = '1' then
            addra <= (others => '0');
             mm_addra <= (others => '0'); -- this line was absent before, and that caused glitches with "addra+1" apparently
         elsif s_ready_sig = '1' and s_valid = '1'  then
            mm_ena <= '1';
            mm_wea <= '1';
            mm_addra <= std_logic_vector(addra(16 downto 0));
            mm_dina <= s_data;
            addra <= addra + 1;
         end if;
      end if;
   end process;

end Behavioral;