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entity s2mm is | |
Port ( | |
clk: in std_logic; | |
rst: in std_logic; | |
s_ready: out std_logic; | |
s_valid: in std_logic; | |
s_data: in std_logic_vector(39 downto 0); | |
mm_ena: out std_logic := '0'; |
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-- We can start the lagrange (and initialize the mm2s and s2mm) either when we didn't do so already, | |
-- or we did, and an interpolation has finished by now. | |
start_in <= start and ((not started) or (done_in)); | |
s2mm_inst: entity work.s2mm | |
Port Map( | |
clk => clk, | |
rst => start_in, | |
s_ready => so_ready_in, |