half-adder.vhd

--- CEG3155 Lab 2 material.

library IEEE;
use IEEE.Std_Logic_1164.all;

entity halfadder is
port (
    A, B  : in std_logic;
    sum, carry : out std_logic
    );
end halfadder;

architecture halfadder_arch of halfadder is
begin
    sum <= A xor B;
    carry <= A and B;
end halfadder_arch;