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View P_DataPath.v
module DataPath_2(clk, reset, current_PC_address,readA_O, readB_O, A_Reg_IF2ID, B_Reg_IF2ID, Sign_IF2ID, opcode, W_Reg_IF2ID, W_address_WB, alu_result_O, W_data_WB);
input clk, reset;
output [7:0] current_PC_address,readA_O, readB_O;
output [3:0] opcode, A_Reg_IF2ID, B_Reg_IF2ID, W_Reg_IF2ID, Sign_IF2ID, W_address_WB;
output [7:0] alu_result_O, W_data_WB;
View P_Mux3.v
module MUX3(a,b,sel,c);
input [7:0] a,b;
input sel;
output reg [7:0]c;
always @(*)begin
if(sel==0)
c = a;
else
c = b;
end
View P_EXE_Pipeline.v
module EXE2WB(clk, WB, mem_out, alu_result, mux1_w_reg, mux1_w_reg_O, alu_O, mem_out_O, mux3, regwrt
);
input clk;
input [1:0] WB;
input [7:0] mem_out;
input [7:0] alu_result;
input [3:0] mux1_w_reg;
output reg [3:0] mux1_w_reg_O;
output reg [7:0] alu_O, mem_out_O;
View P_ALU.v
module ALU(ain,bin,func,result,z,carry);
//input clk;
input [7:0]ain;
input [7:0]bin;
output reg [7:0]result;
reg [8:0]temp;
output reg carry;
input [3:0]func;
output reg z;
initial begin
View P_Adder.v
module ADDER(A,B,out);
input [7:0] A,B;
output reg [7:0] out;
reg [7:0] temp;
initial begin
out <= 0;
end
always @(*)begin
temp = B<<1;
out = A + temp - 2;
View P_ID_Pipeline.v
module IF2ID(clk, next_PC_address, opcode, A_Reg, B_Reg, W_Reg, Sign, freeze, flush,
next_PC_address_O, opcode_O, A_Reg_O, B_Reg_O, W_Reg_O, Sign_O);
input clk;
input [7:0] next_PC_address;
input [3:0] opcode;
input [3:0] A_Reg;
input [3:0] B_Reg;
input [3:0] W_Reg;
input [3:0] Sign;
View 16_Bit_Gating_ALU.v
module ALU(clk_ALU,ain,bin,func,result,z,carry);
input clk_ALU;
input [7:0]ain;
input [7:0]bin;
output reg [7:0]result;
reg [8:0]temp;
output reg carry;
input [3:0]func;
output reg z;
initial begin
@Shashi18
Shashi18 / DataPath.v
Created Mar 22, 2019
DataPath Verilog File for 16 bit RISC Processor
View DataPath.v
module DATAPATH(clk, out, A_reg, B_reg, W_reg, read_data_A, read_data_B, opcode, alu_result, write_data, sel3,carry, z_flag);
input clk;
wire [15:0]instruction;
wire [7:0]sign_out;
wire [7:0]in;
wire [7:0]b_out, in_1, in_2, in_3, in_4;
output [7:0] out;
wire [3:0] Sign, Write_reg;
wire [3:0] aluop; wire [7:0] write_data; wire [7:0] read_data;
wire [7:0]read_data_A, read_data_B, mux2_out, data_out;
View 16_Bit_Risc_Mux1.v
module MUX1(a,b,sel,c);
input [3:0] a,b;
input sel;
output reg [3:0]c;
always @(*)begin
View 16_Bit_Risc_ALU.v
module ALU(clk,ain,bin,func,result,z,carry);
input clk;
input [7:0]ain;
input [7:0]bin;
output reg [7:0]result;
reg [8:0]temp;
output reg carry;
input [3:0]func;
output reg z;
initial begin
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