16_Bit_Risc_ALU.v

module ALU(clk,ain,bin,func,result,z,carry);
input clk;
input [7:0]ain;
input [7:0]bin;
output reg [7:0]result;
reg [8:0]temp;
output reg carry;
input [3:0]func;
output reg z;
initial begin
	result = 0;
	z = 0;
	carry = 0;
	temp = 0;
end

always @(negedge clk)begin
if(func==4'b0000)begin //ADD
temp = ain + bin;
result = temp[7:0];
carry = temp[8];
if(result==0)
	z = 1;
else
	z = 0;
end
else if(func==4'b0001)begin // SUBTRACT
temp = ain - bin;
result = temp[7:0];
carry = temp[8];
if(result==0)
	z = 1;
else
	z = 0;
end
else if(func==4'b0010)begin // INCREMENT BY 1
temp = ain + 1;
result = temp[7:0];
carry = temp[8];
if(result==0)
	z = 1;
else
	z = 0;
end
else if(func==4'b0011)begin // DECREMENT BY 1
temp = ain - 1;
result = temp[7:0];
carry = temp[8];
if(result==0)
	z = 1;
else
	z = 0;
end
// LOGICAL OPERATIONS //
else if(func==4'b0100)begin // ADD Immediate
result = ain + bin;
carry = 0;
if(result==0)
	z = 1;
else
	z = 0;
end 
else if(func==4'b0101)begin // Subtract Immediate
result = ain - bin;
carry = 0;
if(result==0)
	z = 1;
else
	z = 0;
end //AND
else if(func==4'b0110)begin // EX OR
result = ain^bin;
carry = 0;
if(result==0)
	z = 1;
else
	z = 0;
end 
else if(func==4'b0111)begin  // NAND
result[0] = ~(ain[0]&bin[0]);
result[1] = ~(ain[1]&bin[1]);
result[2] = ~(ain[2]&bin[2]);
result[3] = ~(ain[3]&bin[3]);
result[4] = ~(ain[4]&bin[4]);
result[5] = ~(ain[5]&bin[5]);
result[6] = ~(ain[6]&bin[6]);
result[7] = ~(ain[7]&bin[7]);
carry = 0;
if(result==0)
	z = 1;
else
	z = 0;
end //NAND
else if(func==4'b1000)begin  // NOT
result[0] = ~ain[0];
result[1] = ~ain[1];
result[2] = ~ain[2];
result[3] = ~ain[3];
result[4] = ~ain[4];
result[5] = ~ain[5];
result[6] = ~ain[6];
result[7] = ~ain[7];
carry = 0;
if(result==0)
	z = 1;
else
	z = 0;
end //NOT

else if(func==4'b1001)begin // BEQ Function
if(ain==bin)
	result=0;
carry = 0;
if(result==0)
	z = 1;
else
	z = 0;
end 

else if(func==4'b1010)begin // BNE Function
temp=ain-bin;
carry = temp[8];
result = temp[7:0];
if(result==0)
	z = 1;
else
	z = 0;
end 

else if(func==4'b1011)begin // BLT Function
temp=ain-bin;
carry = temp[8];
result = temp[7:0];
if(result==0)
	z = 1;
else
	z = 0;
end 

else if(func==4'b1100)begin // BGT Function
temp=bin-ain;
carry = temp[8];
result = temp[7:0];
if(result==0)
	z = 1;
else
	z = 0;
end 

else if(func==4'b1110)begin // LOAD
result = ain + bin;
carry = 0;
if(result==0)
	z = 1;
else
	z = 0;
end 

else if(func==4'b1111)begin // STORE
result = ain + bin;
carry = 0;
if(result==0)
	z = 1;
else
	z = 0;
end

else begin 
result = 4'bxxxx;
carry = 0;
end //Default
if(result==0)
	z = 1;
else
	z = 0;
end

endmodule

16_Bit_Risc_Control.v

module CONTROL(clk,opcode,Mux1,reg_wrt,BEQ, BNE, BLT, BGT, Mux8, re, wr, alu_op, Mux2, Mux3, pc_select);
input clk;
input [3:0] opcode;
output reg[3:0]alu_op;
output reg reg_wrt,re,wr,Mux1,Mux2,BEQ, BNE, BLT, BGT;
output reg [3:0] Mux8;
output reg Mux3, pc_select;
reg [3:0]pstate;
reg sign;
reg [3:0]count;
parameter s0 = 4'b0000,s1 = 4'b0001, s2=4'b0010, s3=4'b0011, s4=4'b0100, s5=4'b0101;
initial begin
pstate = s0;
sign = 0;
pc_select = 0;
count = 0;
end

always @(negedge clk)begin
alu_op <= opcode;
case(pstate)
//*********************************************************************************************************************
s0:begin  // Initial State
reg_wrt<=1'b0;
re<=1'b1;
wr<=1'b1;
Mux1<=1'b1;
Mux2<=1'b1;
Mux3<=2'b1;
BEQ<=1'b1;
pstate <= s1;
pc_select <= 0;
end
//*********************************************************************************************************************
s1:begin  // After Instruction Fetch Cycle
reg_wrt <= 1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux1 <= 1'b1;
Mux2 <= 1'b0;
Mux3 <= 1'b0;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
pstate <= s2;
pc_select <= 0;
end
//*********************************************************************************************************************
s2:begin  // After REG Stage
case(opcode)
4'b0000:begin
reg_wrt<=1'b0;
re<=1'b0;
wr<=1'b0;
Mux2<=1'b0;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
pc_select <= 0;
pstate<= s3;
end

4'b0001:begin  /* DO NOT MODIFY R-FORMAT STARTS HERE */
//alu_op<=4'b0001;  // Subtraction   
reg_wrt<=1'b0;
re<=1'b0;
wr<=1'b0;
Mux2 <= 1'b0;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
pstate<= s3;
end
//*********************************************************************************************************************
4'b0010:begin
//alu_op<=4'b0010; //Shift by 1 Right
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux2 <= 1'b0;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
pstate <= s3;
end
//*********************************************************************************************************************
4'b0011:begin
//alu_op<=4'b0010; //Shift by 1 Right
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux2 <= 1'b0;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
pstate <= s3;
end
//*********************************************************************************************************************
4'b0100:begin
//alu_op<=4'b0010; //ADD_I
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux1 <= 1'b0;
Mux2 <= 1'b1;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
pstate <= s3;
end
//*********************************************************************************************************************

4'b0101:begin
//alu_op<=4'b0010; // SUB_I
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux1 <= 1'b0;
Mux2 <= 1'b1;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
pstate <= s3;
end
//*********************************************************************************************************************

4'b0110:begin
//alu_op<=4'b0010; //Shift by 1 Right
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux2 <= 1'b0;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
pstate <= s3;
end
//*********************************************************************************************************************

4'b0111:begin
//alu_op<=4'b0010; //Shift by 1 Right
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux2 <= 1'b0;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
pstate <= s3;
end
//*********************************************************************************************************************

4'b1000:begin
//alu_op<=4'b0010; //Shift by 1 Right
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux2 <= 1'b0;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
pstate <= s3;
end
//*********************************************************************************************************************

4'b1001:begin // BRANCH AIN == BIN BEQ
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux2 <= 1'b0;
BEQ <= 1'b1;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
Mux8 <= {BEQ,BNE,BLT,BGT};
count <= count + 1;
if (count < 1)
	pstate <= s2;
else
	pstate <= s5;
end
//*********************************************************************************************************************

4'b1010:begin // BRANCH AIN != BIN BNE
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux2 <= 1'b0;
BEQ <= 1'b0;
BNE <= 1'b1;
BLT <= 1'b0;
BGT <= 1'b0;
Mux8 <= {BEQ,BNE,BLT,BGT};
count <= count + 1;
if (count < 1)
	pstate <= s2;
else
	pstate <= s5;
end
//*********************************************************************************************************************

4'b1011:begin // BRANCH AIN < BIN
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux2 <= 1'b0;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b1;
BGT <= 1'b0;
Mux8 <= {BEQ,BNE,BLT,BGT};
count <= count + 1;
if (count < 1)
	pstate <= s2;
else
	pstate <= s5;
end
//*********************************************************************************************************************

4'b1100:begin // BRANCH IF AIN > BIN
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux2 <= 1'b0;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b1;
Mux8 <= {BEQ,BNE,BLT,BGT};
count <= count + 1;
if (count < 1)
	pstate <= s2;
else
	pstate <= s5;
end
//*********************************************************************************************************************

4'b1101:begin // BRANCH DIRECTLY
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b0;
Mux2 <= 1'b0;
BEQ <= 1'b1;
BNE <= 1'b1;
BLT <= 1'b1;
BGT <= 1'b1;
Mux8 <= {BEQ,BNE,BLT,BGT};
count <= count + 1;
if (count < 1)
	pstate <= s2;
else
	pstate <= s5;
end
//*********************************************************************************************************************

4'b1110:begin // LOAD
reg_wrt<=1'b0;
re <= 1'b1;
wr <= 1'b0;
Mux1 <= 1'b0;
Mux2 <= 1'b1;
Mux3 <= 1'b0;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
pstate <= s3;
end
//*********************************************************************************************************************

4'b1111:begin // STORE
reg_wrt<=1'b0;
re <= 1'b0;
wr <= 1'b1;
Mux1 <= 1'b1;
Mux2 <= 1'b1;
Mux3 <= 1'b0;
BEQ <= 1'b0;
BNE <= 1'b0;
BLT <= 1'b0;
BGT <= 1'b0;
pstate <= s4;
end
//*********************************************************************************************************************

endcase
end

s3:begin  // After ALU Stage
reg_wrt<=1'b0;
//Mux2<=1'b0;
pstate <= s4;
end

s4:begin  // After Memory Stage
if(opcode != 1111) begin
	reg_wrt <= 1'b1;
	Mux3 <= 1;
end
else
	reg_wrt <= 1'b0;
re<=1'b0;
wr<=1'b0;
pc_select <= 0;
Mux8 <= {BEQ,BNE,BLT,BGT};
pstate <= s5;
end

s5:begin  // After Write Back Cycle
reg_wrt<=1'b0;
re<=1'b0;
wr<=1'b0;
Mux3 <= 1'b0;
pstate <= s1;
pc_select <= 1;
count<=0;
end



endcase
end

endmodule

16_Bit_Risc_Data_Memory.v

module RAM(clk,address,data_in,data_out,re,wr);
input [7:0]address;
input [7:0]data_in;
input clk,re,wr;
output reg [7:0]data_out;
reg[7:0] mem [0:30];
initial begin
mem[4]=15;
mem[7]=0;
end
always @(negedge clk)begin
if(wr)
mem[address] <= data_in;
if(re)
data_out <= mem[address];
end
/*always @(address or re)begin
if(re)begin
data = mem[address];
end
end*/

endmodule