module Master(scl,mosi,miso,ss1,ss2,ss3,ss4);
output reg scl;
input [0:0]miso;
output reg [0:0]mosi;
output reg ss1;
output reg ss2;
output reg ss3;
output reg ss4;
reg [16:0]xx;
initial begin
scl = 0;
ss1 = 1;
#10 ss1 = 0;
xx = 17'b010101011_00011001;
end
always @(negedge ss1)
slock ;
always @(posedge scl)begin
mosi = xx[16];
xx = xx<<1;
end
task slock;
repeat (38)
#2 scl = !scl;
endtask: slock;
Slave1 slv1(scl,miso,mosi,ss1);
endmodule