Skip to content

Instantly share code, notes, and snippets.

@Shashi18 Shashi18/P_Adder.v
Last active May 12, 2019

Embed
What would you like to do?
module ADDER(A,B,out);
input [7:0] A,B;
output reg [7:0] out;
reg [7:0] temp;
initial begin
out <= 0;
end
always @(*)begin
temp = B<<1;
out = A + temp - 2;
end
endmodule
//module CONTROL(opcode,Mux1,Branch, re, wr, alu_op, Mux2, Mux3_reg_wrt, pc_select);
module CONTROL(clk, opcode, Signal, EXE, MEM, WB, pc_select, Flush);
input clk;
input [3:0] Signal;
input [3:0] opcode;
output reg [5:0]EXE;
output reg [5:0]MEM;
output reg [1:0]WB;
output reg pc_select;
output reg Flush;
//EXE[5] = Mux2 Select Line
//EXE[4] = Mux1 Select Line
//EXE[3:0] = AluOp
//MEM[5] = Write
//MEM[4] = Read
//MEM[3:0] = Branch
//WB[1] = Mux3 Select Line
//WB[0] = RegWrt
reg sign;
initial begin
sign = 0;
pc_select = 1;
Flush = 0;
end
always @(*)begin
case(opcode)
4'b0001:begin // Addition
EXE = 6'b010001; MEM = 6'b000000; WB = 2'b11; pc_select = 1; Flush = 0;
end
4'b0010:begin // Subtraction
EXE = 6'b010010; MEM = 6'b000000; WB = 2'b11; pc_select = 1; Flush = 0;
end
4'b0011:begin // Increment
EXE = 6'b010011; MEM = 6'b000000; WB = 2'b11; pc_select = 1; Flush = 0;
end
4'b0100:begin // Decrement
EXE = 6'b010100; MEM = 6'b000000; WB = 2'b11; pc_select = 1; Flush = 0;
end
4'b0101:begin // Add Immediate
EXE = 6'b110101; MEM = 6'b000000; WB = 2'b11; pc_select = 1; Flush = 0;
end
4'b0110:begin // Subtract Immediate
EXE = 6'b110110; MEM = 6'b000000; WB = 2'b11; pc_select = 1; Flush = 0;
end
4'b1001:begin // BEQ
EXE = 6'b0; MEM = 6'b0; WB = 2'b0; Flush = Signal[0];
end
4'b1010:begin // BLT
EXE = 6'b0; MEM = 6'b0; WB = 2'b0; Flush = Signal[2];
end
4'b1011:begin // BGT
EXE = 6'b0; MEM = 6'b0; WB = 2'b0; Flush = Signal[1];
end
4'b1101:begin // BNE
EXE = 6'b0; MEM = 6'b0; WB = 2'b0; Flush = Signal[3];
end
4'b1110:begin // LW
EXE = 6'b10_0001; MEM = 6'b10_0000; WB = 2'b01; Flush = 0;
end
4'b1111:begin // SW
EXE = 6'b1x_0001; MEM = 6'b01_0000; WB = 2'b00; Flush = 0;
end
default:begin
EXE = 6'b0;
MEM = 6'b0;
WB = 2'b0;
Flush = 0;
end
endcase
end
endmodule
module SIGN(a,b);
input [3:0]a;
output reg [7:0]b;
always @(a or b)begin
if(a[3]==1)
b = {4'b1111,a};
else
b = {4'b0000,a};
end
endmodule
module ID_EXE(clk, new_address_in, opcode, A_address, B_address, W_address, Sign, W_address_WB, W_data_WB, Reg_write, B_Hazard,
Extend, A_data, B_data, new_address_out, W_address_out, B_address_out, A_address_out, WB, MEM, EX, test, Flush);
//IPs
input clk;
input [7:0]new_address_in;
input [3:0]opcode;
input [3:0]A_address;
input [3:0]B_address;
input [3:0]W_address;
input [3:0]Sign;
input [3:0]W_address_WB;
input [7:0]W_data_WB;
input Reg_write;
input [1:0] B_Hazard;
//OPs
output [7:0] Extend;
output [7:0] A_data;
output [7:0] B_data;
output [7:0] new_address_out;
output [3:0] A_address_out;
output [3:0] W_address_out;
output [3:0] B_address_out;
output [5:0] EX;
output [5:0] MEM;
output [1:0] WB;
output test;
output Flush;
//assign new_address_out = new_address_in;
assign W_address_out = W_address;
assign B_address_out = B_address;
assign A_address_out = A_address;
wire p, q, r, s;
wire [3:0] Comparator_Out;
and A(p, MEM[3], B_Hazard[1]);
and B(q, MEM[2], ~B_Hazard[1]);
and C(r, MEM[1], B_Hazard[0]);
and D(s, MEM[0], ~B_Hazard[0]);
assign test = Flush;
CONTROL CU(clk, opcode, Comparator_Out, EX, MEM, WB,/* pc_enable*/, Flush);
//module Register(clk,readA,readB,dest,data,reg_wrt,readA_out,readB_out);
Register Reg_File (clk, A_address, B_address, W_address_WB, W_data_WB, Reg_write, A_data, B_data);
ADDER add(new_address_in, Extend, new_address_out);
SIGN extend_7bit (Sign, Extend);
Comparator Mag(A_data, B_data, Comparator_Out);
endmodule
module Register(clk,readA,readB,dest,data,reg_wrt,readA_out,readB_out);
input reg_wrt;
input [3:0]readA,readB,dest;
input [7:0]data;
input clk;
reg [7:0] Register [0:15];
initial begin
Register[1]=1; //Random values stored
Register[2]=2;
Register[3]=3;
Register[4]=4;
Register[5]=5; // You can change any value within this initial block
Register[6]=6;
Register[7]=7;
Register[8]=8;
Register[9]=9;
Register[10]=10;Register[12]=12;
Register[11]=11;
end
output [7:0]readA_out,readB_out;
assign readA_out = Register[readA];
assign readB_out = Register[readB];
always @(posedge clk)
if(reg_wrt==1)
Register[dest]<=data;
endmodule
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
You can’t perform that action at this time.