DataPath Verilog File for 16 bit RISC Processor

DataPath.v

module DATAPATH(clk, out, A_reg, B_reg, W_reg, read_data_A, read_data_B, opcode, alu_result, write_data, sel3,carry, z_flag);
input clk;
wire [15:0]instruction;
wire [7:0]sign_out;
wire [7:0]in;
wire [7:0]b_out, in_1, in_2, in_3, in_4;
output [7:0] out;
wire [3:0] Sign, Write_reg;
wire [3:0] aluop; wire [7:0] write_data; wire [7:0] read_data;
wire [7:0]read_data_A, read_data_B, mux2_out, data_out;
wire select4;
reg carry_bit;
wire sel4;
output carry, z_flag;
output [3:0] opcode;
wire [3:0] sel8;
output [7:0] alu_result;
output [3:0] A_reg, B_reg, W_reg;
output [7:0] read_data_A, read_data_B;
output [7:0] write_data;
output sel3;

always @(negedge clk)
	carry_bit <= carry;

PC programcounter(in,pc_select,clk,out);
//ADDER_PC add1(out,pc_select,increment,clk);
INSTRUCTION_MEMORY im(out,clk,opcode,A_reg, B_reg, W_reg,Sign);
CONTROL control_unit(clk, opcode, sel1, reg_write, BEQ, BNE, BLT, BGT, sel8, read, write, aluop, sel2, sel3, pc_select);
MUX1 multiplexor1(B_reg, W_reg, sel1, Write_reg);
REGISTER_FILE register_file(clk,A_reg,B_reg, Write_reg, write_data,reg_write,read_data_A,read_data_B);
MUX2 mux2(read_data_B,sign_out,sel2,mux2_out);
ALU alux(clk,read_data_A,mux2_out,aluop,alu_result,z_flag,carry);
RAM datamemory(clk,alu_result,read_data_B,data_out, read , write);

MUX3 mux3(data_out,alu_result,sel3,write_data);

SIGN xtend(Sign,sign_out);

ADDER branch(out, sign_out, b_out, clk);
//ADDER carry_branch(out, sign_out, c_out, clk);
and branch_if_zero(BEQ_1, z_flag, BEQ);
MUX4 mux4(out, b_out, BEQ_1, in_1); // BEQ
and branch_if_not_zero(BNE_1, ~z_flag, BNE);
MUX4 mux5(out, b_out, BNE_1, in_2); // BNE
and branch_if_less(BLT_1, carry, BLT);
MUX4 mux6(out, b_out, BLT_1, in_3); // BLT
and branch_if_greater(BGT_1, ~carry, BGT);
MUX4 mux7(out, b_out, BGT_1, in_4); // BGT
MUX8 mux8(out, in_1, in_2, in_3, in_4, b_out, sel8, in); 

endmodule

TestBench.v

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:59:03 03/20/2019
// Design Name:   DATAPATH
// Module Name:   C:/Users/Shashi Suman/Desktop/My/RISC/Test.v
// Project Name:  RISC
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: DATAPATH
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Test;

	// Inputs
	reg clk;

	// Outputs
	wire clock;
	wire [7:0] out;
	wire [3:0] A_reg;
	wire [3:0] B_reg;
	wire [3:0] W_reg;
	wire [3:0] opcode;
	wire [7:0] read_data_A;
	wire [7:0] read_data_B;
	wire [7:0] alu_result;
	wire [7:0] write_data;
	wire sel3;
	wire carry;
	wire z_flag;

	// Instantiate the Unit Under Test (UUT)
	DATAPATH uut (
		.clk(clk), 
		.out(out), 
		.A_reg(A_reg), 
		.B_reg(B_reg), 
		.W_reg(W_reg), 
		.read_data_A(read_data_A), 
		.read_data_B(read_data_B), 
		.opcode(opcode), 
		.alu_result(alu_result), 
		.write_data(write_data), 
		.sel3(sel3), 
		.carry(carry), 
		.z_flag(z_flag)
	);

	initial begin
		// Initialize Inputs
		clk = 0;

		// Wait 100 ns for global reset to finish
        
		// Add stimulus here

	end
       always #2 clk <= ~clk;  
assign clock = clk;		 
endmodule