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@Shashi18 Shashi18/P_ALU.v
Created May 12, 2019

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module ALU(ain,bin,func,result,z,carry);
//input clk;
input [7:0]ain;
input [7:0]bin;
output reg [7:0]result;
reg [8:0]temp;
output reg carry;
input [3:0]func;
output reg z;
initial begin
result = 0;
z = 0;
carry = 0;
temp = 0;
end
always @(*)begin
if(func==4'b0001)begin //ADD
temp = ain + bin;
result = temp[7:0];
carry = temp[8];
if(result==0)
z = 1;
else
z = 0;
end
else if(func==4'b0010)begin // SUBTRACT
temp = ain - bin;
result = temp[7:0];
carry = temp[8];
if(result==0)
z = 1;
else
z = 0;
end
else if(func==4'b00011)begin // INCREMENT BY 1
temp = ain + 1;
result = temp[7:0];
carry = temp[8];
if(result==0)
z = 1;
else
z = 0;
end
else if(func==4'b0100)begin // DECREMENT BY 1
temp = ain - 1;
result = temp[7:0];
carry = temp[8];
if(result==0)
z = 1;
else
z = 0;
end
else if(func==4'b0101)begin // ADD Immediate
result = ain + bin;
carry = 0;
if(result==0)
z = 1;
else
z = 0;
end
else if(func==4'b0110)begin // Subtract Immediate
result = ain - bin;
carry = 0;
if(result==0)
z = 1;
else
z = 0;
end //AND
else if(func==4'b0111)begin // EX OR
result = ain^bin;
carry = 0;
if(result==0)
z = 1;
else
z = 0;
end
else if(func==4'b0111)begin // NAND
result[0] = ~(ain[0]&bin[0]);
result[1] = ~(ain[1]&bin[1]);
result[2] = ~(ain[2]&bin[2]);
result[3] = ~(ain[3]&bin[3]);
result[4] = ~(ain[4]&bin[4]);
result[5] = ~(ain[5]&bin[5]);
result[6] = ~(ain[6]&bin[6]);
result[7] = ~(ain[7]&bin[7]);
carry = 0;
if(result==0)
z = 1;
else
z = 0;
end //NAND
else if(func==4'b1000)begin // NOT
result[0] = ~ain[0];
result[1] = ~ain[1];
result[2] = ~ain[2];
result[3] = ~ain[3];
result[4] = ~ain[4];
result[5] = ~ain[5];
result[6] = ~ain[6];
result[7] = ~ain[7];
carry = 0;
if(result==0)
z = 1;
else
z = 0;
end //NOT
else if(func==4'b1001)begin // BEQ Function
if(ain==bin)
result=0;
carry = 0;
if(result==0)
z = 1;
else
z = 0;
end
else if(func==4'b1010)begin // BNE Function
temp=ain-bin;
carry = temp[8];
result = temp[7:0];
if(result==0)
z = 1;
else
z = 0;
end
else if(func==4'b1011)begin // BLT Function
temp=ain-bin;
carry = temp[8];
result = temp[7:0];
if(result==0)
z = 1;
else
z = 0;
end
else if(func==4'b1100)begin // BGT Function
temp=bin-ain;
carry = temp[8];
result = temp[7:0];
if(result==0)
z = 1;
else
z = 0;
end
else if(func==4'b1110)begin // LOAD
result = ain + bin;
carry = 0;
if(result==0)
z = 1;
else
z = 0;
end
else if(func==4'b1111)begin // STORE
result = ain + bin;
carry = 0;
if(result==0)
z = 1;
else
z = 0;
end
else begin
result = 4'bxxxx;
carry = 0;
end //Default
if(result==0)
z = 1;
else
z = 0;
end
endmodule
module EXE_MEM(clk, alu_code, mux2_in, mux1_in, new_address_in, A_data, B_data, Extend, A_register, B_register, W_register_WB, MEM, MEM_regwrt, WB_regwrt, MEM_data, WB_data, MEM_dest, WB_dest,
zero, carry, new_address_out, alu_result, Write_data_to_RAM, Mux1_O, MEM_O, Branch_Taken);
input clk;
input [3:0] alu_code;
input mux2_in;
input mux1_in;
input [7:0] new_address_in;
input [7:0] A_data;
input [7:0] B_data;
input [7:0] Extend;
input [3:0] A_register;
input [3:0] B_register;
input [3:0] W_register_WB;
input [5:0] MEM;
input MEM_regwrt, WB_regwrt;
input [7:0] MEM_data, WB_data;
input [3:0] MEM_dest, WB_dest;
output zero,carry;
output [7:0] new_address_out, alu_result;
output [7:0] Write_data_to_RAM;
output [3:0] Mux1_O;
output [3:0] Branch_Taken;
output [1:0] MEM_O;
wire [7:0] mux2_out, out_for_ALU, out_for_mux2;
wire [1:0] ForA, ForB;
MUX4 ForwardA(A_data, MEM_data, WB_data, ForA, out_for_ALU);
MUX4 ForwardB(B_data, MEM_data, WB_data, ForB, out_for_mux2);
MUX2 mux2(out_for_mux2, Extend, mux2_in, mux2_out);
MUX1 mux1(B_register, W_register_WB, mux1_in, Mux1_O);
ALU Arithmetic(out_for_ALU, mux2_out, alu_code, alu_result, zero, carry);
Forward Forwarding_Unit(MEM_regwrt, WB_regwrt, MEM_dest, WB_dest, A_register, B_register, ForA, ForB);
ADDER add(new_address_in, Extend, new_address_out);
wire p, q, r, s;
and a(p, MEM[3], zero);
and b(q, MEM[2], ~zero);
and c(r, MEM[1], carry);
and d(s, MEM[0], ~carry);
assign Branch_Taken = {p, q, r, s};
assign MEM_O = MEM[5:4];
assign Write_data_to_RAM = B_data;
endmodule
module Forward(MEM_regwrt, WB_regwrt, MEM_dest, WB_dest, A_reg, B_reg,
ForA, ForB);
input MEM_regwrt;
input WB_regwrt;
input [3:0]MEM_dest;
input [3:0]WB_dest;
input [3:0]A_reg;
input [3:0]B_reg;
output reg[1:0]ForA;
output reg[1:0]ForB;
always @(*)begin
if(MEM_regwrt==1 && (MEM_dest==A_reg))
ForA = 1;
else if(MEM_regwrt==1 && MEM_dest==B_reg)
ForB = 1;
else if(WB_regwrt==1 && WB_dest==A_reg && (MEM_dest != A_reg || MEM_regwrt == 0))
ForA = 2;
else if(WB_regwrt==1 && WB_dest==B_reg && (MEM_dest != B_reg || MEM_regwrt == 0))
ForB = 2;
else begin
ForA = 0;
ForB = 0;
end
end
endmodule
module MUX1(a,b,sel,c);
input [3:0] a,b;
input sel;
output reg [3:0]c;
always @(*)begin
if(sel==0)
c = a;
else
c = b;
end
endmodule
module MUX2(a,b,sel,c);
input [7:0] a,b;
input sel;
output reg [7:0]c;
always @(*)begin
if(sel==0)
c = a;
else
c = b;
end
endmodule
module MUX4(a, b, c, sel,d);
input [7:0] a;
input [7:0] b;
input [7:0] c;
input [1:0]sel;
output reg [7:0]d;
always @(*)begin
case(sel)
2'b00: d = a;
2'b01: d = b;
2'b10: d = c;
endcase
end
endmodule
////////////////////////////////////////////////////////////////////////////////
module EXE2MEM(clk, WB, MEM, Jump_address, alu_result, mem_data_in, mux1_in, zero, carry,
WB_O, Branch, read, write, zero_O, carry_O, mux1_O,alu_RAM_address, RAM_data
);
input clk;
input [1:0] WB;
input [1:0] MEM;
input [7:0] Jump_address,alu_result, mem_data_in;
input [3:0] mux1_in;
input zero, carry;
output reg [1:0]WB_O;
output reg [3:0] Branch;
output reg read;
output reg write;
output reg zero_O;
output reg carry_O;
output reg [3:0] mux1_O;
output reg [7:0]alu_RAM_address;
output reg [7:0]RAM_data;
always @(negedge clk)begin
WB_O <= WB;
//Branch <= MEM[3:0];
read <= MEM[1];
write <= MEM[0];
zero_O <= zero;
carry_O <= carry;
mux1_O <= mux1_in;
alu_RAM_address <= alu_result;
RAM_data <= mem_data_in;
end
endmodule
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