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Last active November 10, 2018 07:13
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shift.v
module shifty(output debug_data, input debug_clock, input debug_strobe);
reg[15:0] shift;
assign debug_data = shift[15];
always @(posedge debug_clock) begin
if(debug_strobe) shift <= 16'h BEEF;
else shift <= {shift[14:0], 1'b1};
end
endmodule
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