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@TRBlount
Last active October 21, 2022 10:19
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entity CLA_4 is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
ci : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
co : out STD_LOGIC);
end CLA_4;
architecture Behavioral of CLA_4 is
signal temp_sum : std_logic_vector(3 downto 0) := (others => '0'); -- Sum while waiting for carrys from lookahead logic
signal c : std_logic_vector(4 downto 0) := (others => '0'); -- Carry signals
signal p : std_logic_vector(3 downto 0) := (others => '0'); -- Propagate signals
signal g : std_logic_vector(3 downto 0) := (others => '0'); -- Generate signals
begin
temp_sum <= x xor y; -- Compute intermediate sum
g <= x and y; -- Compute generate bits
p <= x or y; -- Compute propagate bits
c(0) <= ci; -- Need carry to be the carry-in to the whole adder
carry: process(c, p, g)
begin
cll: for i in 0 to 3 loop -- Carry Lookahead Logic
c(i+1) <= g(i) or (p(i) and c(i)); -- Compute the next carry
end loop;
end process;
co <= c(4); -- Set the carry out to be the last carry from the CLL
s <= temp_sum xor c(3 downto 0); -- Compute final sum
end Behavioral;
entity CLA_16 is
Port ( X : in STD_LOGIC_VECTOR (15 downto 0);
Y : in STD_LOGIC_VECTOR (15 downto 0);
Ci : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (15 downto 0);
Co : out STD_LOGIC);
end CLA_16;
architecture Structural of CLA_16 is
component CLA_4 is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
ci : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
co : out STD_LOGIC);
end component CLA_4;
signal c : std_logic_vector(4 downto 0) := (others => '0');
begin
c(0) <= Ci;
gen: for i in 0 to 3 generate -- Generate each 4-bit adder result and carry out
add16: CLA_4 port map( x => X((4*(i+1))-1 downto 4*i),
y => Y((4*(i+1))-1 downto 4*i),
ci => c(i),
s => S((4*(i+1))-1 downto 4*i),
co => c(i+1));
end generate;
Co <= c(4);
end Structural;
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