module biShiftReg74194(D, S, SDR, SDL, CLRb, CLK, Q);
  input[3:0] D;
  input[1:0] S;
  input SDR, SDL, CLRb, CLK;
  output reg [3:0] Q;
  /*initial begin
  Q <= 0;
  end*/
  always @(posedge CLK, negedge CLRb)
    begin
      if(CLRb == 0)
        Q <= 4'b0000;
      else 
        /*if(CLK == 1)
        */
        begin
          case(S)
            0: Q <= Q;
            1: Q <= {Q[2:0],SDL};
            2: Q <= {SDR, Q[3:1]};
            3: Q <= D;
          endcase
        end
    end
endmodule