My simple intro to Makefiles, generalized.

Makefile Tutorial

Working with Makefiles

Make syntax:

You need to know only two types of statements: DEFINITIONS and DEPENDENCIES

Use equal sign to define variables, and use dollar sign plus parentheses to reference them.
e.g.

IFORT = /opt/intel10/fcd/latest/bin/ifort
OPTIONS = -O2
COMPILE = $(IFORT) $(OPTIONS)

Use colon to define dependencies.  This tells Make that the file on the left is dependent on 
everything to the right of the colon.

e.g., a single output with two dependencies:

program : main.for subs.for

When Make encounters a dependency statement, it checks to see if any of the files on the right 
are newer than the file on the left.  If so, it attempts to build the file on the left, using 
the “build rule” for the file.  The build rule is all tab-starting lines below the dependency 
definition, until it hits a line that doesn’t start with tab.

e.g.
program : main.for subs.for
        $(COMPILE) main.for subs.for –o program

This will check the dates of main.for and subs.for, and if either is newer than program, it 
will execute the previously defined $(COMPILE) statement.

Make can also be given general patterns within its build rules, and it has some built-in implicit
rules for building certain types of files without explicitly telling it how.  Neither of those 
types of statements are detailed in this guide, but an Internet search on Makefile pattern rules or 
Implicit Makefile rules should lead to further information.

Although definitions are not required to be all caps, that is the normal convention and is kept for 
our Makefiles.

One last Makefile statement we use is the “include” statement, by which a Makefile can read another 
file.  Make simply parses the included file as if it were inserted into the current Makefile at the 
position of the include statement.