drm-amdgpu-vulkan-haiku-2.log

drmGetDevices2()
drmIoctl(3, (100, VERSION, 64, RW)) -> (
  version: 3.42.0
  name: "(null)"
  date: "(null)"
  desc: "(null)"

drmIoctl(3, (100, VERSION, 64, RW)) -> (
  version: 3.42.0
  name: "amdgpu"
  date: "20150101"
  desc: "AMD GPU"

drmIoctl(3, (100, VERSION, 64, RW)) -> (
  version: 3.42.0
  name: "(null)"
  date: "(null)"
  desc: "(null)"

drmIoctl(3, (100, VERSION, 64, RW)) -> (
  version: 3.42.0
  name: "amdgpu"
  date: "20150101"
  desc: "AMD GPU"

drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_ACCEL_WORKING), 32, R)) -> 1
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_DEV_INFO), 32, R)) -> (
  device_id: 0x683f
  chip_rev: 0x1
  external_rev: 0x29
  pci_rev: 0x87
  family: 0x6e
  num_shader_engines: 0x1
  num_shader_arrays_per_engine: 0x2
  gpu_counter_freq: 0x6978
  max_engine_clock: 0xc3500
  max_memory_clock: 0x112a88
  cu_active_number: 0x8
  cu_ao_mask: 0x1e1e
  cu_bitmap: ((0x1e, 0x1e, 0, 0), (0, 0, 0, 0), (0, 0, 0, 0), (0, 0, 0, 0))
  enabled_rb_pipes_mask: 0xf
  num_rb_pipes: 0x4
  num_hw_gfx_contexts: 0x8
  ids_flags: 0
  virtual_address_offset: 0x200000
  virtual_address_max: 0xfffe00000
  virtual_address_alignment: 0x1000
  pte_fragment_size: 0x200000
  gart_page_size: 0x1000
  ce_ram_size: 0x8000
  vram_type: 0x5
  vram_bit_width: 0x80
  vce_harvest_config: 0
  gc_double_offchip_lds_buf: 0
  prim_buf_gpu_addr: 0
  pos_buf_gpu_addr: 0
  cntl_sb_buf_gpu_addr: 0
  param_buf_gpu_addr: 0
  prim_buf_size: 0
  pos_buf_size: 0
  cntl_sb_buf_size: 0
  param_buf_size: 0
  wave_front_size: 0
  num_shader_visible_vgprs: 0x100
  num_cu_per_sh: 0x5
  num_tcc_blocks: 0x4
  gs_vgt_table_depth: 0
  gs_prim_buffer_depth: 0
  max_gs_waves_per_vgt: 0x20
  cu_ao_bitmap: ((0x1e, 0x1e, 0, 0), (0, 0, 0, 0), (0, 0, 0, 0), (0, 0, 0, 0))
  high_va_offset: 0
  high_va_max: 0
  pa_sc_tile_steering_override: 0
  tcc_disabled_mask: 0
)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_READ_MMR_REG(dword_offset: 0x263d, count: 0x1, instance: 0xff00, flags: 0)), 32, R)) -> (0x1)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_READ_MMR_REG(dword_offset: 0xa0d4, count: 0x1, instance: 0xff00, flags: 0)), 32, R)) -> (0x1240)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_READ_MMR_REG(dword_offset: 0x263e, count: 0x1, instance: 0xffffffff, flags: 0)), 32, R)) -> (0x12010002)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_READ_MMR_REG(dword_offset: 0x2644, count: 0x20, instance: 0xffffffff, flags: 0)), 32, R)) -> (0x3a0112, 0x3a0912, 0x3a1112, 0x212912, 0x10a, 0x111912, 0x121112, 0x22112, 0x4, 0x108, 0x3a1110, 0x351110, 0x341910, 0x109, 0x361111, 0x351111, 0x341911, 0x342911, 0x10d, 0x342921, 0x34291d, 0x221111, 0x211111, 0x121111, 0x111911, 0x22111, 0x22111, 0x22111, 0x22111, 0x22111, 0x12911, 0)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_READ_MMR_REG(dword_offset: 0x9d8, count: 0x1, instance: 0xffffffff, flags: 0)), 32, R)) -> (0x262)
/Haiku/data/packages/libdrm/drm/builddir.x86_64/install/share/libdrm/amdgpu.ids version: 1.0.0
drmGetDevice2()
drmFreeDevice()
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_DEV_INFO), 32, R)) -> (
  device_id: 0x683f
  chip_rev: 0x1
  external_rev: 0x29
  pci_rev: 0x87
  family: 0x6e
  num_shader_engines: 0x1
  num_shader_arrays_per_engine: 0x2
  gpu_counter_freq: 0x6978
  max_engine_clock: 0xc3500
  max_memory_clock: 0x112a88
  cu_active_number: 0x8
  cu_ao_mask: 0x1e1e
  cu_bitmap: ((0x1e, 0x1e, 0, 0), (0, 0, 0, 0), (0, 0, 0, 0), (0, 0, 0, 0))
  enabled_rb_pipes_mask: 0xf
  num_rb_pipes: 0x4
  num_hw_gfx_contexts: 0x8
  ids_flags: 0
  virtual_address_offset: 0x200000
  virtual_address_max: 0xfffe00000
  virtual_address_alignment: 0x1000
  pte_fragment_size: 0x200000
  gart_page_size: 0x1000
  ce_ram_size: 0x8000
  vram_type: 0x5
  vram_bit_width: 0x80
  vce_harvest_config: 0
  gc_double_offchip_lds_buf: 0
  prim_buf_gpu_addr: 0
  pos_buf_gpu_addr: 0
  cntl_sb_buf_gpu_addr: 0
  param_buf_gpu_addr: 0
  prim_buf_size: 0
  pos_buf_size: 0
  cntl_sb_buf_size: 0
  param_buf_size: 0
  wave_front_size: 0
  num_shader_visible_vgprs: 0x100
  num_cu_per_sh: 0x5
  num_tcc_blocks: 0x4
  gs_vgt_table_depth: 0
  gs_prim_buffer_depth: 0
  max_gs_waves_per_vgt: 0x20
  cu_ao_bitmap: ((0x1e, 0x1e, 0, 0), (0, 0, 0, 0), (0, 0, 0, 0), (0, 0, 0, 0))
  high_va_offset: 0
  high_va_max: 0
  pa_sc_tile_steering_override: 0
  tcc_disabled_mask: 0
)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_HW_IP_INFO(type: DMA, ip_instance: 0)), 32, R)) -> (
  hw_ip_version_major: 0x1
  hw_ip_version_minor: 0
  capabilities_flags: 0
  ib_start_alignment: 0x100
  ib_size_alignment: 0x4
  available_rings: 3
)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_HW_IP_INFO(type: GFX, ip_instance: 0)), 32, R)) -> (
  hw_ip_version_major: 0x6
  hw_ip_version_minor: 0
  capabilities_flags: 0
  ib_start_alignment: 0x20
  ib_size_alignment: 0x20
  available_rings: 1
)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_HW_IP_INFO(type: COMPUTE, ip_instance: 0)), 32, R)) -> (
  hw_ip_version_major: 0x6
  hw_ip_version_minor: 0
  capabilities_flags: 0
  ib_start_alignment: 0x20
  ib_size_alignment: 0x20
  available_rings: 3
)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_HW_IP_INFO(type: UVD, ip_instance: 0)), 32, R)) -> (
  hw_ip_version_major: 0x3
  hw_ip_version_minor: 0x1
  capabilities_flags: 0
  ib_start_alignment: 0x40
  ib_size_alignment: 0x40
  available_rings: 1
)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_HW_IP_INFO(type: UVD_ENC, ip_instance: 0)), 32, R)) -> (
  hw_ip_version_major: 0x3
  hw_ip_version_minor: 0x1
  capabilities_flags: 0
  ib_start_alignment: 0x40
  ib_size_alignment: 0x40
  available_rings: 0
)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_HW_IP_INFO(type: VCN_DEC, ip_instance: 0)), 32, R)) -> (
  hw_ip_version_major: 0
  hw_ip_version_minor: 0
  capabilities_flags: 0
  ib_start_alignment: 0
  ib_size_alignment: 0
  available_rings: 0
)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_HW_IP_INFO(type: VCN_ENC, ip_instance: 0)), 32, R)) -> (
  hw_ip_version_major: 0
  hw_ip_version_minor: 0
  capabilities_flags: 0
  ib_start_alignment: 0
  ib_size_alignment: 0
  available_rings: 0
)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_HW_IP_INFO(type: VCN_JPEG, ip_instance: 0)), 32, R)) -> (
  hw_ip_version_major: 0
  hw_ip_version_minor: 0
  capabilities_flags: 0
  ib_start_alignment: 0
  ib_size_alignment: 0
  available_rings: 0
)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_FW_VERSION(type: GFX_ME, ip_instance: 0, index: 0)), 32, R)) -> (ver: 0x91, feature: 0x1d)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_FW_VERSION(type: GFX_PFP, ip_instance: 0, index: 0)), 32, R)) -> (ver: 0x54, feature: 0x1d)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_FW_VERSION(type: GFX_CE, ip_instance: 0, index: 0)), 32, R)) -> (ver: 0x3d, feature: 0x1d)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_FW_VERSION(type: UVD, ip_instance: 0, index: 0)), 32, R)) -> (ver: 0x40000d00, feature: 0)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_HW_IP_INFO(type: VCE, ip_instance: 0)), 32, R)) -> (
  hw_ip_version_major: 0
  hw_ip_version_minor: 0
  capabilities_flags: 0
  ib_start_alignment: 0
  ib_size_alignment: 0
  available_rings: 0
)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_FW_VERSION(type: VCE, ip_instance: 0, index: 0)), 32, R)) -> (ver: 0, feature: 0)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_GDS_CONFIG), 32, R)) -> (
  gds_gfx_partition_size: 0
  compute_partition_size: 0
  gds_total_size: 0
  gws_per_gfx_partition: 0
  gws_per_compute_partition: 0
  oa_per_gfx_partition: 0
  oa_per_compute_partition: 0
)
drmIoctl(4, (100, AMDGPU_INFO(query: AMDGPU_INFO_MEMORY), 32, R)) -> (
  vram: (
    total_heap_size: 0x80000000
    usable_heap_size: 0x7e380000
    heap_usage: 0x2664000
    max_allocation: 0x5eaa0000
  )
  cpu_accessible_vram: (
    total_heap_size: 0x10000000
    usable_heap_size: 0xf378000
    heap_usage: 0x1290000
    max_allocation: 0xb69a000
  )
  gtt: (
    total_heap_size: 0xc0000000
    usable_heap_size: 0xbfddd000
    heap_usage: 0xce1000
    max_allocation: 0x8fe65c00
  )
)
drmIoctl(3, (100, GET_CAP(SYNCOBJ), 16, RW)) -> 0
drmIoctl(3, (100, GET_CAP(SYNCOBJ_TIMELINE), 16, RW)) -> 0
WARNING: radv is not a conformant vulkan implementation, testing use only.
drmFreeDevices()
drmFreeDevice()
sdev->dd->winsys[0].name: null
WARNING: lavapipe is not a conformant vulkan implementation, testing use only.
drmIoctl(4, (100, AMDGPU_CTX(op: ALLOC, flags: 0, ctx_id: 0, priority: 0), 16, RW)) -> 1
drmIoctl(4, (100, AMDGPU_GEM_CREATE(bo_size: 0x1000, alignment: 0x8, domains: {GTT}, domain_flags: {CPU_ACCESS_REQUIRED, EXPLICIT_SYNC}), 32, RW)) -> 1
drmIoctl(4, (100, AMDGPU_GEM_VA(handle: 1, operation: MAP, flags: 0xe, va_address: 0x100000000, offset_in_bo: 0, map_size: 0x1000), 40, RW))
drmIoctl(4, (100, AMDGPU_GEM_MMAP(1), 8, RW)) -> 0
drmMmap(4, 0, 0x1000)
drmIoctl(4, (100, AMDGPU_CTX(op: ALLOC, flags: 0, ctx_id: 0, priority: 0), 16, RW)) -> 2
drmIoctl(4, (100, AMDGPU_GEM_CREATE(bo_size: 0x1000, alignment: 0x8, domains: {GTT}, domain_flags: {CPU_ACCESS_REQUIRED, EXPLICIT_SYNC}), 32, RW)) -> 2
drmIoctl(4, (100, AMDGPU_GEM_VA(handle: 2, operation: MAP, flags: 0xe, va_address: 0x100001000, offset_in_bo: 0, map_size: 0x1000), 40, RW))
drmIoctl(4, (100, AMDGPU_GEM_MMAP(2), 8, RW)) -> 0
drmMmap(4, 0, 0x1000)
drmIoctl(4, (100, AMDGPU_GEM_CREATE(bo_size: 0x40000, alignment: 0x100, domains: {VRAM}, domain_flags: {EXPLICIT_SYNC}), 32, RW)) -> 3
drmIoctl(4, (100, AMDGPU_GEM_VA(handle: 3, operation: MAP, flags: 0xe, va_address: 0x100002000, offset_in_bo: 0, map_size: 0x40000), 40, RW))
drmIoctl(4, (100, AMDGPU_GEM_MMAP(3), 8, RW)) -> 0
drmMmap(4, 0, 0x40000)
swapchain::create_image((1280, 720))
drmIoctl(4, (100, AMDGPU_GEM_CREATE(bo_size: 0x3c3000, alignment: 0x20000, domains: {VRAM}, domain_flags: {NO_CPU_ACCESS, EXPLICIT_SYNC}), 32, RW)) -> 4
drmIoctl(4, (100, AMDGPU_GEM_VA(handle: 4, operation: MAP, flags: 0xe, va_address: 0x100200000, offset_in_bo: 0, map_size: 0x3c3000), 40, RW))
swapchain::create_image((1280, 720))
drmIoctl(4, (100, AMDGPU_GEM_CREATE(bo_size: 0x3c3000, alignment: 0x20000, domains: {VRAM}, domain_flags: {NO_CPU_ACCESS, EXPLICIT_SYNC}), 32, RW)) -> 5
drmIoctl(4, (100, AMDGPU_GEM_VA(handle: 5, operation: MAP, flags: 0xe, va_address: 0x100600000, offset_in_bo: 0, map_size: 0x3c3000), 40, RW))
drmIoctl(4, (100, AMDGPU_GEM_CREATE(bo_size: 0x4c3000, alignment: 0x20000, domains: {VRAM}, domain_flags: {NO_CPU_ACCESS, EXPLICIT_SYNC}), 32, RW)) -> 6
drmIoctl(4, (100, AMDGPU_GEM_VA(handle: 6, operation: MAP, flags: 0xe, va_address: 0x100a00000, offset_in_bo: 0, map_size: 0x4c3000), 40, RW))
drmIoctl(4, (100, AMDGPU_GEM_CREATE(bo_size: 0x40000, alignment: 0x20000, domains: {VRAM}, domain_flags: {NO_CPU_ACCESS, EXPLICIT_SYNC}), 32, RW)) -> 7
drmIoctl(4, (100, AMDGPU_GEM_VA(handle: 7, operation: MAP, flags: 0xe, va_address: 0x100060000, offset_in_bo: 0, map_size: 0x40000), 40, RW))
drmIoctl(4, (100, AMDGPU_GEM_CREATE(bo_size: 0x40000, alignment: 0x20000, domains: {GTT}, domain_flags: {CPU_ACCESS_REQUIRED, CPU_GTT_USWC, EXPLICIT_SYNC}), 32, RW)) -> 8
drmIoctl(4, (100, AMDGPU_GEM_VA(handle: 8, operation: MAP, flags: 0xe, va_address: 0x1000a0000, offset_in_bo: 0, map_size: 0x40000), 40, RW))
drmIoctl(4, (100, AMDGPU_GEM_MMAP(8), 8, RW)) -> 0
drmMmap(4, 0, 0x40000)
drmMunmap(0xd6069a6000, 0x40000)
drmIoctl(4, (100, AMDGPU_GEM_CREATE(bo_size: 0x4000, alignment: 0x1000, domains: {GTT}, domain_flags: {CPU_ACCESS_REQUIRED, CPU_GTT_USWC, EXPLICIT_SYNC}), 32, RW)) -> 9
drmIoctl(4, (100, AMDGPU_GEM_VA(handle: 9, operation: MAP, flags: 0xe, va_address: 0x200000, offset_in_bo: 0, map_size: 0x4000), 40, RW))
drmIoctl(4, (100, AMDGPU_GEM_MMAP(9), 8, RW)) -> 0
drmMmap(4, 0, 0x4000)
drmIoctl(4, (100, AMDGPU_GEM_CREATE(bo_size: 0x7a0, alignment: 0x1000, domains: {GTT}, domain_flags: {CPU_ACCESS_REQUIRED, EXPLICIT_SYNC}), 32, RW)) -> 10
drmIoctl(4, (100, AMDGPU_GEM_VA(handle: 10, operation: MAP, flags: 0xa, va_address: 0x100042000, offset_in_bo: 0, map_size: 0x1000), 40, RW))
drmIoctl(4, (100, AMDGPU_GEM_MMAP(10), 8, RW)) -> 0
drmMmap(4, 0, 0x7a0)
drmIoctl(4, (100, AMDGPU_CS(ctx_id: 1, bo_list_handle: 0, num_chunks: 3, chunks: (
  (id: IB(flags: 0, va_start: 0x100042000, ib_bytes: 1952, ip_type: 0, ip_instance: 0, ring: 0), length: 8, data: 0x10f17703dd60)
  (id: FENCE(handle: 1, offset: 0), length: 2, data: 0x10f17703dd80)
  (id: BO_HANDLES(operation: -1, list_handle: -1, bo_number: 5, bo_info_size: 8, bo_info_ptr: 0x10f176f25500(10, 9, 8, 3, 7)), length: 6, data: 0x7f8ea56a5780)
), 24, RW))
drmIoctl(4, (100, AMDGPU_GEM_VA(handle: 10, operation: UNMAP, flags: 0xe, va_address: 0x100042000, offset_in_bo: 0, map_size: 0x1000), 40, RW))
drmMunmap(0xd606cd7000, 0x7a0)
drmIoctl(4, (100, GEM_CLOSE(10), 8, R))
drmIoctl(4, (100, AMDGPU_WAIT_CS, 32, RW))
Fatal : VkResult is "TIMEOUT" in ../base/VulkanDevice.cpp at line 527
gears: ../base/VulkanDevice.cpp:527:void vks::VulkanDevice::flushCommandBuffer(VkCommandBuffer, VkQueue, VkCommandPool, bool): res == VK_SUCCESS
Kill Thread