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(* Extending the LEDs example with a couple of more advanced features. | |
1) Use interfaces to define the input and output ports of the circuit | |
and then use the generic functors in HardCaml.Interface to avoid | |
needing to explicitly define port names with the `input` and `output` | |
functions. | |
2) Implement the pictorial statemachine from the diagram in the style | |
we would use if writing in VHDL or Verilog | |
*) | |
open HardCaml.Signal.Comb | |
open HardCaml.Signal.Seq | |
module I = interface | |
key{|2|}[1] | |
end | |
module O = interface | |
leds[1] | |
end | |
let leds i = | |
let open HardCaml.Signal.Guarded in | |
let is,sm,next = | |
HardCaml.Signal.Statemachine.statemachine ~encoding:`binary r_none empty [ `off; `on ] | |
in | |
let in0 = ~: (i.I.key.(0)) in | |
let in1 = ~: (i.I.key.(1)) in | |
compile [ | |
sm [ | |
`off, [ | |
g_when in0 [ next `on ] | |
]; | |
`on, [ | |
g_when in1 [ next `off ] | |
]; | |
] | |
]; | |
O.({ leds = is `on }) | |
let () = | |
let module Gen = HardCaml.Interface.Circ(I)(O) in | |
let circuit = Gen.make "leds" leds in | |
HardCaml.Rtl.Verilog.write print_string circuit |
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