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DEF MUX21
# 2-to-1 multiplexer: if S=0, Z=I0. If S=1, Z=I1.
PORT IN I0
PORT IN I1
PORT IN S
PORT OUT Z
NET CI0
NET CI1
INST NAND1 NAND I1 S CI1
NET NS
INST NOT1 NOT S NS
INST NAND2 NAND I0 NS CI0
INST NAND3 NAND CI0 CI1 Z
ENDDEF
DEF DEMUX12
# 2-to-1 demultiplexer: one input to two inputs.
PORT IN A
PORT IN S
PORT OUT Z0
PORT OUT Z1
NET NZ1
INST AND1 NAND A S NZ1
INST NOT2 NOT NZ1 Z1
INST AND2 AND A NZ1 Z0
ENDDEF
DEF MUX41
# 4-to-1 multiplexer.
# Basically a MUX21 of two MUX21s but with some additional optimization.
PORT IN I0
PORT IN I1
PORT IN I2
PORT IN I3
PORT IN S<1:0>
PORT OUT Z
NET MXLO
NET MXHI
NET NS0
INST NOT0 NOT S<0> NS0
NET CI0
NET CI1
NET CI2
NET CI3
INST NAND4 NAND I0 NS0 CI0
INST NAND5 NAND I2 NS0 CI2
INST NAND6 NAND I1 S<0> CI1
INST NAND7 NAND I3 S<0> CI3
INST NAND8 NAND CI0 CI1 MXLO
INST NAND9 NAND CI2 CI3 MXHI
INST MUX1 MUX21 MXLO MXHI S<1> Z
ENDDEF
DEF DEMUX14
PORT IN A
PORT IN S<1:0>
PORT OUT Z0
PORT OUT Z1
PORT OUT Z2
PORT OUT Z3
NET HI
NET LO
INST DEMUX1 DEMUX12 A S<1> LO HI
INST DEMUX2 DEMUX12 HI S<0> Z2 Z3
INST DEMUX3 DEMUX12 LO S<0> Z0 Z1
ENDDEF
# -----------------------------------
# 8-bit logic. Fun as heck of course.
DEF NANDx81
PORT IN A<7:0>
PORT IN B
PORT OUT Z<7:0>
INST NAND0 NAND A<0> B Z<0>
INST NAND1 NAND A<1> B Z<1>
INST NAND2 NAND A<2> B Z<2>
INST NAND3 NAND A<3> B Z<3>
INST NAND4 NAND A<4> B Z<4>
INST NAND5 NAND A<5> B Z<5>
INST NAND6 NAND A<6> B Z<6>
INST NAND7 NAND A<7> B Z<7>
ENDDEF
DEF NANDx88
PORT IN A<7:0>
PORT IN B<7:0>
PORT OUT Z<7:0>
INST NAND0 NAND A<0> B<0> Z<0>
INST NAND1 NAND A<1> B<1> Z<1>
INST NAND2 NAND A<2> B<2> Z<2>
INST NAND3 NAND A<3> B<3> Z<3>
INST NAND4 NAND A<4> B<4> Z<4>
INST NAND5 NAND A<5> B<5> Z<5>
INST NAND6 NAND A<6> B<6> Z<6>
INST NAND7 NAND A<7> B<7> Z<7>
ENDDEF
DEF NOTx8
PORT IN A<7:0>
PORT OUT Z<7:0>
INST NAND0 NANDx88 A<7:0> A<7:0> Z<7:0>
ENDDEF
DEF ANDx88
PORT IN A<7:0>
PORT IN B<7:0>
PORT OUT Z<7:0>
NET N<7:0>
INST NAND0 NANDx88 A<7:0> B<7:0> N<7:0>
INST NOT0 NOTx8 N<7:0> Z<7:0>
ENDDEF
DEF ANDx81
PORT IN A<7:0>
PORT IN B
PORT OUT Z<7:0>
NET N<7:0>
INST NAND0 NANDx81 A<7:0> B N<7:0>
INST NOT0 NOTx8 N<7:0> Z<7:0>
ENDDEF
DEF MUX21x8
# 2-to-1 multiplexer of 8-bit values: if S=0, Z=I0. If S=1, Z=I1.
PORT IN I0<7:0>
PORT IN I1<7:0>
PORT IN S
PORT OUT Z<7:0>
NET CI0<7:0>
NET CI1<7:0>
INST NAND1 NANDx81 I1<7:0> S CI1<7:0>
NET NS
INST NOT1 NOT S NS
INST NAND2 NANDx81 I0<7:0> NS CI0<7:0>
INST NAND3 NANDx88 CI0<7:0> CI1<7:0> Z<7:0>
ENDDEF
DEF DEMUX12x8
# 2-to-1 demultiplexer for 8-bit values: one input to two inputs.
PORT IN A<7:0>
PORT IN S
PORT OUT Z0<7:0>
PORT OUT Z1<7:0>
NET NZ1<7:0>
INST AND1 NANDx81 A<7:0> S NZ1<7:0>
INST NOT2 NOTx8 NZ1<7:0> Z1<7:0>
INST AND2 ANDx88 A<7:0> NZ1<7:0> Z0<7:0>
ENDDEF
DEF MUX41x8
PORT IN I0<7:0>
PORT IN I1<7:0>
PORT IN I2<7:0>
PORT IN I3<7:0>
PORT IN S<1:0>
PORT OUT Z<7:0>
NET MXLO<7:0>
NET MXHI<7:0>
NET NS0
INST NOT0 NOT S<0> NS0
NET CI0<7:0>
NET CI1<7:0>
NET CI2<7:0>
NET CI3<7:0>
INST NAND4 NANDx81 I0<7:0> NS0 CI0<7:0>
INST NAND5 NANDx81 I2<7:0> NS0 CI2<7:0>
INST NAND6 NANDx81 I1<7:0> S<0> CI1<7:0>
INST NAND7 NANDx81 I3<7:0> S<0> CI3<7:0>
INST NAND8 NANDx88 CI0<7:0> CI1<7:0> MXLO<7:0>
INST NAND9 NANDx88 CI2<7:0> CI3<7:0> MXHI<7:0>
INST MUX1 MUX21x8 MXLO<7:0> MXHI<7:0> S<1> Z<7:0>
ENDDEF
DEF DEMUX14x8
PORT IN A<7:0>
PORT IN S<1:0>
PORT OUT Z0<7:0>
PORT OUT Z1<7:0>
PORT OUT Z2<7:0>
PORT OUT Z3<7:0>
NET HI<7:0>
NET LO<7:0>
INST DEMUX1 DEMUX12x8 A<7:0> S<1> LO<7:0> HI<7:0>
INST DEMUX2 DEMUX12x8 HI<7:0> S<0> Z2<7:0> Z3<7:0>
INST DEMUX3 DEMUX12x8 LO<7:0> S<0> Z0<7:0> Z1<7:0>
ENDDEF
DEF MUX81x8
# 8-to-1 multiplexer of 8-bit inputs.
# like wat
PORT IN I0<7:0>
PORT IN I1<7:0>
PORT IN I2<7:0>
PORT IN I3<7:0>
PORT IN I4<7:0>
PORT IN I5<7:0>
PORT IN I6<7:0>
PORT IN I7<7:0>
PORT IN S<2:0>
PORT OUT Z<7:0>
NET MXLL<7:0>
NET MXLH<7:0>
NET MXHL<7:0>
NET MXHH<7:0>
NET CI0<7:0>
NET CI1<7:0>
NET CI2<7:0>
NET CI3<7:0>
NET CI4<7:0>
NET CI5<7:0>
NET CI6<7:0>
NET CI7<7:0>
NET NS0
INST NOT0 NOT S<0> NS0
INST NAND0 NANDx81 I0<7:0> NS0 CI0<7:0>
INST NAND1 NANDx81 I1<7:0> S<0> CI1<7:0>
INST NAND2 NANDx81 I2<7:0> NS0 CI2<7:0>
INST NAND3 NANDx81 I3<7:0> S<0> CI3<7:0>
INST NAND4 NANDx81 I4<7:0> NS0 CI4<7:0>
INST NAND5 NANDx81 I5<7:0> S<0> CI5<7:0>
INST NAND6 NANDx81 I6<7:0> NS0 CI6<7:0>
INST NAND7 NANDx81 I7<7:0> S<0> CI7<7:0>
INST NAND8 NANDx88 CI0<7:0> CI1<7:0> MXLL<7:0>
INST NAND9 NANDx88 CI2<7:0> CI3<7:0> MXLH<7:0>
INST NAND10 NANDx88 CI4<7:0> CI5<7:0> MXHL<7:0>
INST NAND11 NANDx88 CI6<7:0> CI7<7:0> MXHH<7:0>
INST MUX4 MUX41x8 MXLL<7:0> MXLH<7:0> MXHL<7:0> MXHH<7:0> S<2:1> Z<7:0>
ENDDEF
DEF DEMUX18x8
PORT IN A<7:0>
PORT IN S<2:0>
PORT OUT Z0<7:0>
PORT OUT Z1<7:0>
PORT OUT Z2<7:0>
PORT OUT Z3<7:0>
PORT OUT Z4<7:0>
PORT OUT Z5<7:0>
PORT OUT Z6<7:0>
PORT OUT Z7<7:0>
NET HI<7:0>
NET LO<7:0>
INST DEMUX1 DEMUX12x8 A<7:0> S<2> LO<7:0> HI<7:0>
INST DEMUX2 DEMUX14x8 LO<7:0> S<1:0> Z0<7:0> Z1<7:0> Z2<7:0> Z3<7:0>
INST DEMUX3 DEMUX14x8 HI<7:0> S<1:0> Z4<7:0> Z5<7:0> Z6<7:0> Z7<7:0>
ENDDEF
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