Skip to content

Instantly share code, notes, and snippets.

/gist:357732

Created April 6, 2010 15:40
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
Star You must be signed in to star a gist
Save anonymous/357732 to your computer and use it in GitHub Desktop.
Download ZIP
Raw
gistfile1.diff
From 3c4568e2d9a67e2b5f8a637eb029269cb0248b9d Mon Sep 17 00:00:00 2001
From: Ferar Achkar <ferarachkar@gmail.com>
Date: Mon, 5 Apr 2010 18:01:57 -0400
Subject: [PATCH] 1. added -lncurses to scripts/kconfig/Makefile so I can run the make menuconfig
2. added the s3c2450 to arch/arm/Kconfig arch/arm/Makefile
---
arch/arm/Kconfig | 3 ++-
arch/arm/Makefile | 2 +-
scripts/kconfig/Makefile | 2 +-
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1c4119c..c19521e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -602,7 +602,7 @@ config ARCH_SA1100
Support for StrongARM 11x0 based boards.
config ARCH_S3C2410
- bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
+ bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443, S3C2450"
select GENERIC_GPIO
select ARCH_HAS_CPUFREQ
select HAVE_CLK
@@ -759,6 +759,7 @@ source "arch/arm/mach-s3c2412/Kconfig"
source "arch/arm/mach-s3c2440/Kconfig"
source "arch/arm/mach-s3c2442/Kconfig"
source "arch/arm/mach-s3c2443/Kconfig"
+source "arch/arm/mach-s3c2450/Kconfig"
endif
if ARCH_S3C64XX
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a73caaf..58af35b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -157,7 +157,7 @@ machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_REALVIEW) := realview
machine-$(CONFIG_ARCH_RPC) := rpc
-machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
+machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 s3c2450
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410
machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100
diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
index 80599e3..1cf7447 100644
--- a/scripts/kconfig/Makefile
+++ b/scripts/kconfig/Makefile
@@ -128,7 +128,7 @@ check-lxdialog := $(srctree)/$(src)/lxdialog/check-lxdialog.sh
# Use recursively expanded variables so we do not call gcc unless
# we really need to do so. (Do not call gcc as part of make mrproper)
HOST_EXTRACFLAGS = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ccflags)
-HOST_LOADLIBES = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC))
+HOST_LOADLIBES = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC)) -lncurses
HOST_EXTRACFLAGS += -DLOCALE
--
1.5.6.1
From 2a0103c2d01038b5e190639bcac3f23953edfd54 Mon Sep 17 00:00:00 2001
From: Ferar Achkar <ferarachkar@gmail.com>
Date: Mon, 5 Apr 2010 18:32:18 -0400
Subject: [PATCH] 1. porting the so far s3c2450 (secnd attempt)
---
arch/arm/mach-s3c2410/include/mach/hsmmc.h | 45 ++
arch/arm/mach-s3c2450/Kconfig | 42 +
arch/arm/mach-s3c2450/Makefile | 21 +
arch/arm/mach-s3c2450/clock.c | 1039 ++++++++++++++++++++++++++
arch/arm/mach-s3c2450/dma.c | 195 +++++
arch/arm/mach-s3c2450/irq.c | 310 ++++++++
arch/arm/mach-s3c2450/mach-smdk2450.c | 418 +++++++++++
arch/arm/mach-s3c2450/maino.c | 49 ++
arch/arm/mach-s3c2450/pm.c | 158 ++++
arch/arm/mach-s3c2450/s3c2450.c | 207 +++++
arch/arm/plat-s3c24xx/include/plat/s3c2450.h | 32 +
11 files changed, 2516 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-s3c2410/include/mach/hsmmc.h
create mode 100644 arch/arm/mach-s3c2450/Kconfig
create mode 100644 arch/arm/mach-s3c2450/Makefile
create mode 100644 arch/arm/mach-s3c2450/clock.c
create mode 100644 arch/arm/mach-s3c2450/dma.c
create mode 100644 arch/arm/mach-s3c2450/irq.c
create mode 100644 arch/arm/mach-s3c2450/mach-smdk2450.c
create mode 100644 arch/arm/mach-s3c2450/maino.c
create mode 100644 arch/arm/mach-s3c2450/pm.c
create mode 100644 arch/arm/mach-s3c2450/s3c2450.c
create mode 100644 arch/arm/plat-s3c24xx/include/plat/s3c2450.h
diff --git a/arch/arm/mach-s3c2410/include/mach/hsmmc.h b/arch/arm/mach-s3c2410/include/mach/hsmmc.h
new file mode 100644
index 0000000..9a2d9be
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/hsmmc.h
@@ -0,0 +1,45 @@
+#ifndef __ASM_S3C_HSMMC_H
+#define __ASM_S3C_HSMMC_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/mmc/host.h>
+
+#if defined(CONFIG_CPU_S3C6410)
+#define NUM_OF_HSMMC_CLKSOURCES 2
+#else
+#define NUM_OF_HSMMC_CLKSOURCES 3
+#endif
+
+#define SPEED_NORMAL 0
+#define SPEED_HIGH 1
+
+struct s3c_hsmmc_fd_cfg {
+ ulong ctrl2;
+ ulong ctrl3[2]; /* 0: low speed, 1: high speed */
+ ulong ctrl4;
+};
+
+struct s3c_hsmmc_cfg {
+ u32 hwport; /* hardware port number */
+ u32 enabled; /* if port is used, set 1 */
+ u32 host_caps; /* host capabilities */
+ u32 bus_width; /* bus width */
+
+ void *base; /* base address of host */
+
+ u8 highspeed; /* ENHIGHSPD bit configuration */
+
+ /* feedback delay control configuration (0: mmc, 1: sd) */
+ struct s3c_hsmmc_fd_cfg fd_ctrl[2];
+
+ /* HS-MMC has 3 clock source */
+ char *clk_name[NUM_OF_HSMMC_CLKSOURCES];
+};
+
+extern void hsmmc_set_gpio(uint channel, uint width);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_S3C_HSMMC_H */
+
diff --git a/arch/arm/mach-s3c2450/Kconfig b/arch/arm/mach-s3c2450/Kconfig
new file mode 100644
index 0000000..c823c77
--- /dev/null
+++ b/arch/arm/mach-s3c2450/Kconfig
@@ -0,0 +1,42 @@
+# arch/arm/mach-s3c2450/Kconfig
+#
+# Copyright 2007 Simtec Electronics
+#
+# Licensed under GPLv2
+
+config CPU_S3C2450
+ bool
+ depends on ARCH_S3C2410
+ select S3C2450_PM if PM
+ select S3C2450_DMA if S3C2410_DMA
+ help
+ Support for the S3C2450 SoC from the S3C24XX line
+
+config S3C2450_DMA
+ bool
+ depends on CPU_S3C2450
+ help
+ Internal config node for S3C2450 DMA support
+
+config S3C2450_PM
+ bool
+ help
+ Internal config node to apply S3C2450 power management
+
+
+menu "S3C2450 Machines"
+
+config MACH_SMDK2450
+ bool "SMDK2450"
+ select CPU_S3C2450
+ select MACH_SMDK
+ help
+ Say Y here if you are using an SMDK2450
+
+config MACH_FPGA2450
+ bool "FPGA2450"
+ depends on MACH_SMDK2450
+ help
+ Say Y here if you are using an FPGA2450
+
+endmenu
diff --git a/arch/arm/mach-s3c2450/Makefile b/arch/arm/mach-s3c2450/Makefile
new file mode 100644
index 0000000..4c8267d
--- /dev/null
+++ b/arch/arm/mach-s3c2450/Makefile
@@ -0,0 +1,21 @@
+# arch/arm/mach-s3c2450/Makefile
+#
+# Copyright 2007 Simtec Electronics
+#
+# Licensed under GPLv2
+
+obj-y :=
+obj-m :=
+obj-n :=
+obj- :=
+
+obj-$(CONFIG_CPU_S3C2450) += s3c2450.o
+obj-$(CONFIG_CPU_S3C2450) += irq.o
+obj-$(CONFIG_CPU_S3C2450) += clock.o
+
+obj-$(CONFIG_S3C2450_DMA) += dma.o
+obj-$(CONFIG_S3C2450_PM) += pm.o
+
+# Machine support
+obj-$(CONFIG_MACH_SMDK2450) += mach-smdk2450.o
+# obj-$(CONFIG_MACH_SMDK2450) += maino.o
\ No newline at end of file
diff --git a/arch/arm/mach-s3c2450/clock.c b/arch/arm/mach-s3c2450/clock.c
new file mode 100644
index 0000000..9cc33b7
--- /dev/null
+++ b/arch/arm/mach-s3c2450/clock.c
@@ -0,0 +1,1039 @@
+/* linux/arch/arm/mach-s3c2450/clock.c
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * Ryu Euiyoul <ryu.real@gmail.com>
+ *
+ * S3C2450 Clock control support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-s3c2450-clock.h>
+
+#include <plat/s3c2450.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+/* We currently have to assume that the system is running
+ * from the XTPll input, and that all ***REFCLKs are being
+ * fed from it, as we cannot read the state of OM[4] from
+ * software.
+ *
+ * It would be possible for each board initialisation to
+ * set the correct muxing at initialisation
+*/
+
+static int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
+{
+ unsigned int clocks = clk->ctrlbit;
+ unsigned long clkcon;
+
+ clkcon = __raw_readl(S3C2443_HCLKCON);
+
+ if (enable)
+ clkcon |= clocks;
+ else
+ clkcon &= ~clocks;
+
+ __raw_writel(clkcon, S3C2443_HCLKCON);
+
+ return 0;
+}
+
+static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
+{
+ unsigned int clocks = clk->ctrlbit;
+ unsigned long clkcon;
+
+ clkcon = __raw_readl(S3C2443_PCLKCON);
+
+ if (enable)
+ clkcon |= clocks;
+ else
+ clkcon &= ~clocks;
+
+ __raw_writel(clkcon, S3C2443_HCLKCON);
+
+ return 0;
+}
+
+static int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
+{
+ unsigned int clocks = clk->ctrlbit;
+ unsigned long clkcon;
+
+ clkcon = __raw_readl(S3C2443_SCLKCON);
+
+ if (enable)
+ clkcon |= clocks;
+ else
+ clkcon &= ~clocks;
+
+ __raw_writel(clkcon, S3C2443_SCLKCON);
+
+ return 0;
+}
+
+static unsigned long s3c2443_roundrate_clksrc(struct clk *clk,
+ unsigned long rate,
+ unsigned int max)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ int div;
+
+ if (rate > parent_rate)
+ return parent_rate;
+
+ /* note, we remove the +/- 1 calculations as they cancel out */
+
+ div = (rate / parent_rate);
+
+ if (div < 1)
+ div = 1;
+ else if (div > max)
+ div = max;
+
+ return parent_rate / div;
+}
+
+static unsigned long s3c2443_roundrate_clksrc4(struct clk *clk,
+ unsigned long rate)
+{
+ return s3c2443_roundrate_clksrc(clk, rate, 4);
+}
+
+static unsigned long s3c2443_roundrate_clksrc16(struct clk *clk,
+ unsigned long rate)
+{
+ return s3c2443_roundrate_clksrc(clk, rate, 16);
+}
+
+static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk,
+ unsigned long rate)
+{
+ return s3c2443_roundrate_clksrc(clk, rate, 256);
+}
+
+/* clock selections */
+
+
+static struct clk clk_mpllref = {
+ .name = "mpllref",
+ .parent = &clk_xtal,
+ .id = -1,
+};
+
+#if 0
+static struct clk clk_mpll = {
+ .name = "mpll",
+ .parent = &clk_mpllref,
+ .id = -1,
+};
+#endif
+
+static struct clk clk_epllref;
+
+struct clk clk_epll = {
+ .name = "epll",
+ .parent = &clk_epllref,
+ .id = -1,
+};
+
+static struct clk clk_i2s_ext = {
+ .name = "i2s-ext",
+ .id = -1,
+};
+
+static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent)
+{
+ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
+
+ clksrc &= ~S3C2443_CLKSRC_EPLLREF_MASK;
+
+ if (parent == &clk_xtal)
+ clksrc |= S3C2443_CLKSRC_EPLLREF_XTAL;
+ else if (parent == &clk_ext)
+ clksrc |= S3C2443_CLKSRC_EPLLREF_EXTCLK;
+ else if (parent != &clk_mpllref)
+ return -EINVAL;
+
+ __raw_writel(clksrc, S3C2443_CLKSRC);
+ clk->parent = parent;
+
+ return 0;
+}
+
+static struct clk clk_epllref = {
+ .name = "epllref",
+ .id = -1,
+ .set_parent = s3c2443_setparent_epllref,
+};
+
+static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long div = __raw_readl(S3C2443_CLKDIV0);
+
+ div &= S3C2443_CLKDIV0_EXTDIV_MASK;
+ div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
+
+ return parent_rate / (div + 1);
+}
+
+static struct clk clk_mdivclk = {
+ .name = "mdivclk",
+ .parent = &clk_mpllref,
+ .id = -1,
+ .get_rate = s3c2443_getrate_mdivclk,
+};
+
+
+static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent)
+{
+ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
+
+ clksrc &= ~(S3C2443_CLKSRC_MSYSCLK_MPLL |
+ S3C2443_CLKSRC_EXTCLK_DIV);
+
+ if (parent == &clk_mpll)
+ clksrc |= S3C2443_CLKSRC_MSYSCLK_MPLL;
+ else if (parent == &clk_mdivclk)
+ clksrc |= S3C2443_CLKSRC_EXTCLK_DIV;
+ else if (parent != &clk_mpllref)
+ return -EINVAL;
+
+ __raw_writel(clksrc, S3C2443_CLKSRC);
+ clk->parent = parent;
+
+ return 0;
+}
+
+static struct clk clk_msysclk = {
+ .name = "msysclk",
+ .parent = &clk_xtal,
+ .id = -1,
+ .set_parent = s3c2443_setparent_msysclk,
+};
+
+
+/* esysclk
+ *
+ * this is sourced from either the EPLL or the EPLLref clock
+*/
+
+static int s3c2443_setparent_esysclk(struct clk *clk, struct clk *parent)
+{
+ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
+
+ if (parent == &clk_epll)
+ clksrc |= S3C2443_CLKSRC_ESYSCLK_EPLL;
+ else if (parent == &clk_epllref)
+ clksrc &= ~S3C2443_CLKSRC_ESYSCLK_EPLL;
+ else
+ return -EINVAL;
+
+ __raw_writel(clksrc, S3C2443_CLKSRC);
+ clk->parent = parent;
+
+ return 0;
+}
+
+static struct clk clk_esysclk = {
+ .name = "esysclk",
+ .parent = &clk_epll,
+ .id = -1,
+ .set_parent = s3c2443_setparent_esysclk,
+};
+
+/* uartclk
+ *
+ * UART baud-rate clock sourced from esysclk via a divisor
+*/
+
+static unsigned long s3c2443_getrate_uart(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
+
+ div &= S3C2443_CLKDIV1_UARTDIV_MASK;
+ div >>= S3C2443_CLKDIV1_UARTDIV_SHIFT;
+
+ return parent_rate / (div + 1);
+}
+
+
+static int s3c2443_setrate_uart(struct clk *clk, unsigned long rate)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
+
+ rate = s3c2443_roundrate_clksrc16(clk, rate);
+ rate = parent_rate / rate;
+
+ clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK;
+ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT;
+
+ __raw_writel(clkdivn, S3C2443_CLKDIV1);
+ return 0;
+}
+
+static struct clk clk_uart = {
+ .name = "uartclk",
+ .id = -1,
+ .parent = &clk_esysclk,
+ .get_rate = s3c2443_getrate_uart,
+ .set_rate = s3c2443_setrate_uart,
+ .round_rate = s3c2443_roundrate_clksrc16,
+};
+
+/* hsspi
+ *
+ * high-speed spi clock, sourced from esysclk
+*/
+
+static unsigned long s3c2443_getrate_hsspi(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
+
+ div &= S3C2443_CLKDIV1_HSSPIDIV_MASK;
+ div >>= S3C2443_CLKDIV1_HSSPIDIV_SHIFT;
+
+ return parent_rate / (div + 1);
+}
+
+
+static int s3c2443_setrate_hsspi(struct clk *clk, unsigned long rate)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
+
+ rate = s3c2443_roundrate_clksrc4(clk, rate);
+ rate = parent_rate / rate;
+
+ clkdivn &= ~S3C2443_CLKDIV1_HSSPIDIV_MASK;
+ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSSPIDIV_SHIFT;
+
+ __raw_writel(clkdivn, S3C2443_CLKDIV1);
+ return 0;
+}
+
+static struct clk clk_hsspi = {
+ .name = "hsspi",
+ .id = -1,
+ .parent = &clk_esysclk,
+ .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
+ .enable = s3c2443_clkcon_enable_s,
+ .get_rate = s3c2443_getrate_hsspi,
+ .set_rate = s3c2443_setrate_hsspi,
+ .round_rate = s3c2443_roundrate_clksrc4,
+};
+
+/* usbhost
+ *
+ * usb host bus-clock, usually 48MHz to provide USB bus clock timing
+*/
+
+static unsigned long s3c2443_getrate_usbhost(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
+
+ div &= S3C2443_CLKDIV1_USBHOSTDIV_MASK;
+ div >>= S3C2443_CLKDIV1_USBHOSTDIV_SHIFT;
+
+ return parent_rate / (div + 1);
+}
+
+static int s3c2443_setrate_usbhost(struct clk *clk, unsigned long rate)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
+
+ rate = s3c2443_roundrate_clksrc4(clk, rate);
+ rate = parent_rate / rate;
+
+ clkdivn &= ~S3C2443_CLKDIV1_USBHOSTDIV_MASK;
+ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_USBHOSTDIV_SHIFT;
+
+ __raw_writel(clkdivn, S3C2443_CLKDIV1);
+ return 0;
+}
+
+struct clk clk_usb_bus_host = {
+ .name = "usb-bus-host-parent",
+ .id = -1,
+ .parent = &clk_esysclk,
+ .ctrlbit = S3C2443_SCLKCON_USBHOST,
+ .enable = s3c2443_clkcon_enable_s,
+ .get_rate = s3c2443_getrate_usbhost,
+ .set_rate = s3c2443_setrate_usbhost,
+ .round_rate = s3c2443_roundrate_clksrc4,
+};
+
+/* clk_hsmcc_div
+ *
+ * this clock is sourced from epll, and is fed through a divider,
+ * to a mux controlled by sclkcon where either it or a extclk can
+ * be fed to the hsmmc block
+*/
+
+static unsigned long s3c2443_getrate_hsmmc_div(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
+
+ div &= S3C2443_CLKDIV1_HSMMCDIV_MASK;
+ div >>= S3C2443_CLKDIV1_HSMMCDIV_SHIFT;
+
+ return parent_rate / (div + 1);
+}
+
+static int s3c2443_setrate_hsmmc_div(struct clk *clk, unsigned long rate)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
+
+ rate = s3c2443_roundrate_clksrc4(clk, rate);
+ rate = parent_rate / rate;
+
+ clkdivn &= ~S3C2443_CLKDIV1_HSMMCDIV_MASK;
+ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSMMCDIV_SHIFT;
+
+ __raw_writel(clkdivn, S3C2443_CLKDIV1);
+ return 0;
+}
+
+static struct clk clk_hsmmc_div = {
+ .name = "hsmmc-div",
+ .id = -1,
+ .parent = &clk_esysclk,
+ .get_rate = s3c2443_getrate_hsmmc_div,
+ .set_rate = s3c2443_setrate_hsmmc_div,
+ .round_rate = s3c2443_roundrate_clksrc4,
+};
+
+static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
+{
+ unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
+
+ clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
+ S3C2443_SCLKCON_HSMMCCLK_EPLL);
+
+ if (parent == &clk_epll)
+ clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
+ else if (parent == &clk_ext)
+ clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
+ else
+ return -EINVAL;
+
+ if (clk->usage > 0) {
+ __raw_writel(clksrc, S3C2443_SCLKCON);
+ }
+
+ clk->parent = parent;
+ return 0;
+}
+
+static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
+{
+ return s3c2443_setparent_hsmmc(clk, clk->parent);
+}
+
+static struct clk clk_hsmmc = {
+ .name = "hsmmc-if",
+ .id = -1,
+ .parent = &clk_hsmmc_div,
+ .enable = s3c2443_enable_hsmmc,
+ .set_parent = s3c2443_setparent_hsmmc,
+};
+
+/* i2s_eplldiv
+ *
+ * this clock is the output from the i2s divisor of esysclk
+*/
+
+static unsigned long s3c2443_getrate_i2s_eplldiv(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
+
+ div &= S3C2443_CLKDIV1_I2SDIV_MASK;
+ div >>= S3C2443_CLKDIV1_I2SDIV_SHIFT;
+
+ return parent_rate / (div + 1);
+}
+
+static int s3c2443_setrate_i2s_eplldiv(struct clk *clk, unsigned long rate)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
+
+ rate = s3c2443_roundrate_clksrc16(clk, rate);
+ rate = parent_rate / rate;
+
+ clkdivn &= ~S3C2443_CLKDIV1_I2SDIV_MASK;
+ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_I2SDIV_SHIFT;
+
+ __raw_writel(clkdivn, S3C2443_CLKDIV1);
+ return 0;
+}
+
+static struct clk clk_i2s_eplldiv = {
+ .name = "i2s-eplldiv",
+ .id = -1,
+ .parent = &clk_esysclk,
+ .get_rate = s3c2443_getrate_i2s_eplldiv,
+ .set_rate = s3c2443_setrate_i2s_eplldiv,
+ .round_rate = s3c2443_roundrate_clksrc16,
+};
+
+/* i2s-ref
+ *
+ * i2s bus reference clock, selectable from external, esysclk or epllref
+*/
+
+static int s3c2443_setparent_i2s(struct clk *clk, struct clk *parent)
+{
+ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
+
+ clksrc &= ~S3C2443_CLKSRC_I2S_MASK;
+
+ if (parent == &clk_epllref)
+ clksrc |= S3C2443_CLKSRC_I2S_EPLLREF;
+ else if (parent == &clk_i2s_ext)
+ clksrc |= S3C2443_CLKSRC_I2S_EXT;
+ else if (parent != &clk_i2s_eplldiv)
+ return -EINVAL;
+
+ clk->parent = parent;
+ __raw_writel(clksrc, S3C2443_CLKSRC);
+
+ return 0;
+}
+
+static struct clk clk_i2s = {
+ .name = "i2s-if",
+ .id = -1,
+ .parent = &clk_i2s_eplldiv,
+ .ctrlbit = S3C2443_SCLKCON_I2SCLK,
+ .enable = s3c2443_clkcon_enable_s,
+ .set_parent = s3c2443_setparent_i2s,
+};
+
+/* cam-if
+ *
+ * camera interface bus-clock, divided down from esysclk
+*/
+
+static unsigned long s3c2443_getrate_cam(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
+
+ div &= S3C2443_CLKDIV1_CAMDIV_MASK;
+ div >>= S3C2443_CLKDIV1_CAMDIV_SHIFT;
+
+ return parent_rate / (div + 1);
+}
+
+static int s3c2443_setrate_cam(struct clk *clk, unsigned long rate)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long clkdiv1 = __raw_readl(S3C2443_CLKDIV1);
+
+ rate = (int) (parent_rate / 19200000);
+
+ clkdiv1 &= ~S3C2443_CLKDIV1_CAMDIV_MASK;
+ clkdiv1 |= (rate - 1) << S3C2443_CLKDIV1_CAMDIV_SHIFT;
+
+ __raw_writel(clkdiv1, S3C2443_CLKDIV1);
+ return 0;
+}
+
+static struct clk clk_cam = {
+ .name = "camif-upll", /* same as 2440 name */
+ .id = -1,
+ .parent = &clk_esysclk,
+ .ctrlbit = S3C2443_SCLKCON_CAMCLK,
+ .enable = s3c2443_clkcon_enable_s,
+ .get_rate = s3c2443_getrate_cam,
+ .set_rate = s3c2443_setrate_cam,
+ .round_rate = s3c2443_roundrate_clksrc16,
+};
+
+/* display-if
+ *
+ * display interface clock, divided from esysclk
+*/
+
+static unsigned long s3c2443_getrate_display(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
+
+ div &= S3C2443_CLKDIV1_DISPDIV_MASK;
+ div >>= S3C2443_CLKDIV1_DISPDIV_SHIFT;
+
+ return parent_rate / (div + 1);
+}
+
+static int s3c2443_setrate_display(struct clk *clk, unsigned long rate)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
+
+ rate = s3c2443_roundrate_clksrc256(clk, rate);
+ rate = parent_rate / rate;
+
+ clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK;
+ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT;
+
+ __raw_writel(clkdivn, S3C2443_CLKDIV1);
+ return 0;
+}
+
+static struct clk clk_display = {
+ .name = "display-if",
+ .id = -1,
+ .parent = &clk_esysclk,
+ .ctrlbit = S3C2443_SCLKCON_DISPCLK,
+ .enable = s3c2443_clkcon_enable_s,
+ .get_rate = s3c2443_getrate_display,
+ .set_rate = s3c2443_setrate_display,
+ .round_rate = s3c2443_roundrate_clksrc256,
+};
+
+/* standard clock definitions */
+
+static struct clk init_clocks_disable[] = {
+ {
+ .name = "nand",
+ .id = -1,
+ .parent = &clk_h,
+ }, {
+ .name = "sdi",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_SDI,
+ }, {
+ .name = "adc",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_ADC,
+ }, {
+ .name = "i2c",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_IIC,
+ }, {
+ .name = "iis",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_IIS,
+ }, {
+ .name = "spi",
+ .id = 0,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_SPI0,
+ }, {
+ .name = "spi",
+ .id = 1,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_SPI1,
+ }
+};
+
+static struct clk init_clocks[] = {
+ {
+ .name = "dma",
+ .id = 0,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_DMA0,
+ }, {
+ .name = "dma",
+ .id = 1,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_DMA1,
+ }, {
+ .name = "dma",
+ .id = 2,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_DMA2,
+ }, {
+ .name = "dma",
+ .id = 3,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_DMA3,
+ }, {
+ .name = "dma",
+ .id = 4,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_DMA4,
+ }, {
+ .name = "dma",
+ .id = 5,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_DMA5,
+ }, {
+ .name = "dma",
+ .id = 6,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_DMA6,
+ }, {
+ .name = "dma",
+ .id = 7,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_DMA7,
+ }, {
+ .name = "lcd",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_LCDC,
+ }, {
+ .name = "gpio",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_GPIO,
+ }, {
+ .name = "usb-host",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_USBH,
+ }, {
+ .name = "usb-device",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_USBD,
+ }, {
+ .name = "timers",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_PWMT,
+ }, {
+ .name = "uart",
+ .id = 0,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_UART0,
+ }, {
+ .name = "uart",
+ .id = 1,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_UART1,
+ }, {
+ .name = "uart",
+ .id = 2,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_UART2,
+ }, {
+ .name = "uart",
+ .id = 3,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_UART3,
+ }, {
+ .name = "rtc",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_RTC,
+ }, {
+ .name = "watchdog",
+ .id = -1,
+ .parent = &clk_p,
+ .ctrlbit = S3C2443_PCLKCON_WDT,
+ }, {
+ .name = "usb-bus-host",
+ .id = -1,
+ .parent = &clk_usb_bus_host,
+ },{
+ .name = "hsmmc",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_HSMMC
+ },{
+ .name = "hsmmc-epll",
+ .id = -1,
+ .parent = &clk_epll,
+ },{
+ .name = "hsmmc-ext",
+ .id = -1,
+ .parent = &clk_ext,
+ .enable = s3c2443_clkcon_enable_s,
+ .ctrlbit = S3C2443_SCLKCON_HSMMCCLK_EXT,
+ .rate = 12 * 1000 * 1000
+ },{
+ .name = "cfata",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_CFC
+ },
+
+};
+
+/* clocks to add where we need to check their parentage */
+
+/* s3c2443_clk_initparents
+ *
+ * Initialise the parents for the clocks that we get at start-time
+*/
+
+static int __init clk_init_set_parent(struct clk *clk, struct clk *parent)
+{
+ printk(KERN_DEBUG "clock %s: parent %s\n", clk->name, parent->name);
+ return clk_set_parent(clk, parent);
+}
+
+static void __init s3c2443_clk_initparents(void)
+{
+ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
+ struct clk *parent;
+
+ switch (clksrc & S3C2443_CLKSRC_EPLLREF_MASK) {
+ case S3C2443_CLKSRC_EPLLREF_EXTCLK:
+ parent = &clk_ext;
+ break;
+
+ case S3C2443_CLKSRC_EPLLREF_XTAL:
+ default:
+ parent = &clk_xtal;
+ break;
+
+ case S3C2443_CLKSRC_EPLLREF_MPLLREF:
+ case S3C2443_CLKSRC_EPLLREF_MPLLREF2:
+ parent = &clk_mpllref;
+ break;
+ }
+
+ clk_init_set_parent(&clk_epllref, parent);
+
+ switch (clksrc & S3C2443_CLKSRC_I2S_MASK) {
+ case S3C2443_CLKSRC_I2S_EXT:
+ parent = &clk_i2s_ext;
+ break;
+
+ case S3C2443_CLKSRC_I2S_EPLLDIV:
+ default:
+ parent = &clk_i2s_eplldiv;
+ break;
+
+ case S3C2443_CLKSRC_I2S_EPLLREF:
+ case S3C2443_CLKSRC_I2S_EPLLREF3:
+ parent = &clk_epllref;
+ }
+
+ clk_init_set_parent(&clk_i2s, &clk_epllref);
+
+ /* esysclk source */
+
+ parent = (clksrc & S3C2443_CLKSRC_ESYSCLK_EPLL) ?
+ &clk_epll : &clk_epllref;
+
+ clk_init_set_parent(&clk_esysclk, parent);
+
+ /* msysclk source */
+
+ if (clksrc & S3C2443_CLKSRC_MSYSCLK_MPLL) {
+ parent = &clk_mpll;
+ } else {
+ parent = (clksrc & S3C2443_CLKSRC_EXTCLK_DIV) ?
+ &clk_mdivclk : &clk_mpllref;
+ }
+
+ clk_init_set_parent(&clk_msysclk, parent);
+}
+
+/* armdiv divisor table */
+
+static unsigned int armdiv[16] = {
+ [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
+ [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
+ [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3,
+ [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4,
+ [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6,
+ [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8,
+ [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12,
+ [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
+};
+
+static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
+{
+ clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
+
+ return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
+}
+
+static inline unsigned long s3c2443_get_prediv(unsigned long clkcon0)
+{
+ clkcon0 &= S3C2443_CLKDIV0_PREDIV_MASK;
+ clkcon0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
+
+ return clkcon0 + 1;
+}
+
+/* clocks to add straight away */
+
+static struct clk *clks[] __initdata = {
+ &clk_ext,
+ &clk_epll,
+ &clk_usb_bus_host,
+ &clk_usb_bus,
+ &clk_esysclk,
+ &clk_epllref,
+ &clk_mpllref,
+ &clk_msysclk,
+ &clk_uart,
+ &clk_display,
+ &clk_cam,
+ &clk_i2s_eplldiv,
+ &clk_i2s,
+ &clk_hsspi,
+ &clk_hsmmc_div,
+ &clk_hsmmc,
+};
+
+void __init s3c2450_init_clocks(int xtal)
+{
+ unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
+ unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
+ unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+ unsigned long pll;
+ unsigned long fclk;
+ unsigned long hclk;
+ unsigned long pclk;
+ struct clk *clkp;
+ int ret;
+ int ptr;
+
+ pll = s3c2443_get_mpll(mpllcon, xtal);
+
+ fclk = pll / s3c2443_fclk_div(clkdiv0);
+ /* bug fix */
+ /* hclk = fclk / s3c2443_get_prediv(clkdiv0); */
+ hclk = pll / s3c2443_get_prediv(clkdiv0);
+ hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
+ pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
+
+ s3c24xx_setup_clocks(fclk, hclk, pclk);
+
+ printk("S3C2450: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
+ (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
+ print_mhz(pll), print_mhz(fclk),
+ print_mhz(hclk), print_mhz(pclk));
+
+ s3c2443_clk_initparents();
+
+ for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
+ clkp = clks[ptr];
+
+ ret = s3c24xx_register_clock(clkp);
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to register clock %s (%d)\n",
+ clkp->name, ret);
+ }
+ }
+
+ clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
+
+ clk_usb_bus.parent = &clk_usb_bus_host;
+
+ /* ensure usb bus clock is within correct rate of 48MHz */
+
+ if (clk_get_rate(&clk_usb_bus_host) != (48 * 1000 * 1000)) {
+ printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
+ clk_set_rate(&clk_usb_bus_host, 48*1000*1000);
+ }
+
+ printk("S3C2450: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
+ (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
+ print_mhz(clk_get_rate(&clk_epll)),
+ print_mhz(clk_get_rate(&clk_usb_bus)));
+
+ /* register clocks from clock array */
+
+ clkp = init_clocks;
+ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
+ ret = s3c24xx_register_clock(clkp);
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to register clock %s (%d)\n",
+ clkp->name, ret);
+ }
+ }
+
+ /* We must be careful disabling the clocks we are not intending to
+ * be using at boot time, as subsytems such as the LCD which do
+ * their own DMA requests to the bus can cause the system to lockup
+ * if they where in the middle of requesting bus access.
+ *
+ * Disabling the LCD clock if the LCD is active is very dangerous,
+ * and therefore the bootloader should be careful to not enable
+ * the LCD clock if it is not needed.
+ */
+
+ /* install (and disable) the clocks we do not need immediately */
+
+ clkp = init_clocks_disable;
+ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+ ret = s3c24xx_register_clock(clkp);
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to register clock %s (%d)\n",
+ clkp->name, ret);
+ }
+
+ (clkp->enable)(clkp, 0);
+ }
+}
diff --git a/arch/arm/mach-s3c2450/dma.c b/arch/arm/mach-s3c2450/dma.c
new file mode 100644
index 0000000..60fd9d3
--- /dev/null
+++ b/arch/arm/mach-s3c2450/dma.c
@@ -0,0 +1,195 @@
+/* linux/arch/arm/mach-s3c2450/dma.c
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * Ryu Euiyoul <ryu.real@gmail.com>
+ *
+ * S3C2443 DMA selection
+ *
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <mach/dma.h>
+
+#include <plat/dma-plat.h>
+#include <plat/cpu.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+#include <plat/regs-ac97.h>
+#include <plat/regs-dma.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
+#include <mach/regs-sdi.h>
+#include <plat/regs-iis.h>
+#include <plat/regs-spi.h>
+
+#define MAP(x) { (x) | DMA_CH_VALID, }
+
+
+static struct s3c24xx_dma_map __initdata s3c2450_dma_mappings[] = {
+ [DMACH_XD0] = {
+ .name = "xdreq0",
+ .channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
+ },
+ [DMACH_XD1] = {
+ .name = "xdreq1",
+ .channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
+ },
+ [DMACH_SDI] = {
+ .name = "sdi",
+ .channels = MAP(S3C2443_DMAREQSEL_SDI),
+ .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
+ .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
+ },
+ [DMACH_SPI_TX] = {
+ .name = "spi-tx",
+ .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
+ .hw_addr.from = S3C_PA_SPI_0 + S3C_SPI_TX_DATA,
+ },
+ [DMACH_SPI_RX] = {
+ .name = "spi-rx",
+ .channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
+ .hw_addr.to = S3C_PA_SPI_0 + S3C_SPI_RX_DATA,
+ },
+ [DMACH_SPI0] = {
+ .name = "spi0",
+ .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
+ .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
+ .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
+ },
+ [DMACH_SPI1] = {
+ .name = "spi1",
+ .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
+ .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
+ .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
+ },
+ [DMACH_UART0] = {
+ .name = "uart0",
+ .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
+ .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
+ .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
+ },
+ [DMACH_UART1] = {
+ .name = "uart1",
+ .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
+ .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
+ .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
+ },
+ [DMACH_UART2] = {
+ .name = "uart2",
+ .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
+ .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
+ .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
+ },
+ [DMACH_UART3] = {
+ .name = "uart3",
+ .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
+ .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
+ .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
+ },
+ [DMACH_UART0_SRC2] = {
+ .name = "uart0",
+ .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
+ .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
+ .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
+ },
+ [DMACH_UART1_SRC2] = {
+ .name = "uart1",
+ .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
+ .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
+ .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
+ },
+ [DMACH_UART2_SRC2] = {
+ .name = "uart2",
+ .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
+ .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
+ .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
+ },
+ [DMACH_UART3_SRC2] = {
+ .name = "uart3",
+ .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
+ .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
+ .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
+ },
+ [DMACH_TIMER] = {
+ .name = "timer",
+ .channels = MAP(S3C2443_DMAREQSEL_TIMER),
+ },
+ [DMACH_I2S_IN] = {
+ .name = "i2s-sdi",
+ .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
+ .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFORX,
+ },
+ [DMACH_I2S_OUT] = {
+ .name = "i2s-sdo",
+ .channels = MAP(S3C2443_DMAREQSEL_I2STX),
+ .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
+ },
+ [DMACH_I2S_IN_1] = {
+ .name = "i2s-sdi",
+ .channels = MAP(S3C2450_DMAREQSEL_I2SRX_1),
+ .hw_addr.from = S3C2450_PA_IIS_1 + S3C2410_IISFIFORX,
+ },
+ [DMACH_I2S_OUT_1] = {
+ .name = "i2s-sdo",
+ .channels = MAP(S3C2450_DMAREQSEL_I2STX_1),
+ .hw_addr.to = S3C2450_PA_IIS_1 + S3C2410_IISFIFO,
+ },
+ [DMACH_PCM_IN] = {
+ .name = "pcm-in",
+ .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
+ .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
+ },
+ [DMACH_PCM_OUT] = {
+ .name = "pcm-out",
+ .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
+ .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
+ },
+ [DMACH_MIC_IN] = {
+ .name = "mic-in",
+ .channels = MAP(S3C2443_DMAREQSEL_MICIN),
+ .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
+ },
+};
+
+static void s3c2450_dma_select(struct s3c2410_dma_chan *chan,
+ struct s3c24xx_dma_map *map)
+{
+ writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
+ chan->regs + S3C2443_DMA_DMAREQSEL);
+}
+
+static struct s3c24xx_dma_selection __initdata s3c2450_dma_sel = {
+ .select = s3c2450_dma_select,
+ .dcon_mask = 0,
+ .map = s3c2450_dma_mappings,
+ .map_size = ARRAY_SIZE(s3c2450_dma_mappings),
+};
+
+static int s3c2450_dma_add(struct sys_device *sysdev)
+{
+ s3c24xx_dma_init(8, IRQ_S3C2443_DMA0, 0x100);
+ return s3c24xx_dma_init_map(&s3c2450_dma_sel);
+}
+
+static struct sysdev_driver s3c2450_dma_driver = {
+ .add = s3c2450_dma_add,
+};
+
+static int __init s3c2450_dma_init(void)
+{
+ return sysdev_driver_register(&s3c2450_sysclass, &s3c2450_dma_driver);
+}
+
+arch_initcall(s3c2450_dma_init);
diff --git a/arch/arm/mach-s3c2450/irq.c b/arch/arm/mach-s3c2450/irq.c
new file mode 100644
index 0000000..c9b6525
--- /dev/null
+++ b/arch/arm/mach-s3c2450/irq.c
@@ -0,0 +1,310 @@
+/* linux/arch/arm/mach-s3c2443/irq.c
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+*/
+
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/mach/irq.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/irq.h>
+
+#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
+
+static inline void s3c2443_irq_demux ( unsigned int irq, unsigned int len )
+{
+ unsigned int subsrc, submsk;
+ unsigned int end;
+ struct irq_desc *mydesc;
+
+ /* read the current pending interrupts, and the mask
+ * for what it is available */
+
+ subsrc = __raw_readl ( S3C2410_SUBSRCPND );
+ submsk = __raw_readl ( S3C2410_INTSUBMSK );
+
+ subsrc &= ~submsk;
+ subsrc >>= ( irq - S3C2410_IRQSUB ( 0 ) );
+ subsrc &= ( 1 << len )-1;
+
+ end = len + irq;
+ mydesc = irq_desc + irq;
+
+ for ( ; irq < end && subsrc; irq++ )
+ {
+ if ( subsrc & 1 )
+ desc_handle_irq ( irq, mydesc );
+
+ mydesc++;
+ subsrc >>= 1;
+ }
+}
+
+/* WDT/AC97 sub interrupts */
+
+static void s3c2443_irq_demux_wdtac97 ( unsigned int irq, struct irq_desc *desc )
+{
+ s3c2443_irq_demux ( IRQ_S3C2443_WDT, 2 );
+}
+
+#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
+#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
+
+static void s3c2443_irq_wdtac97_mask ( unsigned int irqno )
+{
+ s3c_irqsub_mask ( irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97 );
+}
+
+static void s3c2443_irq_wdtac97_unmask ( unsigned int irqno )
+{
+ s3c_irqsub_unmask ( irqno, INTMSK_WDTAC97 );
+}
+
+static void s3c2443_irq_wdtac97_ack ( unsigned int irqno )
+{
+ s3c_irqsub_maskack ( irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97 );
+}
+
+static struct irq_chip s3c2443_irq_wdtac97 =
+{
+ .mask = s3c2443_irq_wdtac97_mask,
+ .unmask = s3c2443_irq_wdtac97_unmask,
+ .ack = s3c2443_irq_wdtac97_ack,
+ };
+
+
+/* LCD sub interrupts */
+
+static void s3c2443_irq_demux_lcd ( unsigned int irq, struct irq_desc *desc )
+{
+ s3c2443_irq_demux ( IRQ_S3C2443_LCD1, 4 );
+}
+
+#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
+#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
+
+static void s3c2443_irq_lcd_mask ( unsigned int irqno )
+{
+ s3c_irqsub_mask ( irqno, INTMSK_LCD, SUBMSK_LCD );
+}
+
+static void s3c2443_irq_lcd_unmask ( unsigned int irqno )
+{
+ s3c_irqsub_unmask ( irqno, INTMSK_LCD );
+}
+
+static void s3c2443_irq_lcd_ack ( unsigned int irqno )
+{
+ s3c_irqsub_maskack ( irqno, INTMSK_LCD, SUBMSK_LCD );
+}
+
+static struct irq_chip s3c2443_irq_lcd =
+{
+ .mask = s3c2443_irq_lcd_mask,
+ .unmask = s3c2443_irq_lcd_unmask,
+ .ack = s3c2443_irq_lcd_ack,
+ };
+
+
+/* DMA sub interrupts */
+
+static void s3c2443_irq_demux_dma ( unsigned int irq, struct irq_desc *desc )
+{
+ s3c2443_irq_demux ( IRQ_S3C2443_DMA0, 6 );
+ s3c2443_irq_demux ( IRQ_S3C2443_DMA6, 2 );
+}
+
+
+#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
+#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
+#define SUBMSK_DMA_NEW INTMSK(IRQ_S3C2443_DMA6, IRQ_S3C2443_DMA7)
+
+
+static void s3c2443_irq_dma_mask ( unsigned int irqno )
+{
+ if ( irqno < IRQ_S3C2443_DMA6 )
+ s3c_irqsub_mask ( irqno, INTMSK_DMA, SUBMSK_DMA );
+ else
+ s3c_irqsub_mask ( irqno, INTMSK_DMA, SUBMSK_DMA_NEW );
+}
+
+static void s3c2443_irq_dma_unmask ( unsigned int irqno )
+{
+ s3c_irqsub_unmask ( irqno, INTMSK_DMA );
+}
+
+static void s3c2443_irq_dma_ack ( unsigned int irqno )
+{
+ if ( irqno < IRQ_S3C2443_DMA6 )
+ s3c_irqsub_maskack ( irqno, INTMSK_DMA, SUBMSK_DMA );
+ else
+ s3c_irqsub_maskack ( irqno, INTMSK_DMA, SUBMSK_DMA_NEW );
+}
+
+static struct irq_chip s3c2443_irq_dma =
+{
+ .mask = s3c2443_irq_dma_mask,
+ .unmask = s3c2443_irq_dma_unmask,
+ .ack = s3c2443_irq_dma_ack,
+ };
+
+/* UART3 sub interrupts */
+
+static void s3c2443_irq_demux_uart3 ( unsigned int irq, struct irq_desc *desc )
+{
+ s3c2443_irq_demux ( IRQ_S3C2443_UART3, 3 );
+}
+
+#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
+#define SUBMSK_UART3 (0xf << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
+
+
+static void s3c2443_irq_uart3_mask ( unsigned int irqno )
+{
+ s3c_irqsub_mask ( irqno, INTMSK_UART3, SUBMSK_UART3 );
+}
+
+static void s3c2443_irq_uart3_unmask ( unsigned int irqno )
+{
+ s3c_irqsub_unmask ( irqno, INTMSK_UART3 );
+}
+
+static void s3c2443_irq_uart3_ack ( unsigned int irqno )
+{
+ s3c_irqsub_maskack ( irqno, INTMSK_UART3, SUBMSK_UART3 );
+}
+
+static struct irq_chip s3c2443_irq_uart3 =
+{
+ .mask = s3c2443_irq_uart3_mask,
+ .unmask = s3c2443_irq_uart3_unmask,
+ .ack = s3c2443_irq_uart3_ack,
+ };
+
+
+/* CAM sub interrupts */
+
+static void s3c2443_irq_demux_cam ( unsigned int irq, struct irq_desc *desc )
+{
+ s3c2443_irq_demux ( IRQ_S3C2440_CAM_C, 4 );
+}
+
+#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
+#define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
+
+static void s3c2443_irq_cam_mask ( unsigned int irqno )
+{
+ s3c_irqsub_mask ( irqno, INTMSK_CAM, SUBMSK_CAM );
+}
+
+static void s3c2443_irq_cam_unmask ( unsigned int irqno )
+{
+ s3c_irqsub_unmask ( irqno, INTMSK_CAM );
+}
+
+static void s3c2443_irq_cam_ack ( unsigned int irqno )
+{
+ s3c_irqsub_maskack ( irqno, INTMSK_CAM, SUBMSK_CAM );
+}
+
+static struct irq_chip s3c2443_irq_cam =
+{
+ .mask = s3c2443_irq_cam_mask,
+ .unmask = s3c2443_irq_cam_unmask,
+ .ack = s3c2443_irq_cam_ack,
+ };
+
+/* IRQ initialisation code */
+
+static int __init s3c2443_add_sub ( unsigned int base,
+ void ( *demux ) ( unsigned int,
+ struct irq_desc * ),
+ struct irq_chip *chip,
+ unsigned int start, unsigned int end )
+{
+ unsigned int irqno;
+
+ set_irq_chip ( base, &s3c_irq_level_chip );
+ set_irq_handler ( base, handle_level_irq );
+ set_irq_chained_handler ( base, demux );
+
+ for ( irqno = start; irqno <= end; irqno++ )
+ {
+ set_irq_chip ( irqno, chip );
+ set_irq_handler ( irqno, handle_level_irq );
+ set_irq_flags ( irqno, IRQF_VALID );
+
+ if ( irqno == IRQ_S3C2443_DMA5 )
+ irqno += 5;
+ }
+
+ return 0;
+}
+
+static int s3c2443_irq_add ( struct sys_device *sysdev )
+{
+ printk ( "S3C2450: IRQ Support\n" );
+
+ s3c2443_add_sub ( IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam,
+ IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P );
+
+ s3c2443_add_sub ( IRQ_LCD, s3c2443_irq_demux_lcd, &s3c2443_irq_lcd,
+ IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4 );
+
+ s3c2443_add_sub ( IRQ_S3C2443_DMA, s3c2443_irq_demux_dma,
+ &s3c2443_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA7 );
+
+ s3c2443_add_sub ( IRQ_S3C2443_UART3, s3c2443_irq_demux_uart3,
+ &s3c2443_irq_uart3,
+ IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3 );
+
+ s3c2443_add_sub ( IRQ_WDT, s3c2443_irq_demux_wdtac97,
+ &s3c2443_irq_wdtac97,
+ IRQ_S3C2443_WDT, IRQ_S3C2443_AC97 );
+
+ return 0;
+}
+
+static struct sysdev_driver s3c2450_irq_driver =
+{
+ .add = s3c2443_irq_add,
+ };
+
+static int s3c2450_irq_init ( void )
+{
+ return sysdev_driver_register ( &s3c2450_sysclass, &s3c2450_irq_driver );
+}
+
+arch_initcall ( s3c2450_irq_init );
+
diff --git a/arch/arm/mach-s3c2450/mach-smdk2450.c b/arch/arm/mach-s3c2450/mach-smdk2450.c
new file mode 100644
index 0000000..7dcc4ae
--- /dev/null
+++ b/arch/arm/mach-s3c2450/mach-smdk2450.c
@@ -0,0 +1,418 @@
+/* linux/arch/arm/mach-s3c2450/mach-smdk2450.c
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * Ryu Euiyoul <ryu.real@gmail.com>
+ *
+ * http://www.fluff.org/ben/smdk2443/
+ *
+ * Thanks to Samsung for the loan of an SMDK2450
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/setup.h>
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-gpioj.h>
+#include <mach/regs-lcd.h>
+#include <mach/regs-mem.h>
+
+#include <mach/idle.h>
+#include <mach/fb.h>
+#include <plat/iic.h>
+
+#include <plat/s3c2410.h>
+#include <plat/s3c2440.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#include <plat/common-smdk.h>
+
+#include <plat/nand.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <mach/hsmmc.h>
+
+static struct map_desc smdk2450_iodesc[] __initdata = {
+ IODESC_ENT(CS8900),
+};
+
+#define UCON S3C2410_UCON_DEFAULT | S3C2440_UCON_FCLK
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c24xx_uart_clksrc smdk2450_serial_clocks[] = {
+ [0] = {
+ .name = "pclk",
+ .divisor = 1,
+ .min_baud = 0,
+ .max_baud = 0,
+ },
+ [1] = {
+ .name = "esysclk",
+ .divisor = 1,
+ .min_baud = 0,
+ .max_baud = 0,
+ }
+
+};
+
+static struct s3c2410_uartcfg smdk2450_uartcfgs[] __initdata = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = 0x3c5,
+ .ulcon = 0x03,
+ .ufcon = 0x51,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ /* Use PCLK */
+ .ucon = 0x3c5,
+ //.ucon = 0xfc5,
+ .ulcon = 0x03,
+ .ufcon = 0x51,
+ .clocks = smdk2450_serial_clocks,
+ .clocks_size = ARRAY_SIZE(smdk2450_serial_clocks),
+ },
+ /* IR port */
+ [2] = {
+ .hwport = 2,
+ .flags = 0,
+ .ucon = 0x3c5,
+// .ucon = 0xfc5,
+ .ulcon = 0x03,
+// .ulcon = 0x43,
+ .ufcon = 0x51,
+ .clocks = smdk2450_serial_clocks,
+ .clocks_size = ARRAY_SIZE(smdk2450_serial_clocks),
+ }
+};
+
+static struct platform_device *smdk2450_devices[] __initdata = {
+ &s3c_device_spi0,
+ &s3c_device_spi1,
+ &s3c_device_wdt,
+ &s3c_device_i2c,
+ &s3c_device_lcd,
+ &s3c_device_rtc,
+ &s3c_device_adc,
+ &s3c_device_iis,
+ &s3c_device_usbgadget,
+ &s3c_device_usb,
+ &s3c_device_hsmmc0,
+ &s3c_device_hsmmc1,
+ &s3c_device_smc911x,
+ &s3c_device_ide,
+ &s3c_device_camif,
+};
+
+static struct s3c24xx_board smdk2450_board __initdata = {
+ .devices = smdk2450_devices,
+ .devices_count = ARRAY_SIZE(smdk2450_devices)
+};
+
+static void __init smdk2450_map_io(void)
+{
+ s3c24xx_init_io(smdk2450_iodesc, ARRAY_SIZE(smdk2450_iodesc));
+ s3c24xx_init_clocks(12000000);
+ s3c24xx_init_uarts(smdk2450_uartcfgs, ARRAY_SIZE(smdk2450_uartcfgs));
+ s3c24xx_set_board(&smdk2450_board);
+}
+
+static void smdk2450_cs89x0_set(void)
+{
+ u32 val;
+
+ val = readl(S3C_BANK_CFG);
+ val &= ~((1<<8)|(1<<9)|(1<<10));
+ writel(val, S3C_BANK_CFG);
+
+ /* Bank1 Idle cycle ctrl. */
+ writel(0xf, S3C_SSMC_SMBIDCYR1);
+
+ /* Bank1 Read Wait State cont. = 14 clk Tacc? */
+ writel(12, S3C_SSMC_SMBWSTRDR1);
+
+ /* Bank1 Write Wait State ctrl. */
+ writel(12, S3C_SSMC_SMBWSTWRR1);
+
+ /* Bank1 Output Enable Assertion Delay ctrl. Tcho? */
+ writel(2, S3C_SSMC_SMBWSTOENR1);
+
+ /* Bank1 Write Enable Assertion Delay ctrl. */
+ writel(2, S3C_SSMC_SMBWSTWENR1);
+
+ /* SMWAIT active High, Read Byte Lane Enabl WS1? */
+ val = readl(S3C_SSMC_SMBCR1);
+
+ val |= ((1<<15)|(1<<7));
+ writel(val, S3C_SSMC_SMBCR1);
+
+ val = readl(S3C_SSMC_SMBCR1);
+ val |= ((1<<2)|(1<<0));
+ writel(val, S3C_SSMC_SMBCR1);
+
+ val = readl(S3C_SSMC_SMBCR1);
+ val &= ~((3<<20)|(3<<12));
+ writel(val, S3C_SSMC_SMBCR1);
+
+ val = readl(S3C_SSMC_SMBCR1);
+ val &= ~(3<<4);
+ writel(val, S3C_SSMC_SMBCR1);
+
+ val = readl(S3C_SSMC_SMBCR1);
+ val |= (1<<4);
+
+ writel(val, S3C_SSMC_SMBCR1);
+
+}
+
+static void smdk2450_smc911x_set(void)
+{
+ u32 val;
+
+ /* Bank1 Idle cycle ctrl. */
+ writel(0xf, S3C_SSMC_SMBIDCYR4);
+
+ /* Bank1 Read Wait State cont. = 14 clk Tacc? */
+ writel(12, S3C_SSMC_SMBWSTRDR4);
+
+ /* Bank1 Write Wait State ctrl. */
+ writel(12, S3C_SSMC_SMBWSTWRR4);
+
+ /* Bank1 Output Enable Assertion Delay ctrl. Tcho? */
+ writel(2, S3C_SSMC_SMBWSTOENR4);
+
+ /* Bank1 Write Enable Assertion Delay ctrl. */
+ writel(2, S3C_SSMC_SMBWSTWENR4);
+
+ /* SMWAIT active High, Read Byte Lane Enabl WS1? */
+ val = readl(S3C_SSMC_SMBCR4);
+
+ val |= ((1<<15)|(1<<7));
+ writel(val, S3C_SSMC_SMBCR4);
+
+ val = readl(S3C_SSMC_SMBCR4);
+ val |= ((1<<2)|(1<<0));
+ writel(val, S3C_SSMC_SMBCR4);
+
+ val = readl(S3C_SSMC_SMBCR4);
+ val &= ~((3<<20)|(3<<12));
+ writel(val, S3C_SSMC_SMBCR4);
+
+ val = readl(S3C_SSMC_SMBCR4);
+ val &= ~(3<<4);
+ writel(val, S3C_SSMC_SMBCR4);
+
+ val = readl(S3C_SSMC_SMBCR4);
+ val |= (1<<4);
+
+ writel(val, S3C_SSMC_SMBCR4);
+
+}
+
+static void __init smdk2450_machine_init(void)
+{
+ /* SROM init for NFS */
+ smdk2450_cs89x0_set();
+ smdk2450_smc911x_set();
+
+ smdk_machine_init();
+}
+
+static void __init smdk2450_fixup (struct machine_desc *desc, struct tag *tags,
+ char **cmdline, struct meminfo *mi)
+{
+ /*
+ * Bank start addresses are not present in the information
+ * passed in from the boot loader. We could potentially
+ * detect them, but instead we hard-code them.
+ */
+ mi->bank[0].start = 0x30000000;
+
+#if defined(CONFIG_VIDEO_SAMSUNG)
+ mi->bank[0].size = 49*1024*1024;
+#elif defined(CONFIG_PP_S3C2443)
+ mi->bank[0].size = 60*1024*1024;
+#else
+ mi->bank[0].size = 64*1024*1024;
+#endif
+ mi->bank[0].node = 0;
+
+ mi->nr_banks = 1;
+}
+
+
+MACHINE_START(SMDK2450, "SMDK2450")
+ /* Maintainer: Ben Dooks <ben@fluff.org> */
+ .phys_io = S3C2410_PA_UART,
+ .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+ .boot_params = S3C2410_SDRAM_PA + 0x100,
+
+ .init_irq = s3c24xx_init_irq,
+ .map_io = smdk2450_map_io,
+ .fixup = smdk2450_fixup,
+ .init_machine = smdk2450_machine_init,
+ .timer = &s3c24xx_timer,
+MACHINE_END
+
+
+/*
+ * HS-MMC GPIO Set function for S3C2450 SMDK board
+ */
+void hsmmc_set_gpio (uint channel, uint width)
+{
+ switch (channel) {
+
+ /* can supports 1 and 4 bit bus */
+ case 0:
+ /* GPIO E : Command, Clock */
+ s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2450_GPE5_SD0_CLK);
+ s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2450_GPE6_SD0_CMD);
+
+ if (width == 1) {
+ /* GPIO E : MMC DATA0[0] */
+ s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
+ }
+ else if (width == 4) {
+ /* GPIO E : MMC DATA0[0:3] */
+ s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
+ s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2450_GPE8_SD0_DAT1);
+ s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2450_GPE9_SD0_DAT2);
+ s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2450_GPE10_SD0_DAT3);
+ }
+ break;
+
+ /* can supports 1, 4, and 8 bit bus */
+ case 1:
+ /* GPIO L : Command, Clock */
+ s3c2410_gpio_cfgpin(S3C2443_GPL8, S3C2450_GPL8_SD1CMD);
+ s3c2410_gpio_cfgpin(S3C2443_GPL9, S3C2450_GPL9_SD1CLK);
+
+ /* GPIO J : Chip detect, LED, Write Protect */
+ s3c2410_gpio_cfgpin(S3C2443_GPJ13, S3C2450_GPJ13_SD1LED);
+ s3c2410_gpio_cfgpin(S3C2443_GPJ14, S3C2450_GPJ14_nSD1CD);
+
+ s3c2410_gpio_cfgpin(S3C2443_GPJ15, S3C2450_GPJ15_nSD1WP); /* write protect enable */
+ s3c2410_gpio_setpin(S3C2443_GPJ15, 1);
+
+ if (width == 1) {
+ /* GPIO L : MMC DATA1[0] */
+ s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
+ }
+ else if (width == 4) {
+ /* GPIO L : MMC DATA1[0:3] */
+ s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
+ s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2450_GPL1_SD1DAT1);
+ s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2450_GPL2_SD1DAT2);
+ s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2450_GPL3_SD1DAT3);
+ }
+ else if (width == 8) {
+ /* GPIO L : MMC DATA1[0:7] */
+ s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
+ s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2450_GPL1_SD1DAT1);
+ s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2450_GPL2_SD1DAT2);
+ s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2450_GPL3_SD1DAT3);
+
+ s3c2410_gpio_cfgpin(S3C2443_GPL4, S3C2450_GPL4_SD1DAT4);
+ s3c2410_gpio_cfgpin(S3C2443_GPL5, S3C2450_GPL5_SD1DAT5);
+ s3c2410_gpio_cfgpin(S3C2443_GPL6, S3C2450_GPL6_SD1DAT6);
+ s3c2410_gpio_cfgpin(S3C2443_GPL7, S3C2450_GPL7_SD1DAT7);
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+
+#define HOST_CAPS (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | \
+ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)
+#define MMC_MODE_MMC 0
+#define MMC_MODE_SD 1
+/* Channel 0 : added HS-MMC channel */
+struct s3c_hsmmc_cfg s3c_hsmmc0_platform = {
+ .hwport = 0,
+ .enabled = 1,
+ .host_caps = HOST_CAPS,
+ .bus_width = 4,
+ .highspeed = 0,
+
+ /* ctrl for mmc */
+ .fd_ctrl[MMC_MODE_MMC] = {
+ .ctrl2 = 0xC0000100, /* ctrl2 for mmc */
+ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
+ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
+ .ctrl4 = 0x3,
+ },
+
+ /* ctrl for sd */
+ .fd_ctrl[MMC_MODE_SD] = {
+ .ctrl2 = 0xC0000100, /* ctrl2 for sd */
+ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
+ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
+ .ctrl4 = 0x3,
+ },
+
+ .clk_name[0] = "hsmmc", /* 1st clock source */
+ .clk_name[1] = "esysclk", /* 2nd clock source hsmmc-epll by Ben Dooks */
+ .clk_name[2] = "hsmmc-ext", /* 3rd clock source */
+};
+
+/* Channel 1 : default HS-MMC channel */
+struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
+ .hwport = 1,
+ .enabled = 1,
+ .host_caps = HOST_CAPS | MMC_CAP_8_BIT_DATA,
+ .bus_width = 8,
+ .highspeed = 0,
+
+ /* ctrl for mmc */
+ .fd_ctrl[MMC_MODE_MMC] = {
+ .ctrl2 = 0xC0000100, /* ctrl2 for mmc */
+ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
+ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
+ .ctrl4 = 0x3,
+ },
+
+ /* ctrl for sd */
+ .fd_ctrl[MMC_MODE_SD] = {
+ .ctrl2 = 0xC0000100, /* ctrl2 for sd */
+ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
+ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
+ .ctrl4 = 0x3,
+ },
+
+ .clk_name[0] = "hsmmc", /* 1st clock source */
+ .clk_name[1] = "esysclk", /* 2nd clock source hsmmc-epll by Ben Dooks */
+ .clk_name[2] = "hsmmc-ext", /* 3rd clock source */
+};
+
diff --git a/arch/arm/mach-s3c2450/maino.c b/arch/arm/mach-s3c2450/maino.c
new file mode 100644
index 0000000..28d5f9b
--- /dev/null
+++ b/arch/arm/mach-s3c2450/maino.c
@@ -0,0 +1,49 @@
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/setup.h>
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-gpioj.h>
+#include <mach/regs-lcd.h>
+#include <mach/regs-mem.h>
+
+#include <mach/idle.h>
+#include <mach/fb.h>
+#include <plat/iic.h>
+
+#include <plat/s3c2410.h>
+#include <plat/s3c2440.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#include <plat/common-smdk.h>
+
+#include <plat/nand.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <mach/hsmmc.h>
+int maino() {
+ unsigned int i=IRQ_S3C2443_DMA6;
+ sprintf("%d\n", i);
+ return 0;
+}
+
diff --git a/arch/arm/mach-s3c2450/pm.c b/arch/arm/mach-s3c2450/pm.c
new file mode 100644
index 0000000..344bae1
--- /dev/null
+++ b/arch/arm/mach-s3c2450/pm.c
@@ -0,0 +1,158 @@
+/* linux/arch/arm/mach-s3c2450/pm.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://armlinux.simtec.co.uk/.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/errno.h>
+#include <linux/time.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-power.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpioj.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-dsc.h>
+#include <mach/regs-s3c2450-clock.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+
+#include <plat/s3c2450.h>
+
+static void s3c2450_cpu_suspend(void)
+{
+ //unsigned long tmp;
+
+ /* USB Physical power */
+ __raw_writel(__raw_readl(S3C2443_PHYPWR) | 0xf, S3C2443_PHYPWR);
+
+ /* USB Suspend mode */
+ __raw_writel(__raw_readl(S3C2410_MISCCR)|(1<<12)|(1<<13), S3C2410_MISCCR);
+
+ __raw_writel(0xffffffff, S3C2410_INTMSK);
+ __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
+ __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
+
+ __raw_writel(0xffffffff, S3C2410_EINTPEND);
+ __raw_writel(0xffffffff, S3C2410_EINTMASK);
+ __raw_writel(0xffffffff, S3C2410_SRCPND);
+ __raw_writel(0xffffffff, S3C2410_INTPND);
+
+ __raw_writel(0xff80, S3C2443_RSTCON);
+ __raw_writel(0xffff, S3C2443_OSCSET);
+ /* ack any outstanding external interrupts before we go to sleep */
+
+ __raw_writel((0xffffffff & ~((1<<0) | (1<<3) | (1<<30))) , S3C2410_INTMSK);
+
+ __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
+ __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
+ __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
+
+ __raw_writel( (1<<15), S3C2443_PWRCFG);
+
+ /* set our standby method to sleep */
+ __raw_writel(0x2BED, S3C2443_PWRMODE);
+}
+
+static void s3c2450_pm_prepare(void)
+{
+ int ret;
+
+ /* set flag to wake up */
+ __raw_writel(0x2BED, S3C2443_INFORM0);
+
+ /* memory auto-detect configuration for u-boot side wake-up */
+ ret = __raw_readl(S3C2410_BWSCON) & S3C2410_MEMCFG_MASK;
+
+ if(ret == S3C2410_MEMCFG_MDDR)
+ __raw_writel(0xDD, S3C2443_INFORM2); /* mDDR */
+ else if(ret == S3C2410_MEMCFG_MSDR)
+ __raw_writel(0xDA, S3C2443_INFORM2); /* mSDRAM */
+ else if(ret == S3C2410_MEMCFG_DDR2)
+ panic("DDR2 is not supported at u-boot");
+ else
+ panic("memory setup is not correct?");
+
+
+}
+
+static int s3c2450_pm_add(struct sys_device *sysdev)
+{
+ pm_cpu_prep = s3c2450_pm_prepare;
+ pm_cpu_sleep = s3c2450_cpu_suspend;
+
+ return 0;
+}
+
+static struct sleep_save s3c2450_sleep[] = {
+// SAVE_ITEM(S3C2450_DSC0),
+// SAVE_ITEM(S3C2450_DSC1),
+// SAVE_ITEM(S3C2413_GPJDAT),
+// SAVE_ITEM(S2C2413_GPJCON),
+// SAVE_ITEM(S3C2413_GPJUP),
+
+ /* save the PWRCFG to get back to original sleep method */
+
+// SAVE_ITEM(S3C2443_PWRMODE),
+
+ /* save the sleep configuration anyway, just in case these
+ * get damaged during wakeup */
+
+// SAVE_ITEM(S3C2450_GPBSLPCON),
+// SAVE_ITEM(S3C2450_GPCSLPCON),
+// SAVE_ITEM(S3C2450_GPDSLPCON),
+// SAVE_ITEM(S3C2450_GPESLPCON),
+// SAVE_ITEM(S3C2450_GPFSLPCON),
+// SAVE_ITEM(S3C2450_GPGSLPCON),
+// SAVE_ITEM(S3C2450_GPHSLPCON),
+// SAVE_ITEM(S3C2413_GPJSLPCON),
+};
+
+static int s3c2450_pm_suspend(struct sys_device *dev, pm_message_t state)
+{
+ s3c_pm_do_save(s3c2450_sleep, ARRAY_SIZE(s3c2450_sleep));
+ return 0;
+}
+
+static int s3c2450_pm_resume(struct sys_device *dev)
+{
+// unsigned long tmp;
+
+// tmp = __raw_readl(S3C2443_RSTCON);
+// tmp |= (1<<16);
+// __raw_writel(tmp, S3C2443_RSTCON);
+// __raw_writel(0, S3C2443_PWRMODE);
+
+ __raw_writel(0x0, S3C2443_INFORM0);
+ __raw_writel(0x0, S3C2443_INFORM2);
+ s3c_pm_do_restore(s3c2450_sleep, ARRAY_SIZE(s3c2450_sleep));
+ return 0;
+}
+
+static struct sysdev_driver s3c2450_pm_driver = {
+ .add = s3c2450_pm_add,
+ .suspend = s3c2450_pm_suspend,
+ .resume = s3c2450_pm_resume,
+};
+
+static __init int s3c2450_pm_init(void)
+{
+ return sysdev_driver_register(&s3c2450_sysclass, &s3c2450_pm_driver);
+}
+
+arch_initcall(s3c2450_pm_init);
diff --git a/arch/arm/mach-s3c2450/s3c2450.c b/arch/arm/mach-s3c2450/s3c2450.c
new file mode 100644
index 0000000..283f957
--- /dev/null
+++ b/arch/arm/mach-s3c2450/s3c2450.c
@@ -0,0 +1,207 @@
+/* linux/arch/arm/mach-s3c2450/s3c2450.c
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * Ryu Euiyoul <ryu.real@gmail.com>
+ *
+ * Samsung S3C2450 Mobile CPU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <mach/regs-s3c2450-clock.h>
+#include <mach/idle.h>
+#include <mach/reset.h>
+
+#include <plat/s3c2450.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <asm/proc-fns.h>
+
+
+#undef DVS_IDLE
+
+static struct map_desc s3c2450_iodesc[] __initdata = {
+ IODESC_ENT(WATCHDOG),
+ IODESC_ENT(CLKPWR),
+ IODESC_ENT(TIMER),
+ IODESC_ENT(LCD),
+ IODESC_ENT(USBDEV),
+ IODESC_ENT(CAMIF),
+ IODESC_ENT(EBI),
+ IODESC_ENT(SROMC),
+};
+
+struct sysdev_class s3c2450_sysclass = {
+ .name ="s3c2450-core",
+};
+
+static struct sys_device s3c2450_sysdev = {
+ .cls = &s3c2450_sysclass,
+};
+
+static void s3c2450_hard_reset(void)
+{
+ __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
+}
+
+int __init s3c2450_init(void)
+{
+ printk("S3C2450: Initialising architecture\n");
+
+ s3c24xx_reset_hook = s3c2450_hard_reset;
+
+ s3c_device_nand.name = "s3c2412-nand";
+
+ // For S3C nand
+ s3c_device_nand.name = "s3c-nand";
+
+
+ return sysdev_register(&s3c2450_sysdev);
+}
+
+
+#undef IDLE_PROBE
+static void s3c2450_idle(void)
+{
+ unsigned long tmp;
+
+/*if you want to reduce CPU clock with idle */
+ #ifdef DVS_IDLE
+ tmp = __raw_readl(S3C2443_CLKDIV0);
+ tmp &= ~(0x1<<13);
+ tmp |= (0x1<<13);
+ __raw_writel(tmp, S3C2443_CLKDIV0);
+ #else
+ /* ensure our idle mode is to go to idle */
+ tmp = __raw_readl(S3C2443_PWRMODE);
+ tmp &= ~(0x1<<17);
+ tmp |= (0x1<<17);
+ __raw_writel(tmp, S3C2443_PWRMODE);
+ #endif
+
+/* in SMDK2450 you can probe the idle status through the TP11(GPB2) by Laputa*/
+#ifdef IDLE_PROBE
+ tmp = __raw_readl(S3C2410_GPBDAT);
+ tmp |= (0x1<<2);
+ __raw_writel(tmp, S3C2410_GPBDAT);
+ tmp &= ~(0x1<<2);
+ __raw_writel(tmp, S3C2410_GPBDAT);
+#endif
+
+ cpu_do_idle();
+}
+
+void __init s3c2450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+ s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
+
+ /* rename devices that are s3c2413/s3c2443/s3c6400 specific */
+
+#if defined (CONFIG_S3C_SIR)
+ s3c24xx_uart_src[2]->name = "s3c-irda";
+#endif
+ s3c_device_lcd.name = "s3c-lcd";
+}
+
+/* s3c2443_map_io
+ *
+ * register the standard cpu IO areas, and any passed in from the
+ * machine specific initialisation.
+ */
+
+void __init s3c2450_map_io(void/*struct map_desc *mach_desc, int mach_size*/)
+{
+ iotable_init(s3c2450_iodesc, ARRAY_SIZE(s3c2450_iodesc));
+// iotable_init(mach_desc, mach_size);
+
+ s3c24xx_idle = s3c2450_idle;
+
+}
+
+/* need to register class before we actually register the device, and
+ * we also need to ensure that it has been initialised before any of the
+ * drivers even try to use it (even if not on an s3c2443 based system)
+ * as a driver which may support both 2443 and 2440 may try and use it.
+*/
+
+static int __init s3c2450_core_init(void)
+{
+ return sysdev_class_register(&s3c2450_sysclass);
+}
+
+core_initcall(s3c2450_core_init);
+
+
+#define CAMDIV_val 26
+
+int s3c_camif_set_clock (unsigned int camclk)
+{
+ unsigned int camclk_div, val, hclkcon;
+ struct clk *src_clk = clk_get(NULL, "hclk");
+
+ if (camclk == 4800000) {
+ printk(KERN_INFO "External camera clock is set to 48MHz\n");
+ }
+ else if (camclk > 48000000) {
+ printk(KERN_ERR "Invalid camera clock\n");
+ }
+
+ writel(readl(S3C2443_CLKSRC) | (1 << 20), S3C2443_CLKSRC);
+
+ camclk_div = clk_get_rate(src_clk) / camclk;
+ printk("Parent clock = %ld, CAMDIV = %d\n", clk_get_rate(src_clk), camclk_div);
+
+ // CAMIF HCLK Enable
+ hclkcon = __raw_readl(S3C2443_HCLKCON);
+ hclkcon |= S3C2443_HCLKCON_CAMIF;
+ __raw_writel(hclkcon, S3C2443_HCLKCON);
+
+ /* CAMCLK Enable */
+ val = readl(S3C2443_SCLKCON);
+ val |= S3C2443_SCLKCON_CAMCLK;
+ writel(val, S3C2443_SCLKCON);
+
+ val = readl(S3C2443_CLKDIV1);
+ val &= ~(0xf<<CAMDIV_val);
+ writel(val, S3C2443_CLKDIV1);
+
+ val |= ((camclk_div -1) << CAMDIV_val);
+ writel(val, S3C2443_CLKDIV1);
+ val = readl(S3C2443_CLKDIV1);
+
+ return 0;
+}
+
+void s3c_camif_disable_clock (void)
+{
+ unsigned int val;
+
+ val = readl(S3C2443_SCLKCON);
+ val &= ~S3C2443_SCLKCON_CAMCLK;
+ writel(val, S3C2443_SCLKCON);
+}
+
+
+
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2450.h b/arch/arm/plat-s3c24xx/include/plat/s3c2450.h
new file mode 100644
index 0000000..f2e6d4c
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2450.h
@@ -0,0 +1,32 @@
+/* linux/include/asm-arm/plat-s4c24xx/s3c2450.h
+ *
+ * Copyright (c) 2008 Samsung Electronics
+ * Ryu Euiyoul <ryu.real@gmail.com>
+ *
+ * Header file for s3c2450 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifdef CONFIG_CPU_S3C2450
+
+struct s3c2410_uartcfg;
+
+extern int s3c2450_init(void);
+
+extern void s3c2450_map_io(void/*struct map_desc *mach_desc, int size*/);
+
+extern void s3c2450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+
+extern void s3c2450_init_clocks(int xtal);
+
+extern int s3c2443_baseclk_add(void);
+
+#else
+#define s3c2450_init_clocks NULL
+#define s3c2450_init_uarts NULL
+#define s3c2450_map_io NULL
+#define s3c2450_init NULL
+#endif
--
1.5.6.1
From e3b2f7062ac9212135f68c52ba1700da3d52995c Mon Sep 17 00:00:00 2001
From: Ferar Achkar <ferarachkar@gmail.com>
Date: Mon, 5 Apr 2010 18:33:34 -0400
Subject: [PATCH] 1. commiting those files s3c2450
---
arch/arm/mach-s3c2410/include/mach/dma.h | 6 +
arch/arm/mach-s3c2410/include/mach/hardware.h | 9 +
arch/arm/mach-s3c2410/include/mach/irqs.h | 26 +-
arch/arm/mach-s3c2410/include/mach/map.h | 17 +-
arch/arm/mach-s3c2410/include/mach/regs-gpioj.h | 38 ++
arch/arm/mach-s3c2410/include/mach/regs-mem.h | 104 ++++
arch/arm/mach-s3c2443/clock.c | 18 +-
arch/arm/plat-s3c/clock.c | 2 +
arch/arm/plat-s3c/include/plat/cpu.h | 20 +-
arch/arm/plat-s3c/include/plat/devs.h | 1 +
arch/arm/plat-s3c/include/plat/nand.h | 5 +
arch/arm/plat-s3c24xx/common-smdk.c | 59 ++
arch/arm/plat-s3c24xx/cpu.c | 117 ++++-
arch/arm/plat-s3c24xx/devs.c | 739 ++++++++++++++++++-----
arch/arm/plat-s3c24xx/dma.c | 11 +-
arch/arm/plat-s3c24xx/gpio.c | 23 +-
arch/arm/plat-s3c24xx/include/plat/map.h | 394 +++++++++++-
arch/arm/plat-s3c24xx/include/plat/regs-dma.h | 2 +
arch/arm/plat-s3c24xx/include/plat/regs-iis.h | 1 +
arch/arm/plat-s3c24xx/include/plat/regs-spi.h | 214 +++++++
arch/arm/plat-s3c24xx/irq.c | 76 +++
drivers/hwmon/s3c-hwmon.c | 4 +-
drivers/mmc/host/s3cmci.c | 608 ++++---------------
drivers/mmc/host/s3cmci.h | 14 +-
include/linux/mmc/host.h | 2 +
25 files changed, 1811 insertions(+), 699 deletions(-)
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index 92e2687..fc0d908 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -29,6 +29,8 @@ enum dma_ch {
DMACH_XD1,
DMACH_SDI,
DMACH_SPI0,
+ DMACH_SPI_TX,
+ DMACH_SPI_RX,
DMACH_SPI1,
DMACH_UART0,
DMACH_UART1,
@@ -36,6 +38,10 @@ enum dma_ch {
DMACH_TIMER,
DMACH_I2S_IN,
DMACH_I2S_OUT,
+ DMACH_I2S_IN_1, /* s3c2450 iis_1 rx */
+ DMACH_I2S_OUT_1, /* s3c2450 iis_1 tx */
+ DMACH_I2S_V40_IN,
+ DMACH_I2S_V40_OUT,
DMACH_PCM_IN,
DMACH_PCM_OUT,
DMACH_MIC_IN,
diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c2410/include/mach/hardware.h
index aef5631..4d64ee0 100644
--- a/arch/arm/mach-s3c2410/include/mach/hardware.h
+++ b/arch/arm/mach-s3c2410/include/mach/hardware.h
@@ -16,7 +16,16 @@
#ifndef __ASSEMBLY__
extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
+extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
+extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
+extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
+
+extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
+
+extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
+
+extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
#ifdef CONFIG_CPU_S3C2440
extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index 6c12c63..d1f34fc 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -144,6 +144,11 @@
#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22)
#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23)
+#if defined(CONFIG_CPU_S3C2450) || defined (CONFIG_CPU_S3C2416)
+#define IRQ_S3C2443_DMA6 S3C2410_IRQSUB(29)
+#define IRQ_S3C2443_DMA7 S3C2410_IRQSUB(30)
+#endif
+
/* UART3 */
#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24)
#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25)
@@ -152,12 +157,31 @@
#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
-#ifdef CONFIG_CPU_S3C2443
+#if defined (CONFIG_CPU_S3C2450)
+#define IRQ_CFCON S3C2410_IRQ(19)
+#define IRQ_SDI_1 S3C2410_IRQ(20)
+#define IRQ_SDI_0 S3C2410_IRQ(21)
+
+#if defined(CONFIG_CPU_S3C2450)
+#define IRQ_S3C2450_2D S3C2410_IRQSUB(31)
+#define IRQ_S3C2450_IIC1 S3C2410_IRQSUB(32)
+#define IRQ_S3C2450_GIB S3C2410_IRQSUB(33)
+#define IRQ_S3C2450_Reserved S3C2410_IRQSUB(34)
+#define IRQ_S3C2450_PCM0 S3C2410_IRQSUB(35)
+#define IRQ_S3C2450_PCM1 S3C2410_IRQSUB(36)
+#define IRQ_S3C2450_I2S0 S3C2410_IRQSUB(37)
+#define IRQ_S3C2450_I2S1 S3C2410_IRQSUB(38)
+
+#define NR_IRQS (IRQ_S3C2450_I2S1+1)
+#else
#define NR_IRQS (IRQ_S3C2443_AC97+1)
+#endif
+
#else
#define NR_IRQS (IRQ_S3C2440_AC97+1)
#endif
+
/* compatibility define. */
#define IRQ_UART3 IRQ_S3C2443_UART3
#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index b049e61..86ff4ab 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -15,9 +15,9 @@
#include <plat/map-base.h>
#include <plat/map.h>
-
+#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2450) && !defined(CONFIG_CPU_S3C2416)
#define S3C2410_ADDR(x) S3C_ADDR(x)
-
+#endif
/* USB host controller */
#define S3C2410_PA_USBHOST (0x49000000)
@@ -43,7 +43,7 @@
/* RTC */
#define S3C2410_PA_RTC (0x57000000)
-#define S3C24XX_SZ_RTC SZ_1M
+/*#define S3C24XX_SZ_RTC SZ_1M*/
/* ADC */
#define S3C2410_PA_ADC (0x58000000)
@@ -93,14 +93,21 @@
#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
#define S3C24XX_PA_DMA S3C2410_PA_DMA
#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
+
+#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2450) && !defined(CONFIG_CPU_S3C2416)
#define S3C24XX_PA_LCD S3C2410_PA_LCD
+#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
+#define S3C24XX_PA_RTC S3C2410_PA_RTC
+#endif
+
+
#define S3C24XX_PA_UART S3C2410_PA_UART
#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
-#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
+
#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
#define S3C24XX_PA_IIS S3C2410_PA_IIS
#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
-#define S3C24XX_PA_RTC S3C2410_PA_RTC
+
#define S3C24XX_PA_ADC S3C2410_PA_ADC
#define S3C24XX_PA_SPI S3C2410_PA_SPI
#define S3C24XX_PA_SDI S3C2410_PA_SDI
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
index 1202ca5..8d8d1bd 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
@@ -98,9 +98,47 @@
#define S3C2440_GPJ12_OUTP (0x01 << 24)
#define S3C2440_GPJ12_CAMRESET (0x02 << 24)
+#define S3C2443_GPL8 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 8)
#define S3C2443_GPJ13 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 13)
#define S3C2443_GPJ14 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14)
#define S3C2443_GPJ15 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15)
+#define S3C2450_GPJ13_I2S1_LRCK (0x03 << 26)
+#define S3C2450_GPJ13_SD1LED (0x02 << 26)
+#define S3C2450_GPJ14_nSD1CD (0x02 << 28)
+#define S3C2450_GPJ15_nSD1WP (0x02 << 30)
+
+#define S3C2450_GPL8_SD1CMD (0x02 << 16)
+
+#define S3C2443_GPL0 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 0)
+#define S3C2450_GPL0_SD1DAT0 (0x02 << 0)
+
+#define S3C2443_GPL1 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 1)
+#define S3C2450_GPL1_SD1DAT1 (0x02 << 2)
+
+#define S3C2443_GPL2 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 2)
+#define S3C2450_GPL2_SD1DAT2 (0x02 << 4)
+
+#define S3C2443_GPL3 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 3)
+#define S3C2450_GPL3_SD1DAT3 (0x02 << 6)
+
+#define S3C2443_GPL4 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 4)
+#define S3C2450_GPL4_SD1DAT4 (0x02 << 8)
+
+#define S3C2443_GPL5 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 5)
+#define S3C2450_GPL5_SD1DAT5 (0x02 << 10)
+
+#define S3C2443_GPL6 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 6)
+#define S3C2450_GPL6_SD1DAT6 (0x02 << 12)
+
+#define S3C2443_GPL7 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 7)
+#define S3C2450_GPL7_SD1DAT7 (0x02 << 14)
+
+
+#define S3C2443_GPL9 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 9)
+#define S3C2443_GPL9_INP (0x00 << 18)
+#define S3C2443_GPL9_OUTP (0x01 << 18)
+#define S3C2443_GPL9_SD0CLK (0x02 << 18)
+#define S3C2450_GPL9_SD1CLK (0x02 << 18)
#endif /* __ASM_ARCH_REGS_GPIOJ_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
index 7f7c529..8f43d95 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
@@ -20,6 +20,11 @@
/* bus width, and wait state control */
#define S3C2410_BWSCON S3C2410_MEMREG(0x0000)
+#define S3C2410_MEMCFG_MASK (7<<1)
+#define S3C2410_MEMCFG_MSDR (2<<1)
+#define S3C2410_MEMCFG_MDDR (6<<1)
+#define S3C2410_MEMCFG_DDR2 (1<<1)
+
/* bank zero config - note, pinstrapped from OM pins! */
#define S3C2410_BWSCON_DW0_16 (1<<1)
#define S3C2410_BWSCON_DW0_32 (2<<1)
@@ -100,6 +105,105 @@
#define S3C2410_BANKCON_PMC8 (0x02)
#define S3C2410_BANKCON_PMC16 (0x03)
+#if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)||defined(CONFIG_CPU_S3C2416)
+#define S3C_SSMCREG(x) (S3C24XX_VA_SROMC + (x))
+
+/* Bank Idle Cycle Control Registers 0-5 */
+#define S3C_SSMC_SMBIDCYR0 S3C_SSMCREG(0x0000)
+#define S3C_SSMC_SMBIDCYR1 S3C_SSMCREG(0x0020)
+#define S3C_SSMC_SMBIDCYR2 S3C_SSMCREG(0x0040)
+#define S3C_SSMC_SMBIDCYR3 S3C_SSMCREG(0x0060)
+#define S3C_SSMC_SMBIDCYR4 S3C_SSMCREG(0x0080)
+#define S3C_SSMC_SMBIDCYR5 S3C_SSMCREG(0x00A0)
+#define S3C_SSMC_SMBIDCYR6 S3C_SSMCREG(0x00C0)
+#define S3C_SSMC_SMBIDCYR7 S3C_SSMCREG(0x00E0)
+
+/* Bank Read Wait State Contro, Registers 0-5 */
+#define S3C_SSMC_SMBWSTRDR0 S3C_SSMCREG(0x0004)
+#define S3C_SSMC_SMBWSTRDR1 S3C_SSMCREG(0x0024)
+#define S3C_SSMC_SMBWSTRDR2 S3C_SSMCREG(0x0044)
+#define S3C_SSMC_SMBWSTRDR3 S3C_SSMCREG(0x0064)
+#define S3C_SSMC_SMBWSTRDR4 S3C_SSMCREG(0x0084)
+#define S3C_SSMC_SMBWSTRDR5 S3C_SSMCREG(0x00A4)
+#define S3C_SSMC_SMBWSTRDR6 S3C_SSMCREG(0x00C4)
+#define S3C_SSMC_SMBWSTRDR7 S3C_SSMCREG(0x00E4)
+
+/* Bank Write Wait State Control, Registers 0-5 */
+#define S3C_SSMC_SMBWSTWRR0 S3C_SSMCREG(0x0008)
+#define S3C_SSMC_SMBWSTWRR1 S3C_SSMCREG(0x0028)
+#define S3C_SSMC_SMBWSTWRR2 S3C_SSMCREG(0x0048)
+#define S3C_SSMC_SMBWSTWRR3 S3C_SSMCREG(0x0068)
+#define S3C_SSMC_SMBWSTWRR4 S3C_SSMCREG(0x0088)
+#define S3C_SSMC_SMBWSTWRR5 S3C_SSMCREG(0x00A8)
+#define S3C_SSMC_SMBWSTWRR6 S3C_SSMCREG(0x00C8)
+#define S3C_SSMC_SMBWSTWRR7 S3C_SSMCREG(0x00E8)
+
+/* Bank OutPut enable Assertion Delay Control Registers 0-5 */
+#define S3C_SSMC_SMBWSTOENR0 S3C_SSMCREG(0x000C)
+#define S3C_SSMC_SMBWSTOENR1 S3C_SSMCREG(0x002C)
+#define S3C_SSMC_SMBWSTOENR2 S3C_SSMCREG(0x004C)
+#define S3C_SSMC_SMBWSTOENR3 S3C_SSMCREG(0x006C)
+#define S3C_SSMC_SMBWSTOENR4 S3C_SSMCREG(0x008C)
+#define S3C_SSMC_SMBWSTOENR5 S3C_SSMCREG(0x00AC)
+#define S3C_SSMC_SMBWSTOENR6 S3C_SSMCREG(0x00CC)
+#define S3C_SSMC_SMBWSTOENR7 S3C_SSMCREG(0x00EC)
+
+/* Bank Write enable Assertion Delay Control Registers 0-5 */
+#define S3C_SSMC_SMBWSTWENR0 S3C_SSMCREG(0x0010)
+#define S3C_SSMC_SMBWSTWENR1 S3C_SSMCREG(0x0030)
+#define S3C_SSMC_SMBWSTWENR2 S3C_SSMCREG(0x0050)
+#define S3C_SSMC_SMBWSTWENR3 S3C_SSMCREG(0x0070)
+#define S3C_SSMC_SMBWSTWENR4 S3C_SSMCREG(0x0090)
+#define S3C_SSMC_SMBWSTWENR5 S3C_SSMCREG(0x00B0)
+#define S3C_SSMC_SMBWSTWENR6 S3C_SSMCREG(0x00D0)
+#define S3C_SSMC_SMBWSTWENR7 S3C_SSMCREG(0x00F0)
+
+/* Bank Control Registers 0-5 */
+#define S3C_SSMC_SMBCR0 S3C_SSMCREG(0x0014)
+#define S3C_SSMC_SMBCR1 S3C_SSMCREG(0x0034)
+#define S3C_SSMC_SMBCR2 S3C_SSMCREG(0x0054)
+#define S3C_SSMC_SMBCR3 S3C_SSMCREG(0x0074)
+#define S3C_SSMC_SMBCR4 S3C_SSMCREG(0x0094)
+#define S3C_SSMC_SMBCR5 S3C_SSMCREG(0x00B4)
+#define S3C_SSMC_SMBCR6 S3C_SSMCREG(0x00D4)
+#define S3C_SSMC_SMBCR7 S3C_SSMCREG(0x00F4)
+
+/* Bank Status Registers 0-5 */
+#define S3C_SSMC_SMBSR0 S3C_SSMCREG(0x0018)
+#define S3C_SSMC_SMBSR1 S3C_SSMCREG(0x0038)
+#define S3C_SSMC_SMBSR2 S3C_SSMCREG(0x0058)
+#define S3C_SSMC_SMBSR3 S3C_SSMCREG(0x0078)
+#define S3C_SSMC_SMBSR4 S3C_SSMCREG(0x0098)
+#define S3C_SSMC_SMBSR5 S3C_SSMCREG(0x00B8)
+#define S3C_SSMC_SMBSR6 S3C_SSMCREG(0x00D8)
+#define S3C_SSMC_SMBSR7 S3C_SSMCREG(0x00F8)
+
+/* Bank Burst Read Wait delay Control Registers 0-5 */
+#define S3C_SSMC_SMBWSTBRDR0 S3C_SSMCREG(0x001C)
+#define S3C_SSMC_SMBWSTBRDR1 S3C_SSMCREG(0x003C)
+#define S3C_SSMC_SMBWSTBRDR2 S3C_SSMCREG(0x005C)
+#define S3C_SSMC_SMBWSTBRDR3 S3C_SSMCREG(0x007C)
+#define S3C_SSMC_SMBWSTBRDR4 S3C_SSMCREG(0x009C)
+#define S3C_SSMC_SMBWSTBRDR5 S3C_SSMCREG(0x00BC)
+#define S3C_SSMC_SMBWSTBRDR6 S3C_SSMCREG(0x00DC)
+#define S3C_SSMC_SMBWSTBRDR7 S3C_SSMCREG(0x00FC)
+
+/* SROMC status register */
+#define S3C_SSMC_SSMCSR S3C_SSMCREG(0x0200)
+/* SROMC control register */
+#define S3C_SSMC_SSMCCR S3C_SSMCREG(0x0204)
+
+#define S3C_EBIREG(x) (S3C24XX_VA_EBI + (x))
+
+/* bus priority decision */
+#define S3C_EBIPR S3C_EBIREG(0x0000)
+
+/* Bank configuration register */
+#define S3C_BANK_CFG S3C_EBIREG(0x0008)
+
+
+#endif
+
/* bank configurations for banks 0..7, note banks
* 6 and 7 have differnt configurations depending on
* the memory type bits */
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 2785d69..72f9b8e 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -602,9 +602,12 @@ static int s3c2443_setrate_cam(struct clk *clk, unsigned long rate)
unsigned long parent_rate = clk_get_rate(clk->parent);
unsigned long clkdiv1 = __raw_readl(S3C2443_CLKDIV1);
+
rate = s3c2443_roundrate_clksrc16(clk, rate);
- rate = parent_rate / rate;
-
+ rate = parent_rate / rate;
+/*
+ rate = (int) (parent_rate / 19200000);
+*/
clkdiv1 &= ~S3C2443_CLKDIV1_CAMDIV_MASK;
clkdiv1 |= (rate - 1) << S3C2443_CLKDIV1_CAMDIV_SHIFT;
@@ -801,6 +804,17 @@ static struct clk init_clocks[] = {
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_HSMMC,
+ }, {
+ .name = "hsmmc-epll",
+ .id = -1,
+ .parent = &clk_epll,
+ }, {
+ .name = "hsmmc-ext",
+ .id = -1,
+ .parent = &clk_ext,
+ .enable = s3c2443_clkcon_enable_s,
+ .ctrlbit = S3C2443_SCLKCON_HSMMCCLK_EXT,
+ .rate = 12 * 1000 * 1000
}, {
.name = "cfc",
.id = -1,
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c
index 4d01ef1..d27122d 100644
--- a/arch/arm/plat-s3c/clock.c
+++ b/arch/arm/plat-s3c/clock.c
@@ -243,10 +243,12 @@ struct clk clk_ext = {
.id = -1,
};
+/*
struct clk clk_epll = {
.name = "epll",
.id = -1,
};
+*/
struct clk clk_mpll = {
.name = "mpll",
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h
index fbc3d49..f8ebd09 100644
--- a/arch/arm/plat-s3c/include/plat/cpu.h
+++ b/arch/arm/plat-s3c/include/plat/cpu.h
@@ -31,7 +31,7 @@ struct map_desc;
struct cpu_table {
unsigned long idcode;
unsigned long idmask;
- void (*map_io)(void);
+ void (*map_io)(void/*struct map_desc *mach_desc, int size*/);
void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
void (*init_clocks)(int xtal);
int (*init)(void);
@@ -57,6 +57,23 @@ extern void s3c24xx_init_uartdevs(char *name,
struct s3c24xx_uart_resources *res,
struct s3c2410_uartcfg *cfg, int no);
+
+/* the board structure is used at first initialsation time
+ * to get info such as the devices to register for this
+ * board. This is done because platfrom_add_devices() cannot
+ * be called from the map_io entry.
+*/
+
+struct s3c24xx_board {
+ struct platform_device **devices;
+ unsigned int devices_count;
+
+ struct clk **clocks;
+ unsigned int clocks_count;
+};
+
+extern void s3c24xx_set_board(struct s3c24xx_board *board);
+
/* timer for 2410/2440 */
struct sys_timer;
@@ -70,6 +87,7 @@ extern struct sysdev_class s3c2412_sysclass;
extern struct sysdev_class s3c2440_sysclass;
extern struct sysdev_class s3c2442_sysclass;
extern struct sysdev_class s3c2443_sysclass;
+extern struct sysdev_class s3c2450_sysclass;
extern struct sysdev_class s3c6410_sysclass;
extern struct sysdev_class s3c64xx_sysclass;
diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h
index 0f540ea..46fc3dd 100644
--- a/arch/arm/plat-s3c/include/plat/devs.h
+++ b/arch/arm/plat-s3c/include/plat/devs.h
@@ -32,6 +32,7 @@ extern struct platform_device s3c_device_fb;
extern struct platform_device s3c_device_usb;
extern struct platform_device s3c_device_lcd;
extern struct platform_device s3c_device_wdt;
+extern struct platform_device s3c_device_i2c;
extern struct platform_device s3c_device_i2c0;
extern struct platform_device s3c_device_i2c1;
extern struct platform_device s3c_device_rtc;
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h
index 18f9588..4e97a85 100644
--- a/arch/arm/plat-s3c/include/plat/nand.h
+++ b/arch/arm/plat-s3c/include/plat/nand.h
@@ -55,3 +55,8 @@ struct s3c2410_platform_nand {
int chip);
};
+struct s3c_nand_mtd_info {
+ uint chip_nr;
+ uint mtd_part_nr;
+ struct mtd_partition *partition;
+};
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index aa11986..5d4bea7 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -31,6 +31,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
+#include <asm/mach/flash.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
@@ -150,6 +151,60 @@ static struct mtd_partition smdk_default_nand_part[] = {
}
};
+/* ----------------S3C NAND partition information ---------------------*/
+struct mtd_partition s3c_partition_info[] = {
+ {
+ .name = "Bootloader",
+ .offset = 0,
+ .size = (256*SZ_1K),
+ .mask_flags = MTD_CAP_NANDFLASH,
+ },
+ {
+ .name = "Kernel",
+ .offset = (256*SZ_1K), /* Block number is 0x10 */
+ .size = (3*SZ_1M) - (256*SZ_1K),
+ // .mask_flags = MTD_CAP_NANDFLASH,
+ },
+#ifdef CONFIG_SPLIT_ROOT_FILESYSTEM
+ {
+ .name = "File system - YAFFS2",
+ .offset = (3*SZ_1M), /* Block number is 0x80 */
+ .size = (1012*SZ_1M),
+ },
+#endif
+ {
+ .name = "DW_SPECIAL",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 100*SZ_1M,
+ },
+#if 0
+ {
+ .name = "Spare",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+}
+#endif
+};
+
+struct s3c_nand_mtd_info nand_mtd_info = {
+ .chip_nr = 1,
+ .mtd_part_nr = ARRAY_SIZE(s3c_partition_info),
+ .partition = s3c_partition_info,
+};
+
+struct s3c_nand_mtd_info * get_board_nand_mtd_info (void)
+{
+ return &nand_mtd_info;
+}
+
+struct flash_platform_data s3c_onenand_data = {
+ .parts = s3c_partition_info,
+ .nr_parts = ARRAY_SIZE(s3c_partition_info),
+};
+
+
+/* ---------------------------------------------------------------------*/
+
static struct s3c2410_nand_set smdk_nand_sets[] = {
[0] = {
.name = "NAND",
@@ -175,6 +230,7 @@ static struct s3c2410_platform_nand smdk_nand_info = {
static struct platform_device __initdata *smdk_devs[] = {
&s3c_device_nand,
+ &s3c_device_onenand,
&smdk_led4,
&smdk_led5,
&smdk_led6,
@@ -199,6 +255,9 @@ void __init smdk_machine_init(void)
smdk_nand_info.twrph0 = 50;
s3c_device_nand.dev.platform_data = &smdk_nand_info;
+
+ //For s3c nand partition
+ s3c_device_nand.dev.platform_data = &nand_mtd_info;
platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 4af9dd9..743f835 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -53,16 +53,22 @@
#include <plat/s3c2440.h>
#include <plat/s3c2442.h>
#include <plat/s3c2443.h>
-
+#include <plat/s3c2450.h>
/* table of supported CPUs */
static const char name_s3c2400[] = "S3C2400";
static const char name_s3c2410[] = "S3C2410";
static const char name_s3c2412[] = "S3C2412";
+static const char name_s3c2416[] = "S3C2416";
+static const char name_s3c2416a[] = "S3C2416 EVT2";
+static const char name_s3c2416b[] = "S3C2416 EVT3";
static const char name_s3c2440[] = "S3C2440";
static const char name_s3c2442[] = "S3C2442";
static const char name_s3c2442b[] = "S3C2442B";
static const char name_s3c2443[] = "S3C2443";
+static const char name_s3c2450[] = "S3C2450";
+static const char name_s3c2450a[] = "S3C2450 EVT2";
+static const char name_s3c2450b[] = "S3C2450 EVT3";
static const char name_s3c2410a[] = "S3C2410A";
static const char name_s3c2440a[] = "S3C2440A";
@@ -148,6 +154,66 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = s3c2443_init,
.name = name_s3c2443,
},
+ /* TODO */
+#if defined(CONFIG_CPU_S3C2416)
+ { /* same with s3c2450 */
+ .idcode = 0x32450001,
+ .idmask = 0xffffffff,
+ .map_io = s3c2416_map_io,
+ .init_clocks = s3c2416_init_clocks,
+ .init_uarts = s3c2416_init_uarts,
+ .init = s3c2416_init,
+ .name = name_s3c2416,
+ },
+ { /* Evt2 s3c2416 */
+ .idcode = 0x32450002,
+ .idmask = 0xffffffff,
+ .map_io = s3c2416_map_io,
+ .init_clocks = s3c2416_init_clocks,
+ .init_uarts = s3c2416_init_uarts,
+ .init = s3c2416_init,
+ .name = name_s3c2416a,
+ },
+ { /* Evt3 s3c2416 */
+ .idcode = 0x32450003,
+ .idmask = 0xffffffff,
+ .map_io = s3c2416_map_io,
+ .init_clocks = s3c2416_init_clocks,
+ .init_uarts = s3c2416_init_uarts,
+ .init = s3c2416_init,
+ .name = name_s3c2416b,
+ },
+#elif defined(CONFIG_CPU_S3C2450)
+ { /* almost same as s3c2443 */
+ .idcode = 0x32450001,
+ .idmask = 0xffffffff,
+ .map_io = s3c2450_map_io,
+ .init_clocks = s3c2450_init_clocks,
+ .init_uarts = s3c2450_init_uarts,
+ .init = s3c2450_init,
+ .name = name_s3c2450,
+ },
+ { /* Evt2 s3c2450 */
+ .idcode = 0x32450002,
+ .idmask = 0xffffffff,
+ .map_io = s3c2450_map_io,
+ .init_clocks = s3c2450_init_clocks,
+ .init_uarts = s3c2450_init_uarts,
+ .init = s3c2450_init,
+ .name = name_s3c2450a,
+ },
+ { /* Evt3 s3c2450 */
+ .idcode = 0x32450003,
+ .idmask = 0xffffffff,
+ .map_io = s3c2450_map_io,
+ .init_clocks = s3c2450_init_clocks,
+ .init_uarts = s3c2450_init_uarts,
+ .init = s3c2450_init,
+ .name = name_s3c2450b,
+ },
+#endif
+
+
{
.idcode = 0x0, /* S3C2400 doesn't have an idcode */
.idmask = 0xffffffff,
@@ -168,6 +234,55 @@ static struct map_desc s3c_iodesc[] __initdata = {
IODESC_ENT(UART)
};
+static struct cpu_table *
+ s3c_lookup_cpu(unsigned long idcode)
+{
+ struct cpu_table *tab;
+ int count;
+
+ tab = cpu_ids;
+ for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
+ if ((idcode & tab->idmask) == tab->idcode)
+ return tab;
+ }
+
+ return NULL;
+}
+
+/* board information */
+
+static struct s3c24xx_board *board;
+
+void s3c24xx_set_board(struct s3c24xx_board *b)
+{
+ int i;
+
+ board = b;
+
+ if (b->clocks_count != 0) {
+ struct clk **ptr = b->clocks;
+
+ for (i = b->clocks_count; i > 0; i--, ptr++)
+ if (s3c24xx_register_clock(*ptr) < 0)
+ printk(KERN_ERR "failed to register clock.\n");
+ }
+}
+
+/* cpu information */
+
+static struct cpu_table *cpu;
+
+/* For S3C6400 EVT1/S3C6410 */
+static unsigned long s3c64xx_read_idcode_v6(void)
+{
+#if !defined(CONFIG_CPU_S3C6400)
+ return __raw_readl(S3C24XX_VA_SYSCON+0x118);
+#else
+ return 0x36400100;
+#endif
+}
+
+
/* read cpu identificaiton code */
static unsigned long s3c24xx_read_idcode_v5(void)
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index f52a92c..2c0acca 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -39,114 +39,140 @@
/* Serial port registrations */
-static struct resource s3c2410_uart0_resource[] = {
- [0] = {
+static struct resource s3c2410_uart0_resource[] =
+{
+ [0] =
+ {
.start = S3C2410_PA_UART0,
.end = S3C2410_PA_UART0 + 0x3fff,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_S3CUART_RX0,
.end = IRQ_S3CUART_ERR0,
.flags = IORESOURCE_IRQ,
}
};
-static struct resource s3c2410_uart1_resource[] = {
- [0] = {
+static struct resource s3c2410_uart1_resource[] =
+{
+ [0] =
+ {
.start = S3C2410_PA_UART1,
.end = S3C2410_PA_UART1 + 0x3fff,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_S3CUART_RX1,
.end = IRQ_S3CUART_ERR1,
.flags = IORESOURCE_IRQ,
}
};
-static struct resource s3c2410_uart2_resource[] = {
- [0] = {
+static struct resource s3c2410_uart2_resource[] =
+{
+ [0] =
+ {
.start = S3C2410_PA_UART2,
.end = S3C2410_PA_UART2 + 0x3fff,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_S3CUART_RX2,
.end = IRQ_S3CUART_ERR2,
.flags = IORESOURCE_IRQ,
}
};
-static struct resource s3c2410_uart3_resource[] = {
- [0] = {
+static struct resource s3c2410_uart3_resource[] =
+{
+ [0] =
+ {
.start = S3C2443_PA_UART3,
.end = S3C2443_PA_UART3 + 0x3fff,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_S3CUART_RX3,
.end = IRQ_S3CUART_ERR3,
.flags = IORESOURCE_IRQ,
},
};
-struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
- [0] = {
+struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata =
+{
+ [0] =
+ {
.resources = s3c2410_uart0_resource,
- .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
+ .nr_resources = ARRAY_SIZE ( s3c2410_uart0_resource ),
},
- [1] = {
+ [1] =
+ {
.resources = s3c2410_uart1_resource,
- .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
+ .nr_resources = ARRAY_SIZE ( s3c2410_uart1_resource ),
},
- [2] = {
+ [2] =
+ {
.resources = s3c2410_uart2_resource,
- .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
+ .nr_resources = ARRAY_SIZE ( s3c2410_uart2_resource ),
},
- [3] = {
+ [3] =
+ {
.resources = s3c2410_uart3_resource,
- .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
+ .nr_resources = ARRAY_SIZE ( s3c2410_uart3_resource ),
},
};
/* yart devices */
-static struct platform_device s3c24xx_uart_device0 = {
+static struct platform_device s3c24xx_uart_device0 =
+{
.id = 0,
-};
+ };
-static struct platform_device s3c24xx_uart_device1 = {
+static struct platform_device s3c24xx_uart_device1 =
+{
.id = 1,
-};
+ };
-static struct platform_device s3c24xx_uart_device2 = {
+static struct platform_device s3c24xx_uart_device2 =
+{
.id = 2,
-};
+ };
-static struct platform_device s3c24xx_uart_device3 = {
+static struct platform_device s3c24xx_uart_device3 =
+{
.id = 3,
-};
+ };
-struct platform_device *s3c24xx_uart_src[4] = {
+struct platform_device *s3c24xx_uart_src[4] =
+{
&s3c24xx_uart_device0,
&s3c24xx_uart_device1,
&s3c24xx_uart_device2,
&s3c24xx_uart_device3,
};
-struct platform_device *s3c24xx_uart_devs[4] = {
+struct platform_device *s3c24xx_uart_devs[4] =
+{
};
/* LCD Controller */
-static struct resource s3c_lcd_resource[] = {
- [0] = {
+static struct resource s3c_lcd_resource[] =
+{
+ [0] =
+ {
.start = S3C24XX_PA_LCD,
.end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_LCD,
.end = IRQ_LCD,
.flags = IORESOURCE_IRQ,
@@ -156,41 +182,90 @@ static struct resource s3c_lcd_resource[] = {
static u64 s3c_device_lcd_dmamask = 0xffffffffUL;
-struct platform_device s3c_device_lcd = {
+struct platform_device s3c_device_lcd =
+{
.name = "s3c2410-lcd",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_lcd_resource),
- .resource = s3c_lcd_resource,
- .dev = {
+ .id = -1,
+ .num_resources = ARRAY_SIZE ( s3c_lcd_resource ),
+ .resource = s3c_lcd_resource,
+ .dev =
+ {
.dma_mask = &s3c_device_lcd_dmamask,
.coherent_dma_mask = 0xffffffffUL
}
};
-EXPORT_SYMBOL(s3c_device_lcd);
+EXPORT_SYMBOL ( s3c_device_lcd );
-void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
+void __init s3c24xx_fb_set_platdata ( struct s3c2410fb_mach_info *pd )
{
struct s3c2410fb_mach_info *npd;
- npd = kmalloc(sizeof(*npd), GFP_KERNEL);
- if (npd) {
- memcpy(npd, pd, sizeof(*npd));
+ npd = kmalloc ( sizeof ( *npd ), GFP_KERNEL );
+ if ( npd )
+ {
+ memcpy ( npd, pd, sizeof ( *npd ) );
s3c_device_lcd.dev.platform_data = npd;
- } else {
- printk(KERN_ERR "no memory for LCD platform data\n");
+ }
+ else
+ {
+ printk ( KERN_ERR "no memory for LCD platform data\n" );
}
}
+// /* NAND Controller */
+//
+// static struct resource s3c_nand_resource[] = {
+// [0] = {
+// .start = S3C24XX_PA_NAND,
+// .end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,
+// .flags = IORESOURCE_MEM,
+// }
+// };
+//
+// struct platform_device s3c_device_nand = {
+// .name = "s3c2410-nand",
+// .id = -1,
+// .num_resources = ARRAY_SIZE(s3c_nand_resource),
+// .resource = s3c_nand_resource,
+// };
+//
+// EXPORT_SYMBOL(s3c_device_nand);
+
+/* OneNAND Controller */
+static struct resource s3c_onenand_resource[] = {
+ [0] = {
+ .start = S3C6400_PA_ONENAND,
+ .end = S3C6400_PA_ONENAND + S3C_SZ_ONENAND - 1,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+struct platform_device s3c_device_onenand = {
+ .name = "onenand",
+ .id = -1,
+ .dev = {
+ .platform_data = &s3c_onenand_data,
+ },
+ .num_resources = ARRAY_SIZE(s3c_onenand_resource),
+ .resource = s3c_onenand_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_onenand);
+
+
/* USB Device (Gadget)*/
-static struct resource s3c_usbgadget_resource[] = {
- [0] = {
+static struct resource s3c_usbgadget_resource[] =
+{
+ [0] =
+ {
.start = S3C24XX_PA_USBDEV,
.end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_USBD,
.end = IRQ_USBD,
.flags = IORESOURCE_IRQ,
@@ -198,122 +273,216 @@ static struct resource s3c_usbgadget_resource[] = {
};
-struct platform_device s3c_device_usbgadget = {
+struct platform_device s3c_device_usbgadget =
+{
.name = "s3c2410-usbgadget",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
- .resource = s3c_usbgadget_resource,
-};
+ .id = -1,
+ .num_resources = ARRAY_SIZE ( s3c_usbgadget_resource ),
+ .resource = s3c_usbgadget_resource,
+ };
-EXPORT_SYMBOL(s3c_device_usbgadget);
+EXPORT_SYMBOL ( s3c_device_usbgadget );
-void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
+void __init s3c24xx_udc_set_platdata ( struct s3c2410_udc_mach_info *pd )
{
struct s3c2410_udc_mach_info *npd;
- npd = kmalloc(sizeof(*npd), GFP_KERNEL);
- if (npd) {
- memcpy(npd, pd, sizeof(*npd));
+ npd = kmalloc ( sizeof ( *npd ), GFP_KERNEL );
+ if ( npd )
+ {
+ memcpy ( npd, pd, sizeof ( *npd ) );
s3c_device_usbgadget.dev.platform_data = npd;
- } else {
- printk(KERN_ERR "no memory for udc platform data\n");
+ }
+ else
+ {
+ printk ( KERN_ERR "no memory for udc platform data\n" );
}
}
/* Watchdog */
-static struct resource s3c_wdt_resource[] = {
- [0] = {
+static struct resource s3c_wdt_resource[] =
+{
+ [0] =
+ {
.start = S3C24XX_PA_WATCHDOG,
.end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1,
.flags = IORESOURCE_MEM,
},
- [1] = {
- .start = IRQ_WDT,
- .end = IRQ_WDT,
- .flags = IORESOURCE_IRQ,
- }
+#if defined (CONFIG_CPU_S3C2443)|| defined (CONFIG_CPU_S3C2450) || defined (CONFIG_CPU_S3C2416)
+ [1] = {
+ .start = IRQ_S3C2443_WDT,
+ .end = IRQ_S3C2443_WDT,
+ .flags = IORESOURCE_IRQ,
+ }
+
+#else
+ [1] = {
+ .start = IRQ_WDT,
+ .end = IRQ_WDT,
+ .flags = IORESOURCE_IRQ,
+ }
+#endif
+
};
-struct platform_device s3c_device_wdt = {
+struct platform_device s3c_device_wdt =
+{
.name = "s3c2410-wdt",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_wdt_resource),
- .resource = s3c_wdt_resource,
+ .id = -1,
+ .num_resources = ARRAY_SIZE ( s3c_wdt_resource ),
+ .resource = s3c_wdt_resource,
+ };
+
+EXPORT_SYMBOL ( s3c_device_wdt );
+
+
+/* I2C */
+
+static struct resource s3c_i2c_resource[] =
+{
+ [0] =
+ {
+ .start = S3C24XX_PA_IIC,
+ .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] =
+ {
+ .start = IRQ_IIC,
+ .end = IRQ_IIC,
+ .flags = IORESOURCE_IRQ,
+ }
};
-EXPORT_SYMBOL(s3c_device_wdt);
+struct platform_device s3c_device_i2c =
+{
+ .name = "s3c2410-i2c",
+ .id = -1,
+ .num_resources = ARRAY_SIZE ( s3c_i2c_resource ),
+ .resource = s3c_i2c_resource,
+ };
+
+EXPORT_SYMBOL ( s3c_device_i2c );
/* IIS */
-static struct resource s3c_iis_resource[] = {
- [0] = {
+static struct resource s3c_iis_resource[] =
+{
+ [0] =
+ {
.start = S3C24XX_PA_IIS,
.end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1,
.flags = IORESOURCE_MEM,
- }
+ },
+#ifdef CONFIG_CPU_S3C6410
+ [1] = {
+ .start = IRQ_IIS,
+ .end = IRQ_IIS,
+ .flags = IORESOURCE_IRQ,
+ }
+#endif
+
+
};
static u64 s3c_device_iis_dmamask = 0xffffffffUL;
-struct platform_device s3c_device_iis = {
+struct platform_device s3c_device_iis =
+{
.name = "s3c2410-iis",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_iis_resource),
- .resource = s3c_iis_resource,
- .dev = {
+ .id = -1,
+ .num_resources = ARRAY_SIZE ( s3c_iis_resource ),
+ .resource = s3c_iis_resource,
+ .dev =
+ {
.dma_mask = &s3c_device_iis_dmamask,
.coherent_dma_mask = 0xffffffffUL
}
};
-EXPORT_SYMBOL(s3c_device_iis);
+EXPORT_SYMBOL ( s3c_device_iis );
+
+/* IIS v4.0 multi channel */
+
+static struct resource s3c_iis_v40_resource[] = {
+ [0] = {
+ .start = S3C6410_PA_IIS_V40,
+ .end = S3C6410_PA_IIS_V40 + S3C24XX_SZ_IIS -1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static u64 s3c_device_iis_v40_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_iis_v40 = {
+ .name = "s3c-i2s-v40",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_iis_v40_resource),
+ .resource = s3c_iis_v40_resource,
+ .dev = {
+ .dma_mask = &s3c_device_iis_v40_dmamask,
+ .coherent_dma_mask = 0xffffffffUL
+ }
+};
+
+EXPORT_SYMBOL(s3c_device_iis_v40);
+
/* RTC */
-static struct resource s3c_rtc_resource[] = {
- [0] = {
+static struct resource s3c_rtc_resource[] =
+{
+ [0] =
+ {
.start = S3C24XX_PA_RTC,
.end = S3C24XX_PA_RTC + 0xff,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_RTC,
.end = IRQ_RTC,
.flags = IORESOURCE_IRQ,
},
- [2] = {
+ [2] =
+ {
.start = IRQ_TICK,
.end = IRQ_TICK,
.flags = IORESOURCE_IRQ
}
};
-struct platform_device s3c_device_rtc = {
+struct platform_device s3c_device_rtc =
+{
.name = "s3c2410-rtc",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_rtc_resource),
- .resource = s3c_rtc_resource,
-};
+ .id = -1,
+ .num_resources = ARRAY_SIZE ( s3c_rtc_resource ),
+ .resource = s3c_rtc_resource,
+ };
-EXPORT_SYMBOL(s3c_device_rtc);
+EXPORT_SYMBOL ( s3c_device_rtc );
/* ADC */
-static struct resource s3c_adc_resource[] = {
- [0] = {
+static struct resource s3c_adc_resource[] =
+{
+ [0] =
+ {
.start = S3C24XX_PA_ADC,
.end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_TC,
.end = IRQ_TC,
.flags = IORESOURCE_IRQ,
},
- [2] = {
+ [2] =
+ {
.start = IRQ_ADC,
.end = IRQ_ADC,
.flags = IORESOURCE_IRQ,
@@ -321,30 +490,35 @@ static struct resource s3c_adc_resource[] = {
};
-struct platform_device s3c_device_adc = {
+struct platform_device s3c_device_adc =
+{
.name = "s3c24xx-adc",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_adc_resource),
- .resource = s3c_adc_resource,
-};
+ .id = -1,
+ .num_resources = ARRAY_SIZE ( s3c_adc_resource ),
+ .resource = s3c_adc_resource,
+ };
/* HWMON */
-struct platform_device s3c_device_hwmon = {
+struct platform_device s3c_device_hwmon =
+{
.name = "s3c-hwmon",
- .id = -1,
- .dev.parent = &s3c_device_adc.dev,
-};
+ .id = -1,
+ .dev.parent = &s3c_device_adc.dev,
+ };
/* SDI */
-static struct resource s3c_sdi_resource[] = {
- [0] = {
+static struct resource s3c_sdi_resource[] =
+{
+ [0] =
+ {
.start = S3C24XX_PA_SDI,
.end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_SDI,
.end = IRQ_SDI,
.flags = IORESOURCE_IRQ,
@@ -352,24 +526,84 @@ static struct resource s3c_sdi_resource[] = {
};
-struct platform_device s3c_device_sdi = {
+struct platform_device s3c_device_sdi =
+{
.name = "s3c2410-sdi",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_sdi_resource),
- .resource = s3c_sdi_resource,
-};
+ .id = -1,
+ .num_resources = ARRAY_SIZE ( s3c_sdi_resource ),
+ .resource = s3c_sdi_resource,
+ };
-EXPORT_SYMBOL(s3c_device_sdi);
+EXPORT_SYMBOL ( s3c_device_sdi );
/* SPI (0) */
+#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
static struct resource s3c_spi0_resource[] = {
- [0] = {
+ [0] = {
+ .start = S3C_PA_SPI_0,
+ .end = S3C_PA_SPI_0 + S3C_SZ_SPI_0,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_SPI0,
+ .end = IRQ_SPI0,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_spi0 = {
+ .name = "s3c2410-spi",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(s3c_spi0_resource),
+ .resource = s3c_spi0_resource,
+ .dev = {
+ .dma_mask = &s3c_device_spi0_dmamask,
+ .coherent_dma_mask = 0xffffffffUL
+ }
+};
+
+EXPORT_SYMBOL(s3c_device_spi0);
+
+static struct resource s3c_spi1_resource[] = {
+ [0] = {
+ .start = S3C_PA_SPI_0,
+ .end = S3C_PA_SPI_0 + S3C_SZ_SPI_0,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_SPI1,
+ .end = IRQ_SPI1,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+struct platform_device s3c_device_spi1 = {
+ .name = "s3c-spi",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(s3c_spi1_resource),
+ .resource = s3c_spi1_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_spi1);
+
+#else
+
+
+static struct resource s3c_spi0_resource[] =
+{
+ [0] =
+ {
.start = S3C24XX_PA_SPI,
.end = S3C24XX_PA_SPI + 0x1f,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_SPI0,
.end = IRQ_SPI0,
.flags = IORESOURCE_IRQ,
@@ -379,28 +613,33 @@ static struct resource s3c_spi0_resource[] = {
static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
-struct platform_device s3c_device_spi0 = {
+struct platform_device s3c_device_spi0 =
+{
.name = "s3c2410-spi",
- .id = 0,
- .num_resources = ARRAY_SIZE(s3c_spi0_resource),
- .resource = s3c_spi0_resource,
- .dev = {
- .dma_mask = &s3c_device_spi0_dmamask,
- .coherent_dma_mask = 0xffffffffUL
- }
+ .id = 0,
+ .num_resources = ARRAY_SIZE ( s3c_spi0_resource ),
+ .resource = s3c_spi0_resource,
+ .dev =
+ {
+ .dma_mask = &s3c_device_spi0_dmamask,
+ .coherent_dma_mask = 0xffffffffUL
+ }
};
-EXPORT_SYMBOL(s3c_device_spi0);
+EXPORT_SYMBOL ( s3c_device_spi0 );
/* SPI (1) */
-static struct resource s3c_spi1_resource[] = {
- [0] = {
+static struct resource s3c_spi1_resource[] =
+{
+ [0] =
+ {
.start = S3C24XX_PA_SPI + S3C2410_SPI1,
.end = S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_SPI1,
.end = IRQ_SPI1,
.flags = IORESOURCE_IRQ,
@@ -410,30 +649,35 @@ static struct resource s3c_spi1_resource[] = {
static u64 s3c_device_spi1_dmamask = 0xffffffffUL;
-struct platform_device s3c_device_spi1 = {
+struct platform_device s3c_device_spi1 =
+{
.name = "s3c2410-spi",
- .id = 1,
- .num_resources = ARRAY_SIZE(s3c_spi1_resource),
- .resource = s3c_spi1_resource,
- .dev = {
- .dma_mask = &s3c_device_spi1_dmamask,
- .coherent_dma_mask = 0xffffffffUL
- }
+ .id = 1,
+ .num_resources = ARRAY_SIZE ( s3c_spi1_resource ),
+ .resource = s3c_spi1_resource,
+ .dev =
+ {
+ .dma_mask = &s3c_device_spi1_dmamask,
+ .coherent_dma_mask = 0xffffffffUL
+ }
};
-EXPORT_SYMBOL(s3c_device_spi1);
-
-#ifdef CONFIG_CPU_S3C2440
+EXPORT_SYMBOL ( s3c_device_spi1 );
+#endif
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
/* Camif Controller */
-static struct resource s3c_camif_resource[] = {
- [0] = {
+static struct resource s3c_camif_resource[] =
+{
+ [0] =
+ {
.start = S3C2440_PA_CAMIF,
.end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_CAM,
.end = IRQ_CAM,
.flags = IORESOURCE_IRQ,
@@ -443,45 +687,188 @@ static struct resource s3c_camif_resource[] = {
static u64 s3c_device_camif_dmamask = 0xffffffffUL;
-struct platform_device s3c_device_camif = {
+struct platform_device s3c_device_camif =
+{
.name = "s3c2440-camif",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_camif_resource),
- .resource = s3c_camif_resource,
- .dev = {
+ .id = -1,
+ .num_resources = ARRAY_SIZE ( s3c_camif_resource ),
+ .resource = s3c_camif_resource,
+ .dev =
+ {
.dma_mask = &s3c_device_camif_dmamask,
.coherent_dma_mask = 0xffffffffUL
}
};
-EXPORT_SYMBOL(s3c_device_camif);
+EXPORT_SYMBOL ( s3c_device_camif );
+
+
+
+static struct resource s3c_ide_resource[] =
+{
+ [0] =
+ {
+ .start = S3C_PA_CFATA,
+ .end = S3C_PA_CFATA+ S3C_SZ_CFATA,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] =
+ {
+ .start = IRQ_CFCON,
+ .end = IRQ_CFCON,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device s3c_device_ide =
+{
+ .name = "s3c-ide",
+ .id = 0,
+ .num_resources = ARRAY_SIZE ( s3c_ide_resource ),
+ .resource = s3c_ide_resource,
+ };
+
+EXPORT_SYMBOL ( s3c_device_ide );
+
+#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
+/* HS-MMC Controller */
+extern struct s3c_hsmmc_cfg s3c_hsmmc0_platform;
+extern struct s3c_hsmmc_cfg s3c_hsmmc1_platform;
+
+/* cpu board ver0.1 changes detection scheme. */
+static struct resource s3c_hsmmc0_resource[] =
+{
+ [0] =
+ {
+ .start = S3C_PA_HSMMC+0x400000,
+ .end = S3C_PA_HSMMC+0x400000+S3C_SZ_HSMMC,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] =
+ {
+ .start = IRQ_SDI_0,
+ .end = IRQ_SDI_0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource s3c_hsmmc1_resource[] =
+{
+ [0] =
+ {
+ .start = S3C_PA_HSMMC,
+ .end = S3C_PA_HSMMC+S3C_SZ_HSMMC,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] =
+ {
+ .start = IRQ_SDI_1,
+ .end = IRQ_SDI_1,
+ .flags = IORESOURCE_IRQ,
+ },
+ /* To detect a card inserted, use an external interrupt */
+ [2] =
+ {
+ .start = IRQ_EINT1,
+ .end = IRQ_EINT1,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device s3c_device_hsmmc0 =
+{
+ .name = "s3c-hsmmc",
+ .id = 0,
+ .num_resources = ARRAY_SIZE ( s3c_hsmmc0_resource ),
+ .resource = s3c_hsmmc0_resource,
+ .dev =
+ {
+ .platform_data = &s3c_hsmmc0_platform,
+ }
+};
+
+struct platform_device s3c_device_hsmmc1 =
+{
+ .name = "s3c-hsmmc",
+ .id = 1,
+ .num_resources = ARRAY_SIZE ( s3c_hsmmc1_resource ),
+ .resource = s3c_hsmmc1_resource,
+ .dev =
+ {
+ .platform_data = &s3c_hsmmc1_platform,
+ }
+};
+
+EXPORT_SYMBOL ( s3c_device_hsmmc0 );
+EXPORT_SYMBOL ( s3c_device_hsmmc1 );
+
+#else
+/* HS-MMC controller */
+extern struct s3c_hsmmc_cfg s3c_hsmmc_platform;
+
+static struct resource s3c_hsmmc_resource[] =
+{
+ [0] =
+ {
+ .start = S3C_PA_HSMMC,
+ .end = S3C_PA_HSMMC+ S3C_SZ_HSMMC,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] =
+ {
+ .start = IRQ_SDI_1,
+ .end = IRQ_SDI_1,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device s3c_device_hsmmc =
+{
+ .name = "s3c-hsmmc",
+ .id = 0,
+ .num_resources = ARRAY_SIZE ( s3c_hsmmc_resource ),
+ .resource = s3c_hsmmc_resource,
+ .dev =
+ {
+ .platform_data = &s3c_hsmmc_platform,
+ }
+};
+
+EXPORT_SYMBOL ( s3c_device_hsmmc );
+#endif
/* AC97 */
-static struct resource s3c_ac97_resource[] = {
- [0] = {
+static struct resource s3c_ac97_resource[] =
+{
+ [0] =
+ {
.start = S3C2440_PA_AC97,
.end = S3C2440_PA_AC97 + S3C2440_SZ_AC97 -1,
.flags = IORESOURCE_MEM,
},
- [1] = {
+ [1] =
+ {
.start = IRQ_S3C244x_AC97,
.end = IRQ_S3C244x_AC97,
.flags = IORESOURCE_IRQ,
},
- [2] = {
+ [2] =
+ {
.name = "PCM out",
.start = DMACH_PCM_OUT,
.end = DMACH_PCM_OUT,
.flags = IORESOURCE_DMA,
},
- [3] = {
+ [3] =
+ {
.name = "PCM in",
.start = DMACH_PCM_IN,
.end = DMACH_PCM_IN,
.flags = IORESOURCE_DMA,
},
- [4] = {
+ [4] =
+ {
.name = "Mic in",
.start = DMACH_MIC_IN,
.end = DMACH_MIC_IN,
@@ -491,17 +878,49 @@ static struct resource s3c_ac97_resource[] = {
static u64 s3c_device_ac97_dmamask = 0xffffffffUL;
-struct platform_device s3c_device_ac97 = {
+struct platform_device s3c_device_ac97 =
+{
.name = "s3c-ac97",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_ac97_resource),
- .resource = s3c_ac97_resource,
- .dev = {
+ .id = -1,
+ .num_resources = ARRAY_SIZE ( s3c_ac97_resource ),
+ .resource = s3c_ac97_resource,
+ .dev =
+ {
.dma_mask = &s3c_device_ac97_dmamask,
.coherent_dma_mask = 0xffffffffUL
}
};
-EXPORT_SYMBOL(s3c_device_ac97);
+EXPORT_SYMBOL ( s3c_device_ac97 );
+#if defined (CONFIG_CPU_S3C6410) || defined (CONFIG_CPU_S3C2450)
+static struct resource s3c_smc911x_resources[] =
+{
+ [0] =
+ {
+ .start = S3C_PA_SMC9115,
+ .end = S3C_PA_SMC9115 + 0x1fffffff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] =
+ {
+#if defined(CONFIG_CPU_S3C6410)
+ .start = IRQ_EINT10,
+ .end = IRQ_EINT10,
+#elif defined(CONFIG_CPU_S3C2450)
+ .start = IRQ_EINT4,
+ .end = IRQ_EINT4,
+#endif
+ .flags = IORESOURCE_IRQ,
+ },
+};
+struct platform_device s3c_device_smc911x =
+{
+ .name = "smc911x",
+ .id = -1,
+ .num_resources = ARRAY_SIZE ( s3c_smc911x_resources ),
+ .resource = s3c_smc911x_resources,
+ };
+EXPORT_SYMBOL ( s3c_device_smc911x );
+#endif
#endif // CONFIG_CPU_S32440
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index f046f8c..0c72e4f 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1338,7 +1338,16 @@ int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
/* dma channel irqs are in order.. */
cp->number = channel;
- cp->irq = channel + irq;
+#if defined(CONFIG_CPU_S3C2450)|| defined(CONFIG_CPU_S3C2416)
+ if(channel == 6){
+ irq = irq + 5;
+ cp->irq = channel + irq;
+ }
+ else
+ cp->irq = channel + irq;
+#else
+ cp->irq = channel + irq;
+#endif
cp->regs = dma_base + (channel * stride);
/* point current stats somewhere */
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index 5467470..5af0b6f 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -101,6 +101,27 @@ unsigned int s3c2410_gpio_getcfg(unsigned int pin)
EXPORT_SYMBOL(s3c2410_gpio_getcfg);
+#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
+void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
+{
+ void __iomem *base = S3C24XX_GPIO_BASE(pin);
+ unsigned long offs = S3C2410_GPIO_OFFSET(pin)*2;
+ unsigned long flags;
+ unsigned long up;
+
+ if (pin < S3C2410_GPIO_BANKB)
+ return;
+
+ local_irq_save(flags);
+
+ up = __raw_readl(base + 0x08);
+ up &= ~(0x3 << offs);
+ up |= to << offs;
+ __raw_writel(up, base + 0x08);
+
+ local_irq_restore(flags);
+}
+#else
void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
{
void __iomem *base = S3C24XX_GPIO_BASE(pin);
@@ -120,7 +141,7 @@ void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
local_irq_restore(flags);
}
-
+#endif
EXPORT_SYMBOL(s3c2410_gpio_pullup);
int s3c2410_gpio_getpull(unsigned int pin)
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
index c4d1334..246f27c 100644
--- a/arch/arm/plat-s3c24xx/include/plat/map.h
+++ b/arch/arm/plat-s3c24xx/include/plat/map.h
@@ -13,66 +13,288 @@
#ifndef __ASM_PLAT_S3C24XX_MAP_H
#define __ASM_PLAT_S3C24XX_MAP_H
+#ifndef __ASSEMBLY__
+#define S3C2410_ADDR(x) ((void __iomem __force *)0xF0000000 + (x))
+#else
+#define S3C2410_ADDR(x) (0xF0000000 + (x))
+#endif
+
+#define S3C2400_ADDR(x) S3C2410_ADDR(x)
+
/* interrupt controller is the first thing we put in, to make
* the assembly code for the irq detection easier
*/
-#define S3C24XX_VA_IRQ S3C_VA_IRQ
+#define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000)
+#define S3C2400_PA_IRQ (0x14400000)
#define S3C2410_PA_IRQ (0x4A000000)
-#define S3C24XX_SZ_IRQ SZ_1M
+#define S3C6400_PA_IRQ (0x71200000)
+#define S3C24XX_SZ_IRQ SZ_2M
+
/* memory controller registers */
-#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
+#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00800000)
+#define S3C2400_PA_MEMCTRL (0x14000000)
#define S3C2410_PA_MEMCTRL (0x48000000)
#define S3C24XX_SZ_MEMCTRL SZ_1M
+/* USB host controller */
+#define S3C2400_PA_USBHOST (0x14200000)
+#define S3C2410_PA_USBHOST (0x49000000)
+#define S3C6400_PA_USBHOST (0x74300000)
+#define S3C24XX_SZ_USBHOST SZ_1M
+
+/* DMA controller */
+#define S3C2400_PA_DMA (0x14600000)
+#define S3C2410_PA_DMA (0x4B000000)
+#define S3C6400_PA_DMA (0x75000000)
+#define S3C24XX_SZ_DMA SZ_1M
+
+/* Clock and Power management */
+#define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000)
+#define S3C2400_PA_CLKPWR (0x14800000)
+#define S3C2410_PA_CLKPWR (0x4C000000)
+#define S3C24XX_SZ_CLKPWR SZ_1M
+
+/* LCD controller */
+#define S3C24XX_VA_LCD S3C2410_ADDR(0x00300000)
+#define S3C2400_PA_LCD (0x14A00000)
+#define S3C2410_PA_LCD (0x4D000000)
+#define S3C2443_PA_LCD (0x4C800000)
+#define S3C6400_PA_LCD (0x77100000)
+#define S3C24XX_SZ_LCD SZ_1M
+
+ /* NAND flash controller */
+#define S3C2410_PA_NAND (0x4E000000)
+#define S3C6400_PA_NAND (0x70200000)
+#define S3C24XX_SZ_NAND SZ_1M
+
+ /* MMC controller - available on the S3C2400 */
+#define S3C2400_PA_MMC (0x15A00000)
+#define S3C2400_SZ_MMC SZ_1M
+
+ /* HS-MMC controller - available on the S3C2443/S3C6400 */
+#define S3C2443_PA_HSMMC (0x4A800000)
+#define S3C6400_PA_HSMMC (0x7C200000)
+#define S3C_SZ_HSMMC SZ_4K
+
+ /* CF/ATA controller - available on the S3C2443/S3C6400 */
+#define S3C2443_PA_CFATA (0x4B800000)
+#define S3C6400_PA_CFATA (0x70300000)
+#define S3C_SZ_CFATA SZ_8K
+
/* UARTs */
-#define S3C24XX_VA_UART S3C_VA_UART
+#define S3C24XX_VA_UART S3C2410_ADDR(0x00400000)
+#define S3C2400_PA_UART (0x15000000)
#define S3C2410_PA_UART (0x50000000)
+#define S3C6400_PA_UART (0x7F005000)
#define S3C24XX_SZ_UART SZ_1M
#define S3C_UART_OFFSET (0x4000)
#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
/* Timers */
-#define S3C24XX_VA_TIMER S3C_VA_TIMER
+#define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000)
+#define S3C2400_PA_TIMER (0x15100000)
#define S3C2410_PA_TIMER (0x51000000)
+#define S3C6400_PA_TIMER (0x7F006000)
#define S3C24XX_SZ_TIMER SZ_1M
-/* Clock and Power management */
-#define S3C24XX_VA_CLKPWR S3C_VA_SYS
-#define S3C24XX_SZ_CLKPWR SZ_1M
-
/* USB Device port */
+#define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00600000)
+#define S3C2400_PA_USBDEV (0x15200140)
#define S3C2410_PA_USBDEV (0x52000000)
+#define S3C2443_PA_USBDEV (0x49800000)
#define S3C24XX_SZ_USBDEV SZ_1M
/* Watchdog */
-#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
+#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)
+#define S3C2400_PA_WATCHDOG (0x15300000)
#define S3C2410_PA_WATCHDOG (0x53000000)
-#define S3C24XX_SZ_WATCHDOG SZ_1M
-
-/* Standard size definitions for peripheral blocks. */
-
-#define S3C24XX_SZ_IIS SZ_1M
-#define S3C24XX_SZ_ADC SZ_1M
-#define S3C24XX_SZ_SPI SZ_1M
-#define S3C24XX_SZ_SDI SZ_1M
-#define S3C24XX_SZ_NAND SZ_1M
-
-/* GPIO ports */
+#define S3C6400_PA_WATCHDOG (0x7E004000)
+#define S3C24XX_SZ_WATCHDOG SZ_4K
+
+ /* IIC hardware controller */
+#define S3C2400_PA_IIC (0x15400000)
+#define S3C2410_PA_IIC (0x54000000)
+#define S3C6400_PA_IIC (0x7F004000)
+#define S3C24XX_SZ_IIC SZ_4K
+
+ /* IIS controller */
+#define S3C24XX_VA_IIS S3C2410_ADDR(0x00900000)
+#define S3C2400_PA_IIS (0x15508000)
+#define S3C2410_PA_IIS (0x55000000)
+#define S3C2450_PA_IIS_1 (0x55000100)
+#define S3C6400_PA_IIS (0x7F002000)
+#define S3C6410_PA_IIS (0x7F002000)
+#define S3C6410_PA_IIS_V40 (0x7F00D000)
+#define S3C24XX_SZ_IIS SZ_4K
+
+ /* PCM I/F controller */
+#define S3C6410_PA_PCM_PORT0 (0x7F009000)
+#define S3C6410_PA_PCM_PORT1 (0x7F00A000)
+
+ /* GPIO ports */
/* the calculation for the VA of this must ensure that
- * it is the same distance apart from the UART in the
- * phsyical address space, as the initial mapping for the IO
- * is done as a 1:1 maping. This puts it (currently) at
- * 0xFA800000, which is not in the way of any current mapping
- * by the base system.
+ * it is the same distance apart from the UART in the
+ * phsyical address space, as the initial mapping for the IO
+ * is done as a 1:1 maping. This puts it (currently) at
+ * 0xF6800000, which is not in the way of any current mapping
+ * by the base system.
*/
-
+#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
+#define S3C2400_PA_GPIO (0x15600000)
#define S3C2410_PA_GPIO (0x56000000)
-#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
+#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
#define S3C24XX_SZ_GPIO SZ_1M
+#else
+ /* GPIO */
+#define S3C24XX_VA_GPIO S3C2410_ADDR(0x03100000)
+#define S3C6400_PA_GPIO (0x7F008000)
+#define S3C24XX_SZ_GPIO SZ_4K
+#endif
+
+ /* RTC */
+#define S3C2400_PA_RTC (0x15700040)
+#define S3C2410_PA_RTC (0x57000000)
+#define S3C2450_PA_RTC (0x57005000)
+#define S3C6400_PA_RTC (0x7E005000)
+#define S3C24XX_SZ_RTC SZ_4K
+
+ /* ADC */
+#define S3C2400_PA_ADC (0x15800000)
+#define S3C2410_PA_ADC (0x58000000)
+#define S3C6400_PA_ADC (0x7E00B000)
+#define S3C24XX_SZ_ADC SZ_4K
+
+ /* SPI */
+#define S3C2400_PA_SPI (0x15900000)
+#define S3C2410_PA_SPI (0x59000000)
+#define S3C6400_PA_SPI (0x7F00B000)
+#define S3C24XX_SZ_SPI SZ_4K
+
+ /* SDI */
+#define S3C2410_PA_SDI (0x5A000000)
+#define S3C24XX_SZ_SDI SZ_1M
+
+ /* CAMIF */
+#define S3C24XX_VA_CAMIF S3C2410_ADDR(0x00A00000)
+#define S3C2440_PA_CAMIF (0x4F000000)
+#define S3C2443_PA_CAMIF (0x4D800000)
+#define S3C6400_PA_CAMIF (0x78000000)
+#define S3C2440_SZ_CAMIF SZ_1M
+#define S3C2443_SZ_CAMIF SZ_1M
+#define S3C24XX_SZ_CAMIF SZ_1M
+
+ /* AC97 */
+#define S3C24XX_VA_AC97 S3C2410_ADDR(0x00F00000)
+#define S3C2440_PA_AC97 (0x5B000000)
+#define S3C6400_PA_AC97 (0x7F001000)
+#define S3C2440_SZ_AC97 SZ_1M
+#define S3C24XX_SZ_AC97 SZ_4K
+
+ /* Host I/F Indirect & Direct */
+#define S3C24XX_VA_HOSTIFA S3C2410_ADDR(0x00B00000)
+#define S3C24XX_PA_HOSTIFA (0x74000000)
+#define S3C24XX_SZ_HOSTIFA SZ_1M
+
+#define S3C24XX_VA_HOSTIFB S3C2410_ADDR(0x00C00000)
+#define S3C24XX_PA_HOSTIFB (0x74100000)
+#define S3C24XX_SZ_HOSTIFB SZ_1M
+
+ /* System Controller */
+#define S3C24XX_VA_SYSCON S3C2410_ADDR(0x02900000)
+#define S3C24XX_PA_SYSCON (0x7E00F000)
+#define S3C24XX_SZ_SYSCON SZ_4K
+
+ /* AXI */
+#define S3C6410_PA_AXI_SYS (0x7E003000)
+#define S3C6410_PA_AXI_PERI (0x7E008000)
+#define S3C6410_PA_AXI_SFR (0x7E009000)
+
+ /* Ethernet */
+#define S3C24XX_VA_CS8900 S3C2410_ADDR(0x03600000)
+#define S3C2443_PA_CS8900 (0x09000000)
+#define S3C6400_PA_CS8900 (0x18800000)
+#define S3C24XX_SZ_CS8900 SZ_1M
+
+#define S3C6410_PA_SMC9115 (0x18000000)
+#define S3C2450_PA_SMC9115 (0x20000000)
+
+ /* SROM SFR */
+#define S3C24XX_VA_SROMC S3C2410_ADDR(0x03700000)
+#define S3C2443_PA_SROMC (0x4F000000)
+#define S3C6400_PA_SROMC (0x70000000)
+#define S3C24XX_SZ_SROMC SZ_1M
+
+ /* DMC0 */
+#define S3C24XX_VA_DMC0 S3C2410_ADDR(0x01f00000)
+#define S3C24XX_PA_DMC0 (0x7E000000)
+#define S3C24XX_SZ_DMC0 SZ_4K
+ /* DMC1 */
+#define S3C24XX_VA_DMC1 S3C2410_ADDR(0x03800000)
+#define S3C24XX_PA_DMC1 (0x7E001000)
+#define S3C24XX_SZ_DMC1 SZ_4K
+
+#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
+ /* USB OTG */
+#define S3C24XX_VA_OTG S3C2410_ADDR(0x03900000)
+#define S3C24XX_PA_OTG (0x7c000000)
+#define S3C24XX_SZ_OTG SZ_1M
+
+ /* USB OTG SFR */
+#define S3C24XX_VA_OTGSFR S3C2410_ADDR(0x03a00000)
+#define S3C24XX_PA_OTGSFR (0x7c100000)
+#define S3C24XX_SZ_OTGSFR SZ_1M
+#endif
+
+ /* 2D Graphics */
+#define S3C6400_PA_2D (0x76100000)
+#define S3C_SZ_2D SZ_1M
+
+#define S3C6400_PA_ROTATOR (0x77200000)
+#define S3C_SZ_ROTATOR SZ_1M
+
+#if defined(CONFIG_CPU_S3C6410)
+ /* G3D */
+#define S3C6410_PA_G3D (0x72000000)
+#define S3C6410_SZ_G3D SZ_4K
+#endif
+
+ /* TV-ENCODER */
+#define S3C6400_PA_TVENC (0x76200000)
+#define S3C_SZ_TVENC SZ_1M
+
+ /* TV-SCALER*/
+#define S3C6400_PA_TVSCALER (0x76300000)
+#define S3C_SZ_TVSCALER SZ_1M
+
+ /* VPP */
+#define S3C6400_PA_VPP (0x77000000)
+#define S3C_SZ_VPP SZ_1M
+
+ /* MFC */
+#define S3C6400_PA_MFC (0x7E002000)
+#define S3C_SZ_MFC SZ_1M
+
+ /* JPEG */
+#define S3C6400_PA_JPEG (0x78800000)
+#define S3C_SZ_JPEG SZ_1M
+
+
+ /* OneNAND */
+#define S3C6400_PA_ONENAND (0x70100000)
+#define S3C_SZ_ONENAND SZ_4K
+
+ /* Keypad IF */
+#define S3C6400_PA_KEYPAD (0x7E00A000)
+#define S3C24XX_SZ_KEYPAD SZ_4K
+
+ /* EBI registers for 2443 */
+#define S3C24XX_VA_EBI S3C2410_ADDR(0x03c00000)
+#define S3C24XX_PA_EBI (0x4E800000)
+#define S3C24XX_SZ_EBI SZ_1M
/* ISA style IO, for each machine to sort out mappings for, if it
* implements it. We reserve two 16M regions for ISA.
@@ -81,6 +303,122 @@
#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
+
+ /* physical addresses of all the chip-select areas */
+
+#define S3C2410_CS0 (0x00000000)
+#define S3C2410_CS1 (0x08000000)
+#define S3C2410_CS2 (0x10000000)
+#define S3C2410_CS3 (0x18000000)
+#define S3C2410_CS4 (0x20000000)
+#define S3C2410_CS5 (0x28000000)
+#define S3C2410_CS6 (0x30000000)
+#define S3C2410_CS7 (0x38000000)
+
+#define S3C2410_SDRAM_PA (S3C2410_CS6)
+
+#define S3C2400_CS0 (0x00000000)
+#define S3C2400_CS1 (0x02000000)
+#define S3C2400_CS2 (0x04000000)
+#define S3C2400_CS3 (0x06000000)
+#define S3C2400_CS4 (0x08000000)
+#define S3C2400_CS5 (0x0A000000)
+#define S3C2400_CS6 (0x0C000000)
+#define S3C2400_CS7 (0x0E000000)
+
+#define S3C2400_SDRAM_PA (S3C2400_CS6)
+
+#define S3C_SDRAM_PA (0x50000000)
+ /* Use a single interface for common resources between S3C24XX cpus */
+
+#if defined CONFIG_CPU_S3C2400
+#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
+#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
+#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
+#define S3C24XX_PA_DMA S3C2400_PA_DMA
+#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
+/*#ifndef (CONFIG_CPU_S3C2443 || CONFIG_CPU_S3C2450 || CONFIG_CPU_S3C2416)*/
+#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2450) && !defined(CONFIG_CPU_S3C2416)
+#define S3C24XX_PA_LCD S3C2400_PA_LCD
+#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
+#define S3C24XX_PA_RTC S3C2400_PA_RTC
+#endif
+#define S3C24XX_PA_UART S3C2400_PA_UART
+#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
+
+#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
+#define S3C24XX_PA_IIC S3C2400_PA_IIC
+#define S3C24XX_PA_IIS S3C2400_PA_IIS
+#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
+
+#define S3C24XX_PA_ADC S3C2400_PA_ADC
+#define S3C24XX_PA_SPI S3C2400_PA_SPI
+#define S3C24XX_PA_NAND S3C2410_PA_NAND
+
+#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
+#define S3C24XX_PA_ADC S3C6400_PA_ADC
+#define S3C24XX_PA_CAMIF S3C6400_PA_CAMIF
+#define S3C24XX_PA_DMA S3C6400_PA_DMA
+#define S3C24XX_PA_IRQ S3C6400_PA_IRQ
+#define S3C24XX_PA_LCD S3C6400_PA_LCD
+#define S3C24XX_PA_UART S3C6400_PA_UART
+#define S3C24XX_PA_USBHOST S3C6400_PA_USBHOST
+#define S3C24XX_PA_WATCHDOG S3C6400_PA_WATCHDOG
+#define S3C24XX_PA_IIS S3C6400_PA_IIS
+#define S3C24XX_PA_IIC S3C6400_PA_IIC
+#define S3C24XX_PA_RTC S3C6400_PA_RTC
+#define S3C24XX_PA_SPI S3C6400_PA_SPI
+#define S3C24XX_PA_TIMER S3C6400_PA_TIMER
+#define S3C24XX_PA_NAND S3C6400_PA_NAND
+#define S3C24XX_PA_ONENAND S3C6400_PA_ONENAND
+#define S3C24XX_PA_GPIO S3C6400_PA_GPIO
+#define S3C24XX_PA_CS8900 S3C6400_PA_CS8900
+#define S3C24XX_PA_TVENC S3C6400_PA_TVENC
+#define S3C24XX_PA_TVSCALER S3C6400_PA_TVSCALER
+#define S3C24XX_PA_CFATA S3C6400_PA_CFATA
+#define S3C24XX_PA_AC97 S3C6400_PA_AC97
+#define S3C24XX_PA_KEYPAD S3C6400_PA_KEYPAD
+#define S3C24XX_PA_SROMC S3C6400_PA_SROMC
+#define S3C_PA_HSMMC S3C6400_PA_HSMMC
+#define S3C_PA_CFATA S3C6400_PA_CFATA
+#define S3C_PA_SMC9115 S3C6410_PA_SMC9115
+#else
+#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
+#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
+#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
+#define S3C24XX_PA_DMA S3C2410_PA_DMA
+#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
+#if defined (CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
+#define S3C24XX_PA_LCD S3C2443_PA_LCD
+#define S3C24XX_PA_CS8900 S3C2443_PA_CS8900
+#define S3C24XX_PA_USBDEV S3C2443_PA_USBDEV
+#define S3C24XX_PA_CAMIF S3C2443_PA_CAMIF
+#define S3C_PA_HSMMC S3C2443_PA_HSMMC
+#define S3C_PA_CFATA S3C2443_PA_CFATA
+#define S3C24XX_PA_SROMC S3C2443_PA_SROMC
+#define S3C_PA_SPI_0 (0x52000000)
+#define S3C_SZ_SPI_0 SZ_1M
+#define S3C_PA_SMC9115 S3C2450_PA_SMC9115
+#else
+#define S3C24XX_PA_LCD S3C2410_PA_LCD
+#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
+#endif
+#define S3C24XX_PA_UART S3C2410_PA_UART
+#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
+#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
+#define S3C24XX_PA_IIC S3C2410_PA_IIC
+#define S3C24XX_PA_IIS S3C2410_PA_IIS
+#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
+#if defined (CONFIG_CPU_S3C2450) || defined (CONFIG_CPU_S3C2416)
+#define S3C24XX_PA_RTC S3C2450_PA_RTC
+#else
+#define S3C24XX_PA_RTC S3C2410_PA_RTC
+#endif
+#define S3C24XX_PA_ADC S3C2410_PA_ADC
+#define S3C24XX_PA_SPI S3C2410_PA_SPI
+#define S3C24XX_PA_NAND S3C2410_PA_NAND
+#define S3C24XX_PA_AC97 S3C2440_PA_AC97
+#endif
/* deal with the registers that move under the 2412/2413 */
#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
index 3bc0a21..1bf52d0 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
@@ -128,6 +128,8 @@
#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
+#define S3C2450_DMAREQSEL_I2STX_1 S3C2443_DMAREQSEL_SRC(6)
+#define S3C2450_DMAREQSEL_I2SRX_1 S3C2443_DMAREQSEL_SRC(7)
#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h b/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
index a6f1d5d..86d46c3 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
@@ -74,4 +74,5 @@
#define S3C2400_IISFCON_RXSHIFT (0)
#define S3C2410_IISFIFO (0x10)
+#define S3C2410_IISFIFORX (0x14)
#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
index 2b35479..18fa9d0 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
@@ -79,4 +79,218 @@
#define S3C2412_SPFIC (0x24)
+#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
+/*
+ * SPI(High speed) Registers
+ */
+
+#define S3C_SPI_REG_CH0(x) ((x) + S3C_VA_SPI0)
+#define S3C_SPI_REG_CH1(x) ((x) + S3C_VA_SPI1)
+
+#define S3C_CH_CFG (0x00) //SPI configuration
+#define S3C_CLK_CFG (0x04) //Clock configuration
+#define S3C_MODE_CFG (0x08) //SPI FIFO control
+#define S3C_SLAVE_SEL (0x0C) //Slave selection
+#define S3C_SPI_INT_EN (0x10) //SPI interrupt enable
+#define S3C_SPI_STATUS (0x14) //SPI status
+#define S3C_SPI_TX_DATA (0x18) //SPI TX data
+#define S3C_SPI_RX_DATA (0x1C) //SPI RX data
+#define S3C_PACKET_CNT (0x20) //count how many data master gets
+#define S3C_PENDING_CLR (0x24) //Pending clear
+#define S3C_SWAP_CFG (0x28) //SWAP config register
+#define S3C_FB_CLK (0x28) //SWAP FB config register
+
+
+#define SPI_CH_SW_RST (1<<5)
+#define SPI_CH_MASTER (0<<4)
+#define SPI_CH_SLAVE (1<<4)
+#define SPI_CH_RISING (0<<3)
+#define SPI_CH_FALLING (1<<3)
+#define SPI_CH_FORMAT_A (0<<2)
+#define SPI_CH_FORMAT_B (1<<2)
+#define SPI_CH_RXCH_OFF (0<<1)
+#define SPI_CH_RXCH_ON (1<<1)
+#define SPI_CH_TXCH_OFF (0<<0)
+#define SPI_CH_TXCH_ON (1<<0)
+
+#define SPI_CLKSEL_PCLK (0<<9)
+#define SPI_CLKSEL_USBCLK (1<<9)
+#define SPI_CLKSEL_ECLK (2<<9)
+#define SPI_ENCLK_DISABLE (0<<8)
+#define SPI_ENCLK_ENABLE (1<<8)
+
+#define SPI_MODE_CH_TSZ_BYTE (0<<29)
+#define SPI_MODE_CH_TSZ_HALFWORD (1<<29)
+#define SPI_MODE_CH_TSZ_WORD (2<<29)
+#define SPI_MODE_BUS_TSZ_BYTE (0<<17)
+#define SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
+#define SPI_MODE_BUS_TSZ_WORD (2<<17)
+#define SPI_MODE_RXDMA_OFF (0<<2)
+#define SPI_MODE_RXDMA_ON (1<<2)
+#define SPI_MODE_TXDMA_OFF (0<<1)
+#define SPI_MODE_TXDMA_ON (1<<1)
+#define SPI_MODE_SINGLE (0<<0)
+#define SPI_MODE_4BURST (1<<0)
+
+#define SPI_SLAVE_MAN (0<<1)
+#define SPI_SLAVE_AUTO (1<<1)
+#define SPI_SLAVE_SIG_ACT (0<<0)
+#define SPI_SLAVE_SIG_INACT (1<<0)
+
+#define SPI_INT_TRAILING_DIS (0<<6)
+#define SPI_INT_TRAILING_EN (1<<6)
+#define SPI_INT_RX_OVERRUN_DIS (0<<5)
+#define SPI_INT_RX_OVERRUN_EN (1<<5)
+#define SPI_INT_RX_UNDERRUN_DIS (0<<4)
+#define SPI_INT_RX_UNDERRUN_EN (1<<4)
+#define SPI_INT_TX_OVERRUN_DIS (0<<3)
+#define SPI_INT_TX_OVERRUN_EN (1<<3)
+#define SPI_INT_TX_UNDERRUN_DIS (0<<2)
+#define SPI_INT_TX_UNDERRUN_EN (1<<2)
+#define SPI_INT_RX_FIFORDY_DIS (0<<1)
+#define SPI_INT_RX_FIFORDY_EN (1<<1)
+#define SPI_INT_TX_FIFORDY_DIS (0<<0)
+#define SPI_INT_TX_FIFORDY_EN (1<<0)
+
+#define SPI_STUS_TX_DONE (1<<21)
+#define SPI_STUS_TRAILCNT_ZERO (1<<20)
+#define SPI_STUS_RX_OVERRUN_ERR (1<<5)
+#define SPI_STUS_RX_UNDERRUN_ERR (1<<4)
+#define SPI_STUS_TX_OVERRUN_ERR (1<<3)
+#define SPI_STUS_TX_UNDERRUN_ERR (1<<2)
+#define SPI_STUS_RX_FIFORDY (1<<1)
+#define SPI_STUS_TX_FIFORDY (1<<0)
+
+#define SPI_PACKET_CNT_DIS (0<<16)
+#define SPI_PACKET_CNT_EN (1<<16)
+
+#define SPI_PND_TX_UNDERRUN_CLR (1<<4)
+#define SPI_PND_TX_OVERRUN_CLR (1<<3)
+#define SPI_PND_RX_UNDERRUN_CLR (1<<2)
+#define SPI_PND_RX_OVERRUN_CLR (1<<1)
+#define SPI_PND_TRAILING_CLR (1<<0)
+
+#define SPI_SWAP_RX_HALF_WORD (1<<7)
+#define SPI_SWAP_RX_BYTE (1<<6)
+#define SPI_SWAP_RX_BIT (1<<5)
+#define SPI_SWAP_RX_EN (1<<4)
+#define SPI_SWAP_TX_HALF_WORD (1<<3)
+#define SPI_SWAP_TX_BYTE (1<<2)
+#define SPI_SWAP_TX_BIT (1<<1)
+#define SPI_SWAP_TX_EN (1<<0)
+
+#define SPI_FBCLK_0NS (0<<0)
+#define SPI_FBCLK_2NS (1<<4)
+#define SPI_FBCLK_4NS (2<<4)
+#define SPI_FBCLK_6NS (3<<4)
+
+#endif
+
+#if defined CONFIG_CPU_S3C2443 || defined CONFIG_CPU_S3C2450 || defined CONFIG_CPU_S3C2416
+/*
+ * SPI(High speed) Registers
+ */
+
+#define S3C_SPI_REG_CH0(x) ((x) + S3C_VA_SPI0)
+#define S3C_SPI_REG_CH1(x) ((x) + S3C_VA_SPI1)
+
+#define S3C_CH_CFG (0x00) //SPI configuration
+#define S3C_CLK_CFG (0x04) //Clock configuration
+#define S3C_MODE_CFG (0x08) //SPI FIFO control
+#define S3C_SLAVE_SEL (0x0C) //Slave selection
+#define S3C_SPI_INT_EN (0x10) //SPI interrupt enable
+#define S3C_SPI_STATUS (0x14) //SPI status
+#define S3C_SPI_TX_DATA (0x18) //SPI TX data
+#define S3C_SPI_RX_DATA (0x1C) //SPI RX data
+#define S3C_PACKET_CNT (0x20) //count how many data master gets
+#define S3C_PENDING_CLR (0x24) //Pending clear
+#define S3C_SWAP_CFG (0x28) //SWAP config register
+#define S3C_FB_CLK (0x28) //SWAP FB config register
+
+
+#define SPI_CH_SW_RST (1<<5)
+#define SPI_CH_MASTER (0<<4)
+#define SPI_CH_SLAVE (1<<4)
+#define SPI_CH_RISING (0<<3)
+#define SPI_CH_FALLING (1<<3)
+#define SPI_CH_FORMAT_A (0<<2)
+#define SPI_CH_FORMAT_B (1<<2)
+#define SPI_CH_RXCH_OFF (0<<1)
+#define SPI_CH_RXCH_ON (1<<1)
+#define SPI_CH_TXCH_OFF (0<<0)
+#define SPI_CH_TXCH_ON (1<<0)
+
+#define SPI_CLKSEL_PCLK (0<<9)
+#define SPI_CLKSEL_USBCLK (1<<9)
+#define SPI_CLKSEL_ECLK (2<<9)
+#define SPI_ENCLK_DISABLE (0<<8)
+#define SPI_ENCLK_ENABLE (1<<8)
+
+#define SPI_MODE_CH_TSZ_BYTE (0<<18)
+#define SPI_MODE_CH_TSZ_HALFWORD (1<<29)
+#define SPI_MODE_CH_TSZ_WORD (2<<18)
+#define SPI_MODE_BUS_TSZ_BYTE (0<<17)
+#define SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
+#define SPI_MODE_BUS_TSZ_WORD (2<<17)
+#define SPI_MODE_RXDMA_OFF (0<<2)
+#define SPI_MODE_RXDMA_ON (1<<2)
+#define SPI_MODE_TXDMA_OFF (0<<1)
+#define SPI_MODE_TXDMA_ON (1<<1)
+#define SPI_MODE_SINGLE (0<<0)
+#define SPI_MODE_4BURST (1<<0)
+
+#define SPI_SLAVE_MAN (0<<1)
+#define SPI_SLAVE_AUTO (1<<1)
+#define SPI_SLAVE_SIG_ACT (0<<0)
+#define SPI_SLAVE_SIG_INACT (1<<0)
+
+#define SPI_INT_TRAILING_DIS (0<<6)
+#define SPI_INT_TRAILING_EN (1<<6)
+#define SPI_INT_RX_OVERRUN_DIS (0<<5)
+#define SPI_INT_RX_OVERRUN_EN (1<<5)
+#define SPI_INT_RX_UNDERRUN_DIS (0<<4)
+#define SPI_INT_RX_UNDERRUN_EN (1<<4)
+#define SPI_INT_TX_OVERRUN_DIS (0<<3)
+#define SPI_INT_TX_OVERRUN_EN (1<<3)
+#define SPI_INT_TX_UNDERRUN_DIS (0<<2)
+#define SPI_INT_TX_UNDERRUN_EN (1<<2)
+#define SPI_INT_RX_FIFORDY_DIS (0<<1)
+#define SPI_INT_RX_FIFORDY_EN (1<<1)
+#define SPI_INT_TX_FIFORDY_DIS (0<<0)
+#define SPI_INT_TX_FIFORDY_EN (1<<0)
+
+#define SPI_STUS_TX_DONE (1<<21)
+#define SPI_STUS_TRAILCNT_ZERO (1<<20)
+#define SPI_STUS_RX_OVERRUN_ERR (1<<5)
+#define SPI_STUS_RX_UNDERRUN_ERR (1<<4)
+#define SPI_STUS_TX_OVERRUN_ERR (1<<3)
+#define SPI_STUS_TX_UNDERRUN_ERR (1<<2)
+#define SPI_STUS_RX_FIFORDY (1<<1)
+#define SPI_STUS_TX_FIFORDY (1<<0)
+
+#define SPI_PACKET_CNT_DIS (0<<16)
+#define SPI_PACKET_CNT_EN (1<<16)
+
+#define SPI_PND_TX_UNDERRUN_CLR (1<<4)
+#define SPI_PND_TX_OVERRUN_CLR (1<<3)
+#define SPI_PND_RX_UNDERRUN_CLR (1<<2)
+#define SPI_PND_RX_OVERRUN_CLR (1<<1)
+#define SPI_PND_TRAILING_CLR (1<<0)
+
+#define SPI_SWAP_RX_HALF_WORD (1<<7)
+#define SPI_SWAP_RX_BYTE (1<<6)
+#define SPI_SWAP_RX_BIT (1<<5)
+#define SPI_SWAP_RX_EN (1<<4)
+#define SPI_SWAP_TX_HALF_WORD (1<<3)
+#define SPI_SWAP_TX_BYTE (1<<2)
+#define SPI_SWAP_TX_BIT (1<<1)
+#define SPI_SWAP_TX_EN (1<<0)
+
+#define SPI_FBCLK_0NS (0<<0)
+#define SPI_FBCLK_2NS (1<<4)
+#define SPI_FBCLK_4NS (2<<4)
+#define SPI_FBCLK_6NS (3<<4)
+
+#endif
+
#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index d02f5f0..adba5f7 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -98,6 +98,57 @@ struct irq_chip s3c_irq_chip = {
.unmask = s3c_irq_unmask,
.set_wake = s3c_irq_wake
};
+#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
+/*--- For additional interrupt sources on S3C2450/S3C2416 ----*/
+static void
+ s3c2450_irq_mask(unsigned int irqno)
+{
+ unsigned long mask;
+
+ irqno -= IRQ_S3C2450_2D;
+
+ mask = __raw_readl(S3C2450_INTMSK);
+ mask |= 1UL << irqno;
+ __raw_writel(mask, S3C2450_INTMSK);
+}
+
+static inline void
+ s3c2450_irq_maskack(unsigned int irqno)
+{
+ unsigned long bitval = 1UL << (irqno - IRQ_S3C2450_2D);
+ unsigned long mask;
+
+ mask = __raw_readl(S3C2450_INTMSK);
+ __raw_writel(mask|bitval, S3C2450_INTMSK);
+
+ __raw_writel(bitval, S3C2450_SRCPND);
+ __raw_writel(bitval, S3C2450_INTPND);
+}
+
+
+static void
+ s3c2450_irq_unmask(unsigned int irqno)
+{
+ unsigned long mask;
+
+ irqno -= IRQ_S3C2450_2D;
+
+ mask = __raw_readl(S3C2450_INTMSK);
+ mask &= ~(1UL << irqno);
+ __raw_writel(mask, S3C2450_INTMSK);
+}
+
+struct irq_chip s3c2450_irq_level_chip = {
+ .name = "s3c2450-level",
+ .ack = s3c2450_irq_maskack,
+ .mask = s3c2450_irq_mask,
+ .unmask = s3c2450_irq_unmask,
+ //.set_wake = s3c2450_irq_wake
+};
+
+/*--------------------------------------------------------------*/
+#endif
+
static void
s3c_irqext_mask(unsigned int irqno)
@@ -672,6 +723,31 @@ void __init s3c24xx_init_irq(void)
set_irq_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
+
+#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
+ /* first, clear all interrupts pending... */
+ last = 0;
+ for (i = 0; i < 4; i++) {
+ pend = __raw_readl(S3C2450_INTPND);
+
+ if (pend == 0 || pend == last)
+ break;
+
+ __raw_writel(pend, S3C2450_SRCPND);
+ __raw_writel(pend, S3C2450_INTPND);
+ printk("irq: clearing pending status %08x\n", (int)pend);
+ last = pend;
+ }
+
+ for (irqno = IRQ_S3C2450_2D; irqno <= IRQ_S3C2450_I2S1; irqno++) {
+ irqdbf("registering irq %d (s3c gib irq)\n", irqno);
+
+ set_irq_chip(irqno, &s3c2450_irq_level_chip);
+ set_irq_handler(irqno, handle_level_irq);
+ set_irq_flags(irqno, IRQF_VALID);
+ }
+#endif
+
irqdbf("s3c2410: registered interrupt handlers\n");
}
diff --git a/drivers/hwmon/s3c-hwmon.c b/drivers/hwmon/s3c-hwmon.c
index 7183541..3f3f9a4 100644
--- a/drivers/hwmon/s3c-hwmon.c
+++ b/drivers/hwmon/s3c-hwmon.c
@@ -323,7 +323,7 @@ static int __devinit s3c_hwmon_probe(struct platform_device *dev)
}
for (i = 0; i < ARRAY_SIZE(pdata->in); i++) {
- struct s3c24xx_adc_hwmon_incfg *cfg = pdata->in[i];
+ struct s3c_hwmon_chcfg *cfg = pdata->in[i];
if (!cfg)
continue;
@@ -333,7 +333,7 @@ static int __devinit s3c_hwmon_probe(struct platform_device *dev)
"channel %d multiplier too large\n",
i);
- if (cfg->divider == 0) {
+ if (cfg->div == 0) {
dev_err(&dev->dev, "channel %d divider zero\n", i);
continue;
}
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index 99b74a3..8c08cd7 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -17,8 +17,6 @@
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/cpufreq.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/io.h>
@@ -60,6 +58,8 @@ static const int dbgmap_debug = dbg_err | dbg_debug;
dev_dbg(&host->pdev->dev, args); \
} while (0)
+#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
+
static struct s3c2410_dma_client s3cmci_dma_client = {
.name = "s3c-mci",
};
@@ -164,40 +164,6 @@ static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
#endif /* CONFIG_MMC_DEBUG */
-/**
- * s3cmci_host_usedma - return whether the host is using dma or pio
- * @host: The host state
- *
- * Return true if the host is using DMA to transfer data, else false
- * to use PIO mode. Will return static data depending on the driver
- * configuration.
- */
-static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
-{
-#ifdef CONFIG_MMC_S3C_PIO
- return false;
-#elif defined(CONFIG_MMC_S3C_DMA)
- return true;
-#else
- return host->dodma;
-#endif
-}
-
-/**
- * s3cmci_host_canpio - return true if host has pio code available
- *
- * Return true if the driver has been compiled with the PIO support code
- * available.
- */
-static inline bool s3cmci_host_canpio(void)
-{
-#ifdef CONFIG_MMC_S3C_PIO
- return true;
-#else
- return false;
-#endif
-}
-
static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
{
u32 newmask;
@@ -224,33 +190,7 @@ static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
static inline void clear_imask(struct s3cmci_host *host)
{
- u32 mask = readl(host->base + host->sdiimsk);
-
- /* preserve the SDIO IRQ mask state */
- mask &= S3C2410_SDIIMSK_SDIOIRQ;
- writel(mask, host->base + host->sdiimsk);
-}
-
-/**
- * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
- * @host: The host to check.
- *
- * Test to see if the SDIO interrupt is being signalled in case the
- * controller has failed to re-detect a card interrupt. Read GPE8 and
- * see if it is low and if so, signal a SDIO interrupt.
- *
- * This is currently called if a request is finished (we assume that the
- * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
- * already being indicated.
-*/
-static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
-{
- if (host->sdio_irqen) {
- if (gpio_get_value(S3C2410_GPE(8)) == 0) {
- printk(KERN_DEBUG "%s: signalling irq\n", __func__);
- mmc_signal_sdio_irq(host->mmc);
- }
- }
+ writel(0, host->base + host->sdiimsk);
}
static inline int get_data_buffer(struct s3cmci_host *host,
@@ -298,64 +238,6 @@ static inline u32 fifo_free(struct s3cmci_host *host)
return 63 - fifostat;
}
-/**
- * s3cmci_enable_irq - enable IRQ, after having disabled it.
- * @host: The device state.
- * @more: True if more IRQs are expected from transfer.
- *
- * Enable the main IRQ if needed after it has been disabled.
- *
- * The IRQ can be one of the following states:
- * - disabled during IDLE
- * - disabled whilst processing data
- * - enabled during transfer
- * - enabled whilst awaiting SDIO interrupt detection
- */
-static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
-{
- unsigned long flags;
- bool enable = false;
-
- local_irq_save(flags);
-
- host->irq_enabled = more;
- host->irq_disabled = false;
-
- enable = more | host->sdio_irqen;
-
- if (host->irq_state != enable) {
- host->irq_state = enable;
-
- if (enable)
- enable_irq(host->irq);
- else
- disable_irq(host->irq);
- }
-
- local_irq_restore(flags);
-}
-
-/**
- *
- */
-static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
-{
- unsigned long flags;
-
- local_irq_save(flags);
-
- //printk(KERN_DEBUG "%s: transfer %d\n", __func__, transfer);
-
- host->irq_disabled = transfer;
-
- if (transfer && host->irq_state) {
- host->irq_state = false;
- disable_irq(host->irq);
- }
-
- local_irq_restore(flags);
-}
-
static void do_pio_read(struct s3cmci_host *host)
{
int res;
@@ -492,7 +374,8 @@ static void pio_tasklet(unsigned long data)
{
struct s3cmci_host *host = (struct s3cmci_host *) data;
- s3cmci_disable_irq(host, true);
+
+ disable_irq(host->irq);
if (host->pio_active == XFER_WRITE)
do_pio_write(host);
@@ -512,10 +395,9 @@ static void pio_tasklet(unsigned long data)
host->mrq->data->error = -EINVAL;
}
- s3cmci_enable_irq(host, false);
finalize_request(host);
} else
- s3cmci_enable_irq(host, true);
+ enable_irq(host->irq);
}
/*
@@ -550,27 +432,17 @@ static irqreturn_t s3cmci_irq(int irq, void *dev_id)
struct s3cmci_host *host = dev_id;
struct mmc_command *cmd;
u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
- u32 mci_cclear = 0, mci_dclear;
+ u32 mci_cclear, mci_dclear;
unsigned long iflags;
- mci_dsta = readl(host->base + S3C2410_SDIDSTA);
- mci_imsk = readl(host->base + host->sdiimsk);
-
- if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
- if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
- mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
- writel(mci_dclear, host->base + S3C2410_SDIDSTA);
-
- mmc_signal_sdio_irq(host->mmc);
- return IRQ_HANDLED;
- }
- }
-
spin_lock_irqsave(&host->complete_lock, iflags);
mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
+ mci_dsta = readl(host->base + S3C2410_SDIDSTA);
mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
mci_fsta = readl(host->base + S3C2410_SDIFSTA);
+ mci_imsk = readl(host->base + host->sdiimsk);
+ mci_cclear = 0;
mci_dclear = 0;
if ((host->complete_what == COMPLETION_NONE) ||
@@ -594,7 +466,7 @@ static irqreturn_t s3cmci_irq(int irq, void *dev_id)
goto irq_out;
}
- if (!s3cmci_host_usedma(host)) {
+ if (!host->dodma) {
if ((host->pio_active == XFER_WRITE) &&
(mci_fsta & S3C2410_SDIFSTA_TFDET)) {
@@ -801,7 +673,6 @@ static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
size, mci_dsta, mci_dcnt);
- host->dma_complete = 1;
host->complete_what = COMPLETION_FINALIZE;
out:
@@ -812,9 +683,9 @@ out:
fail_request:
host->mrq->data->error = -EINVAL;
host->complete_what = COMPLETION_FINALIZE;
- clear_imask(host);
-
+ writel(0, host->base + host->sdiimsk);
goto out;
+
}
static void finalize_request(struct s3cmci_host *host)
@@ -831,9 +702,8 @@ static void finalize_request(struct s3cmci_host *host)
if (cmd->data && (cmd->error == 0) &&
(cmd->data->error == 0)) {
- if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
- dbg(host, dbg_dma, "DMA Missing (%d)!\n",
- host->dma_complete);
+ if (host->dodma && (!host->dma_complete)) {
+ dbg(host, dbg_dma, "DMA Missing!\n");
return;
}
}
@@ -858,7 +728,7 @@ static void finalize_request(struct s3cmci_host *host)
writel(0, host->base + S3C2410_SDICMDARG);
writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
writel(0, host->base + S3C2410_SDICMDCON);
- clear_imask(host);
+ writel(0, host->base + host->sdiimsk);
if (cmd->data && cmd->error)
cmd->data->error = cmd->error;
@@ -884,7 +754,7 @@ static void finalize_request(struct s3cmci_host *host)
/* If we had an error while transfering data we flush the
* DMA channel and the fifo to clear out any garbage. */
if (mrq->data->error != 0) {
- if (s3cmci_host_usedma(host))
+ if (host->dodma)
s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
if (host->is2440) {
@@ -906,8 +776,6 @@ static void finalize_request(struct s3cmci_host *host)
request_done:
host->complete_what = COMPLETION_NONE;
host->mrq = NULL;
-
- s3cmci_check_sdio_irq(host);
mmc_request_done(host->mmc, mrq);
}
@@ -1004,7 +872,7 @@ static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
- if (s3cmci_host_usedma(host))
+ if (host->dodma)
dcon |= S3C2410_SDIDCON_DMAEN;
if (host->bus_width == MMC_BUS_WIDTH_4)
@@ -1082,7 +950,7 @@ static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
{
int dma_len, i;
- int rw = data->flags & MMC_DATA_WRITE;
+ int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
@@ -1090,7 +958,7 @@ static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
- rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+ (rw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
if (dma_len == 0)
return -ENOMEM;
@@ -1101,11 +969,11 @@ static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
for (i = 0; i < dma_len; i++) {
int res;
- dbg(host, dbg_dma, "enqueue %i: %08x@%u\n", i,
- sg_dma_address(&data->sg[i]),
- sg_dma_len(&data->sg[i]));
+ dbg(host, dbg_dma, "enqueue %i:%u@%u\n", i,
+ sg_dma_address(&data->sg[i]),
+ sg_dma_len(&data->sg[i]));
- res = s3c2410_dma_enqueue(host->dma, host,
+ res = s3c2410_dma_enqueue(host->dma, (void *) host,
sg_dma_address(&data->sg[i]),
sg_dma_len(&data->sg[i]));
@@ -1150,7 +1018,7 @@ static void s3cmci_send_request(struct mmc_host *mmc)
return;
}
- if (s3cmci_host_usedma(host))
+ if (host->dodma)
res = s3cmci_prepare_dma(host, cmd->data);
else
res = s3cmci_prepare_pio(host, cmd->data);
@@ -1169,7 +1037,7 @@ static void s3cmci_send_request(struct mmc_host *mmc)
s3cmci_send_command(host, cmd);
/* Enable Interrupt */
- s3cmci_enable_irq(host, true);
+ enable_irq(host->irq);
}
static int s3cmci_card_present(struct mmc_host *mmc)
@@ -1181,7 +1049,7 @@ static int s3cmci_card_present(struct mmc_host *mmc)
if (pdata->gpio_detect == 0)
return -ENOSYS;
- ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
+ ret = s3c2410_gpio_getpin(pdata->gpio_detect) ? 0 : 1;
return ret ^ pdata->detect_invert;
}
@@ -1236,12 +1104,12 @@ static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
switch (ios->power_mode) {
case MMC_POWER_ON:
case MMC_POWER_UP:
- s3c2410_gpio_cfgpin(S3C2410_GPE(5), S3C2410_GPE5_SDCLK);
- s3c2410_gpio_cfgpin(S3C2410_GPE(6), S3C2410_GPE6_SDCMD);
- s3c2410_gpio_cfgpin(S3C2410_GPE(7), S3C2410_GPE7_SDDAT0);
- s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
- s3c2410_gpio_cfgpin(S3C2410_GPE(9), S3C2410_GPE9_SDDAT2);
- s3c2410_gpio_cfgpin(S3C2410_GPE(10), S3C2410_GPE10_SDDAT3);
+ s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_SDCLK);
+ s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2410_GPE6_SDCMD);
+ s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2410_GPE7_SDDAT0);
+ s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
+ s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2410_GPE9_SDDAT2);
+ s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2410_GPE10_SDDAT3);
if (host->pdata->set_power)
host->pdata->set_power(ios->power_mode, ios->vdd);
@@ -1253,7 +1121,8 @@ static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
case MMC_POWER_OFF:
default:
- gpio_direction_output(S3C2410_GPE(5), 0);
+ s3c2410_gpio_setpin(S3C2410_GPE5, 0);
+ s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPIO_OUTPUT);
if (host->is2440)
mci_con |= S3C2440_SDICON_SDRESET;
@@ -1299,7 +1168,7 @@ static int s3cmci_get_ro(struct mmc_host *mmc)
struct s3c24xx_mci_pdata *pdata = host->pdata;
int ret;
- if (pdata->no_wprotect)
+ if (pdata->gpio_wprotect == 0)
return 0;
ret = s3c2410_gpio_getpin(pdata->gpio_wprotect);
@@ -1310,52 +1179,11 @@ static int s3cmci_get_ro(struct mmc_host *mmc)
return ret;
}
-static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
-{
- struct s3cmci_host *host = mmc_priv(mmc);
- unsigned long flags;
- u32 con;
-
- local_irq_save(flags);
-
- con = readl(host->base + S3C2410_SDICON);
- host->sdio_irqen = enable;
-
- if (enable == host->sdio_irqen)
- goto same_state;
-
- if (enable) {
- con |= S3C2410_SDICON_SDIOIRQ;
- enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
-
- if (!host->irq_state && !host->irq_disabled) {
- host->irq_state = true;
- enable_irq(host->irq);
- }
- } else {
- disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
- con &= ~S3C2410_SDICON_SDIOIRQ;
-
- if (!host->irq_enabled && host->irq_state) {
- disable_irq_nosync(host->irq);
- host->irq_state = false;
- }
- }
-
- writel(con, host->base + S3C2410_SDICON);
-
- same_state:
- local_irq_restore(flags);
-
- s3cmci_check_sdio_irq(host);
-}
-
static struct mmc_host_ops s3cmci_ops = {
.request = s3cmci_request,
.set_ios = s3cmci_set_ios,
.get_ro = s3cmci_get_ro,
.get_cd = s3cmci_card_present,
- .enable_sdio_irq = s3cmci_enable_sdio_irq,
};
static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
@@ -1418,140 +1246,11 @@ static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
}
#endif
-
-#ifdef CONFIG_DEBUG_FS
-
-static int s3cmci_state_show(struct seq_file *seq, void *v)
-{
- struct s3cmci_host *host = seq->private;
-
- seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
- seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
- seq_printf(seq, "Prescale = %d\n", host->prescaler);
- seq_printf(seq, "is2440 = %d\n", host->is2440);
- seq_printf(seq, "IRQ = %d\n", host->irq);
- seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
- seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
- seq_printf(seq, "IRQ state = %d\n", host->irq_state);
- seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
- seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
- seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
- seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
-
- return 0;
-}
-
-static int s3cmci_state_open(struct inode *inode, struct file *file)
-{
- return single_open(file, s3cmci_state_show, inode->i_private);
-}
-
-static const struct file_operations s3cmci_fops_state = {
- .owner = THIS_MODULE,
- .open = s3cmci_state_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-#define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
-
-struct s3cmci_reg {
- unsigned short addr;
- unsigned char *name;
-} debug_regs[] = {
- DBG_REG(CON),
- DBG_REG(PRE),
- DBG_REG(CMDARG),
- DBG_REG(CMDCON),
- DBG_REG(CMDSTAT),
- DBG_REG(RSP0),
- DBG_REG(RSP1),
- DBG_REG(RSP2),
- DBG_REG(RSP3),
- DBG_REG(TIMER),
- DBG_REG(BSIZE),
- DBG_REG(DCON),
- DBG_REG(DCNT),
- DBG_REG(DSTA),
- DBG_REG(FSTA),
- {}
-};
-
-static int s3cmci_regs_show(struct seq_file *seq, void *v)
-{
- struct s3cmci_host *host = seq->private;
- struct s3cmci_reg *rptr = debug_regs;
-
- for (; rptr->name; rptr++)
- seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
- readl(host->base + rptr->addr));
-
- seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
-
- return 0;
-}
-
-static int s3cmci_regs_open(struct inode *inode, struct file *file)
-{
- return single_open(file, s3cmci_regs_show, inode->i_private);
-}
-
-static const struct file_operations s3cmci_fops_regs = {
- .owner = THIS_MODULE,
- .open = s3cmci_regs_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static void s3cmci_debugfs_attach(struct s3cmci_host *host)
-{
- struct device *dev = &host->pdev->dev;
-
- host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
- if (IS_ERR(host->debug_root)) {
- dev_err(dev, "failed to create debugfs root\n");
- return;
- }
-
- host->debug_state = debugfs_create_file("state", 0444,
- host->debug_root, host,
- &s3cmci_fops_state);
-
- if (IS_ERR(host->debug_state))
- dev_err(dev, "failed to create debug state file\n");
-
- host->debug_regs = debugfs_create_file("regs", 0444,
- host->debug_root, host,
- &s3cmci_fops_regs);
-
- if (IS_ERR(host->debug_regs))
- dev_err(dev, "failed to create debug regs file\n");
-}
-
-static void s3cmci_debugfs_remove(struct s3cmci_host *host)
-{
- debugfs_remove(host->debug_regs);
- debugfs_remove(host->debug_state);
- debugfs_remove(host->debug_root);
-}
-
-#else
-static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
-static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
-
-#endif /* CONFIG_DEBUG_FS */
-
-static int __devinit s3cmci_probe(struct platform_device *pdev)
+static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440)
{
struct s3cmci_host *host;
struct mmc_host *mmc;
int ret;
- int is2440;
- int i;
-
- is2440 = platform_get_device_id(pdev)->driver_data;
mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
if (!mmc) {
@@ -1559,18 +1258,6 @@ static int __devinit s3cmci_probe(struct platform_device *pdev)
goto probe_out;
}
- for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
- ret = gpio_request(i, dev_name(&pdev->dev));
- if (ret) {
- dev_err(&pdev->dev, "failed to get gpio %d\n", i);
-
- for (i--; i >= S3C2410_GPE(5); i--)
- gpio_free(i);
-
- goto probe_free_host;
- }
- }
-
host = mmc_priv(mmc);
host->mmc = mmc;
host->pdev = pdev;
@@ -1595,12 +1282,11 @@ static int __devinit s3cmci_probe(struct platform_device *pdev)
host->clk_div = 2;
}
+ host->dodma = 0;
host->complete_what = COMPLETION_NONE;
host->pio_active = XFER_NONE;
-#ifdef CONFIG_MMC_S3C_PIODMA
- host->dodma = host->pdata->dma;
-#endif
+ host->dma = S3CMCI_DMA;
host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!host->mem) {
@@ -1608,19 +1294,19 @@ static int __devinit s3cmci_probe(struct platform_device *pdev)
"failed to get io memory region resouce.\n");
ret = -ENOENT;
- goto probe_free_gpio;
+ goto probe_free_host;
}
host->mem = request_mem_region(host->mem->start,
- resource_size(host->mem), pdev->name);
+ RESSIZE(host->mem), pdev->name);
if (!host->mem) {
dev_err(&pdev->dev, "failed to request io memory region.\n");
ret = -ENOENT;
- goto probe_free_gpio;
+ goto probe_free_host;
}
- host->base = ioremap(host->mem->start, resource_size(host->mem));
+ host->base = ioremap(host->mem->start, RESSIZE(host->mem));
if (!host->base) {
dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
ret = -EINVAL;
@@ -1645,60 +1331,31 @@ static int __devinit s3cmci_probe(struct platform_device *pdev)
* ensure we don't lock the system with un-serviceable requests. */
disable_irq(host->irq);
- host->irq_state = false;
- if (!host->pdata->no_detect) {
- ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
- if (ret) {
- dev_err(&pdev->dev, "failed to get detect gpio\n");
- goto probe_free_irq;
- }
+ host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect);
- host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect);
-
- if (host->irq_cd >= 0) {
- if (request_irq(host->irq_cd, s3cmci_irq_cd,
- IRQF_TRIGGER_RISING |
- IRQF_TRIGGER_FALLING,
- DRIVER_NAME, host)) {
- dev_err(&pdev->dev,
- "can't get card detect irq.\n");
- ret = -ENOENT;
- goto probe_free_gpio_cd;
- }
- } else {
- dev_warn(&pdev->dev,
- "host detect has no irq available\n");
- gpio_direction_input(host->pdata->gpio_detect);
- }
- } else
- host->irq_cd = -1;
-
- if (!host->pdata->no_wprotect) {
- ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
- if (ret) {
- dev_err(&pdev->dev, "failed to get writeprotect\n");
- goto probe_free_irq_cd;
+ if (host->irq_cd >= 0) {
+ if (request_irq(host->irq_cd, s3cmci_irq_cd,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ DRIVER_NAME, host)) {
+ dev_err(&pdev->dev, "can't get card detect irq.\n");
+ ret = -ENOENT;
+ goto probe_free_irq;
}
-
- gpio_direction_input(host->pdata->gpio_wprotect);
+ } else {
+ dev_warn(&pdev->dev, "host detect has no irq available\n");
+ s3c2410_gpio_cfgpin(host->pdata->gpio_detect,
+ S3C2410_GPIO_INPUT);
}
- /* depending on the dma state, get a dma channel to use. */
+ if (host->pdata->gpio_wprotect)
+ s3c2410_gpio_cfgpin(host->pdata->gpio_wprotect,
+ S3C2410_GPIO_INPUT);
- if (s3cmci_host_usedma(host)) {
- host->dma = s3c2410_dma_request(DMACH_SDI, &s3cmci_dma_client,
- host);
- if (host->dma < 0) {
- dev_err(&pdev->dev, "cannot get DMA channel.\n");
- if (!s3cmci_host_canpio()) {
- ret = -EBUSY;
- goto probe_free_gpio_wp;
- } else {
- dev_warn(&pdev->dev, "falling back to PIO.\n");
- host->dodma = 0;
- }
- }
+ if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL) < 0) {
+ dev_err(&pdev->dev, "unable to get DMA channel.\n");
+ ret = -EBUSY;
+ goto probe_free_irq_cd;
}
host->clk = clk_get(&pdev->dev, "sdi");
@@ -1706,7 +1363,7 @@ static int __devinit s3cmci_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "failed to find clock source.\n");
ret = PTR_ERR(host->clk);
host->clk = NULL;
- goto probe_free_dma;
+ goto probe_free_host;
}
ret = clk_enable(host->clk);
@@ -1719,11 +1376,7 @@ static int __devinit s3cmci_probe(struct platform_device *pdev)
mmc->ops = &s3cmci_ops;
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-#ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
- mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
-#else
mmc->caps = MMC_CAP_4_BIT_DATA;
-#endif
mmc->f_min = host->clk_rate / (host->clk_div * 256);
mmc->f_max = host->clk_rate / host->clk_div;
@@ -1755,12 +1408,8 @@ static int __devinit s3cmci_probe(struct platform_device *pdev)
goto free_cpufreq;
}
- s3cmci_debugfs_attach(host);
-
platform_set_drvdata(pdev, mmc);
- dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
- s3cmci_host_usedma(host) ? "dma" : "pio",
- mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
+ dev_info(&pdev->dev, "initialisation done.\n");
return 0;
@@ -1773,18 +1422,6 @@ static int __devinit s3cmci_probe(struct platform_device *pdev)
clk_free:
clk_put(host->clk);
- probe_free_dma:
- if (s3cmci_host_usedma(host))
- s3c2410_dma_free(host->dma, &s3cmci_dma_client);
-
- probe_free_gpio_wp:
- if (!host->pdata->no_wprotect)
- gpio_free(host->pdata->gpio_wprotect);
-
- probe_free_gpio_cd:
- if (!host->pdata->no_detect)
- gpio_free(host->pdata->gpio_detect);
-
probe_free_irq_cd:
if (host->irq_cd >= 0)
free_irq(host->irq_cd, host);
@@ -1796,15 +1433,10 @@ static int __devinit s3cmci_probe(struct platform_device *pdev)
iounmap(host->base);
probe_free_mem_region:
- release_mem_region(host->mem->start, resource_size(host->mem));
-
- probe_free_gpio:
- for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
- gpio_free(i);
+ release_mem_region(host->mem->start, RESSIZE(host->mem));
probe_free_host:
mmc_free_host(mmc);
-
probe_out:
return ret;
}
@@ -1817,7 +1449,6 @@ static void s3cmci_shutdown(struct platform_device *pdev)
if (host->irq_cd >= 0)
free_irq(host->irq_cd, host);
- s3cmci_debugfs_remove(host);
s3cmci_cpufreq_deregister(host);
mmc_remove_host(mmc);
clk_disable(host->clk);
@@ -1827,102 +1458,104 @@ static int __devexit s3cmci_remove(struct platform_device *pdev)
{
struct mmc_host *mmc = platform_get_drvdata(pdev);
struct s3cmci_host *host = mmc_priv(mmc);
- struct s3c24xx_mci_pdata *pd = host->pdata;
- int i;
s3cmci_shutdown(pdev);
clk_put(host->clk);
tasklet_disable(&host->pio_tasklet);
-
- if (s3cmci_host_usedma(host))
- s3c2410_dma_free(host->dma, &s3cmci_dma_client);
+ s3c2410_dma_free(S3CMCI_DMA, &s3cmci_dma_client);
free_irq(host->irq, host);
- if (!pd->no_wprotect)
- gpio_free(pd->gpio_wprotect);
-
- if (!pd->no_detect)
- gpio_free(pd->gpio_detect);
-
- for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
- gpio_free(i);
-
-
iounmap(host->base);
- release_mem_region(host->mem->start, resource_size(host->mem));
+ release_mem_region(host->mem->start, RESSIZE(host->mem));
mmc_free_host(mmc);
return 0;
}
-static struct platform_device_id s3cmci_driver_ids[] = {
- {
- .name = "s3c2410-sdi",
- .driver_data = 0,
- }, {
- .name = "s3c2412-sdi",
- .driver_data = 1,
- }, {
- .name = "s3c2440-sdi",
- .driver_data = 1,
- },
- { }
-};
+static int __devinit s3cmci_2410_probe(struct platform_device *dev)
+{
+ return s3cmci_probe(dev, 0);
+}
-MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
+static int __devinit s3cmci_2412_probe(struct platform_device *dev)
+{
+ return s3cmci_probe(dev, 1);
+}
+static int __devinit s3cmci_2440_probe(struct platform_device *dev)
+{
+ return s3cmci_probe(dev, 1);
+}
#ifdef CONFIG_PM
-static int s3cmci_suspend(struct device *dev)
+static int s3cmci_suspend(struct platform_device *dev, pm_message_t state)
{
- struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
- struct pm_message event = { PM_EVENT_SUSPEND };
+ struct mmc_host *mmc = platform_get_drvdata(dev);
- return mmc_suspend_host(mmc, event);
+ return mmc_suspend_host(mmc, state);
}
-static int s3cmci_resume(struct device *dev)
+static int s3cmci_resume(struct platform_device *dev)
{
- struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
+ struct mmc_host *mmc = platform_get_drvdata(dev);
return mmc_resume_host(mmc);
}
-static struct dev_pm_ops s3cmci_pm = {
+#else /* CONFIG_PM */
+#define s3cmci_suspend NULL
+#define s3cmci_resume NULL
+#endif /* CONFIG_PM */
+
+
+static struct platform_driver s3cmci_2410_driver = {
+ .driver.name = "s3c2410-sdi",
+ .driver.owner = THIS_MODULE,
+ .probe = s3cmci_2410_probe,
+ .remove = __devexit_p(s3cmci_remove),
+ .shutdown = s3cmci_shutdown,
.suspend = s3cmci_suspend,
.resume = s3cmci_resume,
};
-#define s3cmci_pm_ops &s3cmci_pm
-#else /* CONFIG_PM */
-#define s3cmci_pm_ops NULL
-#endif /* CONFIG_PM */
-
+static struct platform_driver s3cmci_2412_driver = {
+ .driver.name = "s3c2412-sdi",
+ .driver.owner = THIS_MODULE,
+ .probe = s3cmci_2412_probe,
+ .remove = __devexit_p(s3cmci_remove),
+ .shutdown = s3cmci_shutdown,
+ .suspend = s3cmci_suspend,
+ .resume = s3cmci_resume,
+};
-static struct platform_driver s3cmci_driver = {
- .driver = {
- .name = "s3c-sdi",
- .owner = THIS_MODULE,
- .pm = s3cmci_pm_ops,
- },
- .id_table = s3cmci_driver_ids,
- .probe = s3cmci_probe,
+static struct platform_driver s3cmci_2440_driver = {
+ .driver.name = "s3c2440-sdi",
+ .driver.owner = THIS_MODULE,
+ .probe = s3cmci_2440_probe,
.remove = __devexit_p(s3cmci_remove),
.shutdown = s3cmci_shutdown,
+ .suspend = s3cmci_suspend,
+ .resume = s3cmci_resume,
};
+
static int __init s3cmci_init(void)
{
- return platform_driver_register(&s3cmci_driver);
+ platform_driver_register(&s3cmci_2410_driver);
+ platform_driver_register(&s3cmci_2412_driver);
+ platform_driver_register(&s3cmci_2440_driver);
+ return 0;
}
static void __exit s3cmci_exit(void)
{
- platform_driver_unregister(&s3cmci_driver);
+ platform_driver_unregister(&s3cmci_2410_driver);
+ platform_driver_unregister(&s3cmci_2412_driver);
+ platform_driver_unregister(&s3cmci_2440_driver);
}
module_init(s3cmci_init);
@@ -1931,3 +1564,6 @@ module_exit(s3cmci_exit);
MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
+MODULE_ALIAS("platform:s3c2410-sdi");
+MODULE_ALIAS("platform:s3c2412-sdi");
+MODULE_ALIAS("platform:s3c2440-sdi");
diff --git a/drivers/mmc/host/s3cmci.h b/drivers/mmc/host/s3cmci.h
index c76b53d..ca1ba3d 100644
--- a/drivers/mmc/host/s3cmci.h
+++ b/drivers/mmc/host/s3cmci.h
@@ -8,6 +8,9 @@
* published by the Free Software Foundation.
*/
+/* FIXME: DMA Resource management ?! */
+#define S3CMCI_DMA 0
+
enum s3cmci_waitfor {
COMPLETION_NONE,
COMPLETION_FINALIZE,
@@ -39,11 +42,6 @@ struct s3cmci_host {
int dodma;
int dmatogo;
- bool irq_disabled;
- bool irq_enabled;
- bool irq_state;
- int sdio_irqen;
-
struct mmc_request *mrq;
int cmd_is_stop;
@@ -70,12 +68,6 @@ struct s3cmci_host {
unsigned int ccnt, dcnt;
struct tasklet_struct pio_tasklet;
-#ifdef CONFIG_DEBUG_FS
- struct dentry *debug_root;
- struct dentry *debug_state;
- struct dentry *debug_regs;
-#endif
-
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
#endif
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index eaf3636..e486cb2 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -142,6 +142,8 @@ struct mmc_host {
unsigned long caps; /* Host capabilities */
#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */
+#define MMC_CAP_MULTIWRITE (1 << 1) /* Can accurately report bytes sent to card on error */
+#define MMC_CAP_BYTEBLOCK (1 << 2) /* Can do non-log2 block sizes */
#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */
#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */
#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */
--
1.5.6.1
From f5a4da2aca0aa0ed9a878a9242b46d360498c1db Mon Sep 17 00:00:00 2001
From: Ferar Achkar <ferarachkar@gmail.com>
Date: Tue, 6 Apr 2010 10:03:40 -0400
Subject: [PATCH] 1. fixed section mismatch related stuff
---
.../mach-s3c2410/include/mach/regs-s3c2450-clock.h | 224 ++++++++++++++++++++
1 files changed, 224 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-s3c2410/include/mach/regs-s3c2450-clock.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2450-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2450-clock.h
new file mode 100644
index 0000000..f587686
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2450-clock.h
@@ -0,0 +1,224 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-clock.h
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2443 clock register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
+#define __ASM_ARM_REGS_S3C2443_CLOCK
+
+#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
+
+#define S3C2443_PLLCON_MDIVSHIFT 14
+#define S3C2443_PLLCON_PDIVSHIFT 5
+#define S3C2443_PLLCON_SDIVSHIFT 0
+#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-14)))-1)
+#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(10-5)))-1)
+#define S3C2443_PLLCON_SDIVMASK (7)
+
+#define S3C2443_EPLLCON_MDIVSHIFT 16
+#define S3C2443_EPLLCON_PDIVSHIFT 8
+#define S3C2443_EPLLCON_SDIVSHIFT 0
+#define S3C2443_EPLLCON_MDIVMASK ((1<<(1+(23-16)))-1)
+#define S3C2443_EPLLCON_PDIVMASK ((1<<(1+(13-8)))-1)
+#define S3C2443_EPLLCON_SDIVMASK (7)
+
+#define S3C2443_LOCKCON0 S3C2443_CLKREG(0x00)
+#define S3C2443_LOCKCON1 S3C2443_CLKREG(0x04)
+#define S3C2443_OSCSET S3C2443_CLKREG(0x08)
+#define S3C2443_MPLLCON S3C2443_CLKREG(0x10)
+#define S3C2443_EPLLCON S3C2443_CLKREG(0x18)
+#define S3C2450_EPLLCON_K S3C2443_CLKREG(0x1C)
+#define S3C2443_CLKSRC S3C2443_CLKREG(0x20)
+#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24)
+#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28)
+#define S3C2443_CLKDIV2 S3C2443_CLKREG(0x2C)
+#define S3C2443_HCLKCON S3C2443_CLKREG(0x30)
+#define S3C2443_PCLKCON S3C2443_CLKREG(0x34)
+#define S3C2443_SCLKCON S3C2443_CLKREG(0x38)
+#define S3C2443_PWRMODE S3C2443_CLKREG(0x40)
+#define S3C2443_SWRST S3C2443_CLKREG(0x44)
+#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50)
+#define S3C2443_SYSID S3C2443_CLKREG(0x5C)
+#define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
+#define S3C2443_RSTCON S3C2443_CLKREG(0x64)
+#define S3C2443_RSTSTAT S3C2443_CLKREG(0x68)
+#define S3C2443_INFORM0 S3C2443_CLKREG(0x70)
+#define S3C2443_INFORM1 S3C2443_CLKREG(0x74)
+#define S3C2443_INFORM2 S3C2443_CLKREG(0x78)
+#define S3C2443_INFORM3 S3C2443_CLKREG(0x7C)
+#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80)
+#define S3C2443_PHYPWR S3C2443_CLKREG(0x84)
+#define S3C2443_URSTCON S3C2443_CLKREG(0x88)
+#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C)
+
+#define S3C2443_SWRST_RESET (0x533c2443)
+
+#define S3C2443_PLLCON_OFF (1<<24)
+
+#define S3C2443_CLKSRC_I2S_EXT (1<<14)
+#define S3C2443_CLKSRC_I2S_EPLLDIV (0<<14)
+#define S3C2443_CLKSRC_I2S_EPLLREF (2<<14)
+#define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14)
+#define S3C2443_CLKSRC_I2S_MASK (3<<14)
+
+#define S3C2450_CLKSRC_I2S1_EPLL (0<<12)
+#define S3C2450_CLKSRC_I2S1_EXT (1<<12)
+#define S3C2450_CLKSRC_I2S1_EPLLREF (2<<12)
+
+#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<8)
+#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<8)
+#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<8)
+#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<8)
+#define S3C2443_CLKSRC_EPLLREF_MASK (3<<8)
+
+#define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6)
+#define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4)
+#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3)
+
+#define S3C2443_CLKDIV0_DVS (1<<13)
+#define S3C2443_CLKDIV0_HALF_HCLK (1<<3)
+#define S3C2443_CLKDIV0_HALF_PCLK (1<<2)
+
+#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0)
+
+#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6)
+#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6)
+
+#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
+#define S3C2443_CLKDIV0_PREDIV_SHIFT (4)
+
+#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
+#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
+
+#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
+#define S3C2443_CLKDIV0_ARMDIV_2 (1<<9)
+#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
+#define S3C2443_CLKDIV0_ARMDIV_4 (3<<9)
+#define S3C2443_CLKDIV0_ARMDIV_6 (5<<9)
+#define S3C2443_CLKDIV0_ARMDIV_8 (7<<9)
+#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
+#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
+
+/* S3C2443_CLKDIV1 */
+
+#define S3C2443_CLKDIV1_CAMDIV_MASK (15<<26)
+#define S3C2443_CLKDIV1_CAMDIV_SHIFT (26)
+
+#define S3C2443_CLKDIV1_HSSPIDIV_MASK (3<<24)
+#define S3C2443_CLKDIV1_HSSPIDIV_SHIFT (24)
+
+#define S3C2443_CLKDIV1_DISPDIV_MASK (0xff<<16)
+#define S3C2443_CLKDIV1_DISPDIV_SHIFT (16)
+
+#define S3C2443_CLKDIV1_I2SDIV_MASK (15<<12)
+#define S3C2443_CLKDIV1_I2SDIV_SHIFT (12)
+
+#define S3C2443_CLKDIV1_UARTDIV_MASK (15<<8)
+#define S3C2443_CLKDIV1_UARTDIV_SHIFT (8)
+
+#define S3C2443_CLKDIV1_HSMMCDIV_MASK (3<<6)
+#define S3C2443_CLKDIV1_HSMMCDIV_SHIFT (6)
+
+#define S3C2443_CLKDIV1_USBHOSTDIV_MASK (3<<4)
+#define S3C2443_CLKDIV1_USBHOSTDIV_SHIFT (4)
+
+#define S3C2443_CLKCON_NAND
+
+#define S3C2443_HCLKCON_DMA0 (1<<0)
+#define S3C2443_HCLKCON_DMA1 (1<<1)
+#define S3C2443_HCLKCON_DMA2 (1<<2)
+#define S3C2443_HCLKCON_DMA3 (1<<3)
+#define S3C2443_HCLKCON_DMA4 (1<<4)
+#define S3C2443_HCLKCON_DMA5 (1<<5)
+#define S3C2443_HCLKCON_DMA6 (1<<6)
+#define S3C2443_HCLKCON_DMA7 (1<<7)
+#define S3C2443_HCLKCON_CAMIF (1<<8)
+#define S3C2443_HCLKCON_DISP (1<<9)
+#define S3C2443_HCLKCON_LCDC (1<<10)
+#define S3C2443_HCLKCON_USBH (1<<11)
+#define S3C2443_HCLKCON_USBD (1<<12)
+#define S3C2443_HCLKCON_HSMMC (1<<16)
+#define S3C2443_HCLKCON_CFC (1<<17)
+#define S3C2443_HCLKCON_SSMC (1<<18)
+#define S3C2443_HCLKCON_DRAMC (1<<19)
+
+#define S3C2443_PCLKCON_UART0 (1<<0)
+#define S3C2443_PCLKCON_UART1 (1<<1)
+#define S3C2443_PCLKCON_UART2 (1<<2)
+#define S3C2443_PCLKCON_UART3 (1<<3)
+#define S3C2443_PCLKCON_IIC (1<<4)
+#define S3C2443_PCLKCON_SDI (1<<5)
+#define S3C2443_PCLKCON_ADC (1<<7)
+#define S3C2443_PCLKCON_IIS (1<<9)
+#define S3C2443_PCLKCON_PWMT (1<<10)
+#define S3C2443_PCLKCON_WDT (1<<11)
+#define S3C2443_PCLKCON_RTC (1<<12)
+#define S3C2443_PCLKCON_GPIO (1<<13)
+#define S3C2443_PCLKCON_SPI0 (1<<14)
+#define S3C2443_PCLKCON_SPI1 (1<<15)
+
+#define S3C2443_SCLKCON_DDRCLK (1<<16)
+#define S3C2443_SCLKCON_SSMCCLK (1<<15)
+#define S3C2443_SCLKCON_HSSPICLK (1<<14)
+#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13)
+#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12)
+#define S3C2443_SCLKCON_CAMCLK (1<<11)
+#define S3C2443_SCLKCON_DISPCLK (1<<10)
+#define S3C2443_SCLKCON_I2SCLK (1<<9)
+#define S3C2443_SCLKCON_UARTCLK (1<<8)
+#define S3C2443_SCLKCON_I2SCLK_1 (1<<5)
+#define S3C2443_SCLKCON_USBHOST (1<<1)
+
+#include <asm/div64.h>
+
+static inline unsigned int
+s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
+{
+ unsigned int mdiv, pdiv, sdiv;
+ uint64_t fvco;
+
+ mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
+ pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
+ sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
+
+ mdiv &= S3C2443_PLLCON_MDIVMASK;
+ pdiv &= S3C2443_PLLCON_PDIVMASK;
+ sdiv &= S3C2443_PLLCON_SDIVMASK;
+
+ fvco = (uint64_t)baseclk * (mdiv);
+
+ do_div(fvco, pdiv << sdiv);
+
+ return (unsigned int)fvco;
+}
+
+static inline unsigned int
+s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
+{
+ unsigned int mdiv, pdiv, sdiv;
+ uint64_t fvco;
+
+ mdiv = pllval >> S3C2443_EPLLCON_MDIVSHIFT;
+ pdiv = pllval >> S3C2443_EPLLCON_PDIVSHIFT;
+ sdiv = pllval >> S3C2443_EPLLCON_SDIVSHIFT;
+
+ mdiv &= S3C2443_EPLLCON_MDIVMASK;
+ pdiv &= S3C2443_EPLLCON_PDIVMASK;
+ sdiv &= S3C2443_EPLLCON_SDIVMASK;
+
+ fvco = (uint64_t)baseclk * (mdiv);
+ do_div(fvco, pdiv << sdiv);
+
+ return (unsigned int)fvco;
+}
+
+#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */
+
--
1.5.6.1
From 0d827ded5de5e9ac97bb331e11abb73347470687 Mon Sep 17 00:00:00 2001
From: Ferar Achkar <ferarachkar@gmail.com>
Date: Tue, 6 Apr 2010 10:10:59 -0400
Subject: [PATCH] 1. commiting changes
---
arch/arm/mach-s3c2410/include/mach/regs-gpio.h | 8 ++++++++
arch/arm/mach-s3c2410/include/mach/regs-irq.h | 8 ++++++++
arch/arm/mach-s3c2450/dma.c | 2 +-
arch/arm/plat-s3c/include/plat/devs.h | 8 +++++++-
4 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index f6e8eec..33d8612 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -404,32 +404,38 @@
#define S3C2410_GPE5_SDCLK (0x02 << 10)
#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
+#define S3C2450_GPE5_SD0_CLK (0x02 << 10)
#define S3C2400_GPE5_EINT5 (0x02 << 10)
#define S3C2400_GPE5_TCLK1 (0x03 << 10)
#define S3C2410_GPE6_SDCMD (0x02 << 12)
#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
+#define S3C2450_GPE6_SD0_CMD (0x02 << 12)
#define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
#define S3C2400_GPE6_EINT6 (0x02 << 12)
#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
+#define S3C2450_GPE7_SD0_DAT0 (0x02 << 14)
#define S3C2443_GPE7_AC_SDI (0x03 << 14)
#define S3C2400_GPE7_EINT7 (0x02 << 14)
#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
+#define S3C2450_GPE8_SD0_DAT1 (0x02 << 16)
#define S3C2443_GPE8_AC_SDO (0x03 << 16)
#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
+#define S3C2450_GPE9_SD0_DAT2 (0x02 << 18)
#define S3C2443_GPE9_AC_SYNC (0x03 << 18)
#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
#define S3C2400_GPE9_nXBACK (0x03 << 18)
#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
+#define S3C2450_GPE10_SD0_DAT3 (0x02 << 20)
#define S3C2443_GPE10_AC_nRESET (0x03 << 20)
#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
@@ -597,6 +603,8 @@
#define S3C2410_GPG_PUPDIS(x) (1<<(x))
+#define S3C2410_GPIO_BANKJ (32*13)
+#define S3C2410_GPIO_BANKL (32*15)
/* Port H consists of11 GPIO/serial/Misc pins
*
* GPGCON has 2 bits for each of the input pins on port F
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
index de86ee8..e56ce1b 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-irq.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
@@ -27,6 +27,14 @@
#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
+#if defined(CONFIG_CPU_S3C2450)
+#define S3C2450_SRCPND S3C2410_IRQREG(0x040)
+#define S3C2450_INTMOD S3C2410_IRQREG(0x044)
+#define S3C2450_INTMSK S3C2410_IRQREG(0x048)
+#define S3C2450_INTPND S3C2410_IRQREG(0x050)
+#define S3C2450_INTOFFSET S3C2410_IRQREG(0x054)
+#define S3C2450_PRIORITY S3C2410_IRQREG(0x070)
+#endif
/* mask: 0=enable, 1=disable
* 1 bit EINT, 4=EINT4, 23=EINT23
* EINT0,1,2,3 are not handled here.
diff --git a/arch/arm/mach-s3c2450/dma.c b/arch/arm/mach-s3c2450/dma.c
index 60fd9d3..473bea1 100644
--- a/arch/arm/mach-s3c2450/dma.c
+++ b/arch/arm/mach-s3c2450/dma.c
@@ -177,7 +177,7 @@ static struct s3c24xx_dma_selection __initdata s3c2450_dma_sel = {
.map_size = ARRAY_SIZE(s3c2450_dma_mappings),
};
-static int s3c2450_dma_add(struct sys_device *sysdev)
+static int __init s3c2450_dma_add(struct sys_device *sysdev)
{
s3c24xx_dma_init(8, IRQ_S3C2443_DMA0, 0x100);
return s3c24xx_dma_init_map(&s3c2450_dma_sel);
diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h
index 46fc3dd..2aef57d 100644
--- a/arch/arm/plat-s3c/include/plat/devs.h
+++ b/arch/arm/plat-s3c/include/plat/devs.h
@@ -53,7 +53,13 @@ extern struct platform_device s3c_device_nand;
extern struct platform_device s3c_device_usbgadget;
extern struct platform_device s3c_device_usb_hsotg;
-
+#if defined (CONFIG_CPU_S3C2450)
+extern struct platform_device s3c_device_smc911x;
+extern struct platform_device s3c_device_ide;
+extern struct platform_device s3c_device_camif;
+extern struct flash_platform_data s3c_onenand_data;
+extern struct platform_device s3c_device_onenand;
+#endif
/* s3c2440 specific devices */
#ifdef CONFIG_CPU_S3C2440
--
1.5.6.1
From ab2b26d760d02cca99d16b03ad143b38745e050c Mon Sep 17 00:00:00 2001
From: Ferar Achkar <ferarachkar@gmail.com>
Date: Tue, 6 Apr 2010 10:30:21 -0400
Subject: [PATCH] 1. deleted a dummy test file
2. removed that file from the makefile
---
arch/arm/mach-s3c2450/Makefile | 1 -
arch/arm/mach-s3c2450/maino.c | 49 ----------------------------------------
2 files changed, 0 insertions(+), 50 deletions(-)
delete mode 100644 arch/arm/mach-s3c2450/maino.c
diff --git a/arch/arm/mach-s3c2450/Makefile b/arch/arm/mach-s3c2450/Makefile
index 4c8267d..9d7fa59 100644
--- a/arch/arm/mach-s3c2450/Makefile
+++ b/arch/arm/mach-s3c2450/Makefile
@@ -18,4 +18,3 @@ obj-$(CONFIG_S3C2450_PM) += pm.o
# Machine support
obj-$(CONFIG_MACH_SMDK2450) += mach-smdk2450.o
-# obj-$(CONFIG_MACH_SMDK2450) += maino.o
\ No newline at end of file
diff --git a/arch/arm/mach-s3c2450/maino.c b/arch/arm/mach-s3c2450/maino.c
deleted file mode 100644
index 28d5f9b..0000000
--- a/arch/arm/mach-s3c2450/maino.c
+++ /dev/null
@@ -1,49 +0,0 @@
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <asm/setup.h>
-#include <mach/hardware.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <plat/regs-serial.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-gpioj.h>
-#include <mach/regs-lcd.h>
-#include <mach/regs-mem.h>
-
-#include <mach/idle.h>
-#include <mach/fb.h>
-#include <plat/iic.h>
-
-#include <plat/s3c2410.h>
-#include <plat/s3c2440.h>
-#include <plat/clock.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-
-#include <plat/common-smdk.h>
-
-#include <plat/nand.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
-#include <mach/hsmmc.h>
-int maino() {
- unsigned int i=IRQ_S3C2443_DMA6;
- sprintf("%d\n", i);
- return 0;
-}
-
--
1.5.6.1
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment