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//===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the RISC-V instructions in TableGen format.

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[RFC] Addressing the problems with opaque floating point encodings in F/D/Q

Alex Bradbury, lowRISC CIC

Brief problem summary

The current version of the RISC-V ISA specification explicitly leaves the encoding of a single precision value undefined when it is either converted to a wider integer register or written to a wider memory location (e.g. a float written with fsd or fmv.x.d. The motivation for this is to allow a low overhead internal recoding. Unfortunately, the freedom to keep this

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diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 2ccb459..6f92eeb 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -6651,6 +6651,57 @@ ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+// RISC-V Target
+// TODO: need to handle 64-bit as well as 32-bit

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#!/bin/sh
# File:            scratch
# Description:     Script to start the Cog Stack VM binary with the nuscratch image
# Original Author: Bert Freudenberg
# Adapted by:      Miriam Ruiz, Alex Bradbury

VM="/usr/bin/squeak-stack"
VMOPTIONS=""
IMAGE="/usr/share/scratch/NuScratchBeta15.image"
IMOPTIONS=""

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#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 3.1.9 Kernel Configuration
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_KTIME_SCALAR=y