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msp430 isr minimal
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msp430-gcc -Os -fno-strict-aliasing -g -Wall -mmcu=msp430f5438 -std=gnu99 -c -o isr.o isr.c | |
msp430-ar rcf mylib.a isr.o | |
msp430-gcc -Os -fno-strict-aliasing -g -Wall -mmcu=msp430f5438 -std=gnu99 main.c mylib.a -o main-lib.elf |
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msp430-gcc -Os -fno-strict-aliasing -g -Wall -mmcu=msp430f5438 -std=gnu99 -c -o isr.o isr.c | |
msp430-gcc -Os -fno-strict-aliasing -g -Wall -mmcu=msp430f5438 -std=gnu99 -c -o main.o main.c | |
msp430-gcc ./isr.o ./main.o -mmcu=msp430f5438 -o "main-nolib.elf" |
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#include <msp430.h> | |
#define IRQPRAGMA(VAL) __attribute__((interrupt(VAL))) | |
IRQPRAGMA(PORT2_VECTOR) | |
void isr_port2(void) { | |
P1DIR = 1; | |
} |
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int main() { | |
return 0 | |
} |
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main-lib.elf: file format elf32-msp430 | |
Disassembly of section .text: | |
00005c00 <__watchdog_support>: | |
__watchdog_support: | |
#if WITH_DISABLE_WDT | |
mov #0x5a80, &__WDTCTL | |
#else /* WITH_DISABLE_WDT */ | |
mov.b &__WDTCTL, r5 | |
5c00: 55 42 5c 01 mov.b &0x015c,r5 | |
bis #0x5a08, r5 | |
5c04: 35 d0 08 5a bis #23048, r5 ;#0x5a08 | |
mov r5, &__wdt_clear_value | |
5c08: 82 45 00 1c mov r5, &0x1c00 | |
00005c0c <__init_stack>: | |
.weak __init_stack | |
.func __init_stack | |
__init_stack: | |
mov #__stack, r1 | |
5c0c: 31 40 00 5c mov #23552, r1 ;#0x5c00 | |
00005c10 <__do_copy_data>: | |
.weak __do_copy_data | |
.func __do_copy_data | |
__do_copy_data: | |
mov #__data_size, r15 | |
5c10: 3f 40 00 00 mov #0, r15 ;#0x0000 | |
tst r15 | |
5c14: 0f 93 tst r15 | |
jz .L__copy_data_end | |
5c16: 08 24 jz $+18 ;abs 0x5c28 | |
.L__copy_data_loop: | |
WDTIMER_KICK | |
5c18: 92 42 00 1c mov &0x1c00,&0x015c | |
5c1c: 5c 01 | |
decd r15 | |
5c1e: 2f 83 decd r15 | |
mov.w __data_load_start(r15), __data_start(r15) ; data section is word-aligned, so word transfer is acceptable | |
5c20: 9f 4f 4c 5c mov 23628(r15),7168(r15);0x5c4c(r15), 0x1c00(r15) | |
5c24: 00 1c | |
jne .L__copy_data_loop | |
5c26: f8 23 jnz $-14 ;abs 0x5c18 | |
00005c28 <__do_clear_bss>: | |
.weak __do_clear_bss | |
.func __do_clear_bss | |
__do_clear_bss: | |
mov #__bss_size, r15 | |
5c28: 3f 40 00 00 mov #0, r15 ;#0x0000 | |
tst r15 | |
5c2c: 0f 93 tst r15 | |
jz .L__clear_bss_end | |
5c2e: 07 24 jz $+16 ;abs 0x5c3e | |
.L__clear_bss_loop: | |
WDTIMER_KICK | |
5c30: 92 42 00 1c mov &0x1c00,&0x015c | |
5c34: 5c 01 | |
dec r15 | |
5c36: 1f 83 dec r15 | |
clr.b __bss_start(r15) | |
5c38: cf 43 00 1c mov.b #0, 7168(r15);r3 As==00, 0x1c00(r15) | |
jne .L__clear_bss_loop | |
5c3c: f9 23 jnz $-12 ;abs 0x5c30 | |
00005c3e <main>: | |
int main() { | |
return 0; | |
} | |
5c3e: 0f 43 clr r15 | |
00005c40 <__stop_progExec__>: | |
.global _endless_loop__ | |
.weak _endless_loop__ | |
.func _endless_loop__ | |
_endless_loop__: | |
bis #0xf0, r2 | |
5c40: 32 d0 f0 00 bis #240, r2 ;#0x00f0 | |
jmp _endless_loop__ | |
5c44: fd 3f jmp $-4 ;abs 0x5c40 | |
00005c46 <__ctors_end>: | |
5c46: 30 40 4a 5c br #0x5c4a | |
00005c4a <_unexpected_>: | |
.global _unexpected_ | |
.weak _unexpected_ | |
.p2align 1,0 | |
_unexpected_: | |
reti | |
5c4a: 00 13 reti | |
Disassembly of section .vectors: | |
0000ff80 <__ivtbl_64>: | |
ff80: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
ff90: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
ffa0: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
ffb0: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
ffc0: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
ffd0: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
ffe0: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
fff0: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 00 5c F\F\F\F\F\F\F\.\ |
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main-nolib.elf: file format elf32-msp430 | |
Disassembly of section .text: | |
00005c00 <__watchdog_support>: | |
__watchdog_support: | |
#if WITH_DISABLE_WDT | |
mov #0x5a80, &__WDTCTL | |
#else /* WITH_DISABLE_WDT */ | |
mov.b &__WDTCTL, r5 | |
5c00: 55 42 5c 01 mov.b &0x015c,r5 | |
bis #0x5a08, r5 | |
5c04: 35 d0 08 5a bis #23048, r5 ;#0x5a08 | |
mov r5, &__wdt_clear_value | |
5c08: 82 45 00 1c mov r5, &0x1c00 | |
00005c0c <__init_stack>: | |
.weak __init_stack | |
.func __init_stack | |
__init_stack: | |
mov #__stack, r1 | |
5c0c: 31 40 00 5c mov #23552, r1 ;#0x5c00 | |
00005c10 <__do_copy_data>: | |
.weak __do_copy_data | |
.func __do_copy_data | |
__do_copy_data: | |
mov #__data_size, r15 | |
5c10: 3f 40 00 00 mov #0, r15 ;#0x0000 | |
tst r15 | |
5c14: 0f 93 tst r15 | |
jz .L__copy_data_end | |
5c16: 08 24 jz $+18 ;abs 0x5c28 | |
.L__copy_data_loop: | |
WDTIMER_KICK | |
5c18: 92 42 00 1c mov &0x1c00,&0x015c | |
5c1c: 5c 01 | |
decd r15 | |
5c1e: 2f 83 decd r15 | |
mov.w __data_load_start(r15), __data_start(r15) ; data section is word-aligned, so word transfer is acceptable | |
5c20: 9f 4f 52 5c mov 23634(r15),7168(r15);0x5c52(r15), 0x1c00(r15) | |
5c24: 00 1c | |
jne .L__copy_data_loop | |
5c26: f8 23 jnz $-14 ;abs 0x5c18 | |
00005c28 <__do_clear_bss>: | |
.weak __do_clear_bss | |
.func __do_clear_bss | |
__do_clear_bss: | |
mov #__bss_size, r15 | |
5c28: 3f 40 00 00 mov #0, r15 ;#0x0000 | |
tst r15 | |
5c2c: 0f 93 tst r15 | |
jz .L__clear_bss_end | |
5c2e: 07 24 jz $+16 ;abs 0x5c3e | |
.L__clear_bss_loop: | |
WDTIMER_KICK | |
5c30: 92 42 00 1c mov &0x1c00,&0x015c | |
5c34: 5c 01 | |
dec r15 | |
5c36: 1f 83 dec r15 | |
clr.b __bss_start(r15) | |
5c38: cf 43 00 1c mov.b #0, 7168(r15);r3 As==00, 0x1c00(r15) | |
jne .L__clear_bss_loop | |
5c3c: f9 23 jnz $-12 ;abs 0x5c30 | |
00005c3e <main>: | |
int main() { | |
return 0; | |
} | |
5c3e: 0f 43 clr r15 | |
00005c40 <__stop_progExec__>: | |
.global _endless_loop__ | |
.weak _endless_loop__ | |
.func _endless_loop__ | |
_endless_loop__: | |
bis #0xf0, r2 | |
5c40: 32 d0 f0 00 bis #240, r2 ;#0x00f0 | |
jmp _endless_loop__ | |
5c44: fd 3f jmp $-4 ;abs 0x5c40 | |
00005c46 <__ctors_end>: | |
5c46: 30 40 50 5c br #0x5c50 | |
00005c4a <isr_port2>: | |
IRQPRAGMA(PORT2_VECTOR) | |
void isr_port2(void) { | |
P1DIR = 1; | |
5c4a: d2 43 04 02 mov.b #1, &0x0204 ;r3 As==01 | |
} | |
5c4e: 00 13 reti | |
00005c50 <_unexpected_>: | |
.global _unexpected_ | |
.weak _unexpected_ | |
.p2align 1,0 | |
_unexpected_: | |
reti | |
5c50: 00 13 reti | |
Disassembly of section .vectors: | |
0000ff80 <__ivtbl_64>: | |
ff80: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
ff90: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
ffa0: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
ffb0: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
ffc0: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
ffd0: 46 5c 46 5c 4a 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\J\F\F\F\F\F\ | |
ffe0: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c F\F\F\F\F\F\F\F\ | |
fff0: 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 46 5c 00 5c F\F\F\F\F\F\F\.\ |
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