fsm_err.py

from nmigen import *
import nmigen.back
from nmigen.cli import main

class MVCE(Elaboratable):
    def __init__(self):
        self.write_en = Signal()

    def elaborate(self, platform):
        m = Module()

        with m.FSM() as fsm:
            with m.State("A"):
                with m.If(~self.write_en):
                    m.next = "B"
                m.next = "C" # doesn't exist
            with m.State("B"):
                with m.If(self.write_en):
                    m.next = "A"

        return m

if __name__ == "__main__":
    m = MVCE()
    main(m, ports=(m.write_en))
    
    print(nmigen.back.verilog.convert(m, ports=[m.write_en]))