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# FSM | |
#with m.FSM(reset="IDLE", domain="scope") as fsm: | |
# with m.State("IDLE"): | |
# m.d.scope += done.eq(1) | |
# with m.If(enable & ~enable_d): | |
# m.next = "FLUSH" | |
# m.d.scope += self.sink.ready.eq(1) | |
# m.d.scope += mem.source.connect(cdc.sink) | |
# with m.State("FLUSH"): | |
# m.d.scope += self.sink.ready.eq(1), | |
# m.d.scope += mem_flush.wait.eq(1) | |
# m.d.scope += mem.source.ready.eq(1) | |
# with m.If(mem_flush.done): | |
# m.next = "WAIT" | |
# with m.State("WAIT"): | |
# m.d.scope += self.sink.connect(mem.sink, omit={"hit"}) | |
# with m.If(self.sink.valid & self.sink.hit): | |
# m.next = "RUN" | |
# m.d.scope += mem.source.ready.eq(mem.level >= self.offset) | |
# with m.State("RUN"): | |
# m.d.scope += self.sink.connect(mem.sink, omit={"hit"}) | |
# with m.If(mem.level >= self.length): | |
# m.next = "IDLE" | |
fsm = nmigen.compat.genlib.fsm.FSM(reset_state="IDLE") | |
fsm = DomainRenamer("scope")(fsm) | |
m.submodules += fsm | |
fsm.act("IDLE", | |
done.eq(1), | |
If(enable & ~enable_d, | |
NextState("FLUSH") | |
), | |
self.sink.ready.eq(1), | |
mem.source.connect(cdc.sink) | |
) | |
fsm.act("FLUSH", | |
self.sink.ready.eq(1), | |
mem_flush.wait.eq(1), | |
mem.source.ready.eq(1), | |
If(mem_flush.done, | |
NextState("WAIT") | |
) | |
) | |
fsm.act("WAIT", | |
self.sink.connect(mem.sink, omit={"hit"}), | |
If(self.sink.valid & self.sink.hit, | |
NextState("RUN") | |
), | |
mem.source.ready.eq(mem.level >= self.offset) | |
) | |
fsm.act("RUN", | |
self.sink.connect(mem.sink, omit={"hit"}), | |
If(mem.level >= self.length, | |
NextState("IDLE"), | |
) | |
) |
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