Skip to content

Instantly share code, notes, and snippets.

@awygle

awygle/nextpnr.log

Created June 29, 2020 20:33
Show Gist options
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save awygle/bbbbbe24b4621a22473bfada16b262c6 to your computer and use it in GitHub Desktop.
Save awygle/bbbbbe24b4621a22473bfada16b262c6 to your computer and use it in GitHub Desktop.
Download ZIP
Raw
nextpnr.log
+ [ -n ]
+ : yosys
+ : nextpnr-ecp5
+ : ecppack
+ yosys -l top.rpt top.ys
+ nextpnr-ecp5 --log top.tim --12k --package CABGA256 --speed 6 --json top.json --lpf top.lpf --textcfg top.config
Info: Logic utilisation before packing:
Info: Total LUT4s: 10455/24288 43%
Info: logic LUTs: 5207/24288 21%
Info: carry LUTs: 688/24288 2%
Info: RAM LUTs: 3040/12144 25%
Info: RAMW LUTs: 1520/ 6072 25%
Info: Total DFFs: 1570/24288 6%
Info: Packing IOs..
Info: sram_0__cs__io feeds TRELLIS_IO pin_sram_0__cs.sram_0__cs_0, removing $nextpnr_obuf sram_0__cs__io.
Info: pin 'pin_sram_0__cs.sram_0__cs_0' constrained to Bel 'X72/Y26/PIOB'.
Info: sram_0__oe__io feeds TRELLIS_IO pin_sram_0__oe.sram_0__oe_0, removing $nextpnr_obuf sram_0__oe__io.
Info: pin 'pin_sram_0__oe.sram_0__oe_0' constrained to Bel 'X72/Y41/PIOB'.
Info: sram_0__we__io feeds TRELLIS_IO pin_sram_0__we.sram_0__we_0, removing $nextpnr_obuf sram_0__we__io.
Info: pin 'pin_sram_0__we.sram_0__we_0' constrained to Bel 'X72/Y23/PIOD'.
Info: uart_0__rx__io feeds TRELLIS_IO pin_uart_0__rx.uart_0__rx_0, removing $nextpnr_ibuf uart_0__rx__io.
Info: pin 'pin_uart_0__rx.uart_0__rx_0' constrained to Bel 'X72/Y14/PIOC'.
Info: uart_0__tx__io feeds TRELLIS_IO pin_uart_0__tx.uart_0__tx_0, removing $nextpnr_obuf uart_0__tx__io.
Info: pin 'pin_uart_0__tx.uart_0__tx_0' constrained to Bel 'X72/Y14/PIOD'.
Info: sram_0__a__io[0] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_0, removing $nextpnr_obuf sram_0__a__io[0].
Info: pin 'pin_sram_0__a.sram_0__a_0' constrained to Bel 'X72/Y44/PIOA'.
Info: sram_0__a__io[1] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_1, removing $nextpnr_obuf sram_0__a__io[1].
Info: pin 'pin_sram_0__a.sram_0__a_1' constrained to Bel 'X72/Y41/PIOC'.
Info: sram_0__a__io[10] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_10, removing $nextpnr_obuf sram_0__a__io[10].
Info: pin 'pin_sram_0__a.sram_0__a_10' constrained to Bel 'X72/Y23/PIOC'.
Info: sram_0__a__io[11] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_11, removing $nextpnr_obuf sram_0__a__io[11].
Info: pin 'pin_sram_0__a.sram_0__a_11' constrained to Bel 'X72/Y26/PIOC'.
Info: sram_0__a__io[12] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_12, removing $nextpnr_obuf sram_0__a__io[12].
Info: pin 'pin_sram_0__a.sram_0__a_12' constrained to Bel 'X72/Y26/PIOD'.
Info: sram_0__a__io[13] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_13, removing $nextpnr_obuf sram_0__a__io[13].
Info: pin 'pin_sram_0__a.sram_0__a_13' constrained to Bel 'X72/Y32/PIOA'.
Info: sram_0__a__io[14] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_14, removing $nextpnr_obuf sram_0__a__io[14].
Info: pin 'pin_sram_0__a.sram_0__a_14' constrained to Bel 'X72/Y35/PIOA'.
Info: sram_0__a__io[15] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_15, removing $nextpnr_obuf sram_0__a__io[15].
Info: pin 'pin_sram_0__a.sram_0__a_15' constrained to Bel 'X72/Y32/PIOB'.
Info: sram_0__a__io[2] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_2, removing $nextpnr_obuf sram_0__a__io[2].
Info: pin 'pin_sram_0__a.sram_0__a_2' constrained to Bel 'X72/Y44/PIOB'.
Info: sram_0__a__io[3] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_3, removing $nextpnr_obuf sram_0__a__io[3].
Info: pin 'pin_sram_0__a.sram_0__a_3' constrained to Bel 'X72/Y44/PIOC'.
Info: sram_0__a__io[4] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_4, removing $nextpnr_obuf sram_0__a__io[4].
Info: pin 'pin_sram_0__a.sram_0__a_4' constrained to Bel 'X72/Y38/PIOA'.
Info: sram_0__a__io[5] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_5, removing $nextpnr_obuf sram_0__a__io[5].
Info: pin 'pin_sram_0__a.sram_0__a_5' constrained to Bel 'X72/Y38/PIOB'.
Info: sram_0__a__io[6] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_6, removing $nextpnr_obuf sram_0__a__io[6].
Info: pin 'pin_sram_0__a.sram_0__a_6' constrained to Bel 'X72/Y29/PIOD'.
Info: sram_0__a__io[7] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_7, removing $nextpnr_obuf sram_0__a__io[7].
Info: pin 'pin_sram_0__a.sram_0__a_7' constrained to Bel 'X72/Y20/PIOB'.
Info: sram_0__a__io[8] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_8, removing $nextpnr_obuf sram_0__a__io[8].
Info: pin 'pin_sram_0__a.sram_0__a_8' constrained to Bel 'X72/Y23/PIOA'.
Info: sram_0__a__io[9] feeds TRELLIS_IO pin_sram_0__a.sram_0__a_9, removing $nextpnr_obuf sram_0__a__io[9].
Info: pin 'pin_sram_0__a.sram_0__a_9' constrained to Bel 'X72/Y20/PIOC'.
Info: sram_0__d__io[0] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_0, removing $nextpnr_iobuf sram_0__d__io[0].
Info: pin 'pin_sram_0__d.sram_0__d_0' constrained to Bel 'X72/Y26/PIOA'.
Info: sram_0__d__io[1] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_1, removing $nextpnr_iobuf sram_0__d__io[1].
Info: pin 'pin_sram_0__d.sram_0__d_1' constrained to Bel 'X72/Y35/PIOD'.
Info: sram_0__d__io[10] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_10, removing $nextpnr_iobuf sram_0__d__io[10].
Info: pin 'pin_sram_0__d.sram_0__d_10' constrained to Bel 'X72/Y47/PIOD'.
Info: sram_0__d__io[11] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_11, removing $nextpnr_iobuf sram_0__d__io[11].
Info: pin 'pin_sram_0__d.sram_0__d_11' constrained to Bel 'X72/Y47/PIOB'.
Info: sram_0__d__io[12] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_12, removing $nextpnr_iobuf sram_0__d__io[12].
Info: pin 'pin_sram_0__d.sram_0__d_12' constrained to Bel 'X72/Y47/PIOC'.
Info: sram_0__d__io[13] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_13, removing $nextpnr_iobuf sram_0__d__io[13].
Info: pin 'pin_sram_0__d.sram_0__d_13' constrained to Bel 'X72/Y47/PIOA'.
Info: sram_0__d__io[14] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_14, removing $nextpnr_iobuf sram_0__d__io[14].
Info: pin 'pin_sram_0__d.sram_0__d_14' constrained to Bel 'X72/Y35/PIOB'.
Info: sram_0__d__io[15] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_15, removing $nextpnr_iobuf sram_0__d__io[15].
Info: pin 'pin_sram_0__d.sram_0__d_15' constrained to Bel 'X72/Y38/PIOD'.
Info: sram_0__d__io[2] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_2, removing $nextpnr_iobuf sram_0__d__io[2].
Info: pin 'pin_sram_0__d.sram_0__d_2' constrained to Bel 'X72/Y35/PIOC'.
Info: sram_0__d__io[3] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_3, removing $nextpnr_iobuf sram_0__d__io[3].
Info: pin 'pin_sram_0__d.sram_0__d_3' constrained to Bel 'X72/Y29/PIOC'.
Info: sram_0__d__io[4] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_4, removing $nextpnr_iobuf sram_0__d__io[4].
Info: pin 'pin_sram_0__d.sram_0__d_4' constrained to Bel 'X72/Y32/PIOD'.
Info: sram_0__d__io[5] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_5, removing $nextpnr_iobuf sram_0__d__io[5].
Info: pin 'pin_sram_0__d.sram_0__d_5' constrained to Bel 'X72/Y29/PIOB'.
Info: sram_0__d__io[6] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_6, removing $nextpnr_iobuf sram_0__d__io[6].
Info: pin 'pin_sram_0__d.sram_0__d_6' constrained to Bel 'X72/Y32/PIOC'.
Info: sram_0__d__io[7] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_7, removing $nextpnr_iobuf sram_0__d__io[7].
Info: pin 'pin_sram_0__d.sram_0__d_7' constrained to Bel 'X72/Y29/PIOA'.
Info: sram_0__d__io[8] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_8, removing $nextpnr_iobuf sram_0__d__io[8].
Info: pin 'pin_sram_0__d.sram_0__d_8' constrained to Bel 'X72/Y41/PIOA'.
Info: sram_0__d__io[9] feeds TRELLIS_IO pin_sram_0__d.sram_0__d_9, removing $nextpnr_iobuf sram_0__d__io[9].
Info: pin 'pin_sram_0__d.sram_0__d_9' constrained to Bel 'X72/Y44/PIOD'.
Info: sram_0__dm__io[0] feeds TRELLIS_IO pin_sram_0__dm.sram_0__dm_0, removing $nextpnr_obuf sram_0__dm__io[0].
Info: pin 'pin_sram_0__dm.sram_0__dm_0' constrained to Bel 'X72/Y38/PIOC'.
Info: sram_0__dm__io[1] feeds TRELLIS_IO pin_sram_0__dm.sram_0__dm_1, removing $nextpnr_obuf sram_0__dm__io[1].
Info: pin 'pin_sram_0__dm.sram_0__dm_1' constrained to Bel 'X72/Y41/PIOD'.
Info: Packing constants..
Info: Packing carries...
Info: Finding LUTFF pairs...
Info: Packing LUT5-7s...
Info: Finding LUT-LUT pairs...
Info: Packing paired LUTs into a SLICE...
Info: Packing unpaired LUTs into a SLICE...
Info: Packing unpaired FFs into a SLICE...
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net sram_clk to global network
Info: Checksum: 0xf4cd2a73
Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0xd5baff1f
Info: Device utilisation:
Info: TRELLIS_SLICE: 6140/12144 50%
Info: TRELLIS_IO: 39/ 197 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 5/ 56 8%
Info: MULT18X18D: 0/ 28 0%
Info: ALU54B: 0/ 14 0%
Info: EHXPLLL: 0/ 2 0%
Info: EXTREFB: 0/ 1 0%
Info: DCUA: 0/ 1 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 128 0%
Info: SIOLOGIC: 0/ 69 0%
Info: GSR: 1/ 1 100%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 1/ 1 100%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 8 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: Placed 40 cells based on constraints.
Info: Creating initial analytic placement for 3693 cells, random placement wirelen = 317637.
Info: at initial placer iter 0, wirelen = 1388
Info: at initial placer iter 1, wirelen = 1091
Info: at initial placer iter 2, wirelen = 1053
Info: at initial placer iter 3, wirelen = 1055
Info: Running main analytical placer.
Info: at iteration #1, type ALL: wirelen solved = 1050, spread = 87232, legal = 88646; time = 0.19s
Info: at iteration #2, type ALL: wirelen solved = 7701, spread = 64211, legal = 66059; time = 0.21s
Info: at iteration #3, type ALL: wirelen solved = 8546, spread = 58356, legal = 61091; time = 0.21s
Info: at iteration #4, type ALL: wirelen solved = 10874, spread = 66528, legal = 67670; time = 0.20s
Info: at iteration #5, type ALL: wirelen solved = 13987, spread = 58064, legal = 60429; time = 0.20s
Info: at iteration #6, type ALL: wirelen solved = 15655, spread = 55891, legal = 58664; time = 0.20s
Info: at iteration #7, type ALL: wirelen solved = 16516, spread = 55553, legal = 59082; time = 0.20s
Info: at iteration #8, type ALL: wirelen solved = 17429, spread = 54365, legal = 57869; time = 0.20s
Info: at iteration #9, type ALL: wirelen solved = 17925, spread = 55848, legal = 58147; time = 0.20s
Info: at iteration #10, type ALL: wirelen solved = 18583, spread = 57969, legal = 60762; time = 0.20s
Info: at iteration #11, type ALL: wirelen solved = 19622, spread = 56061, legal = 58368; time = 0.19s
Info: at iteration #12, type ALL: wirelen solved = 19642, spread = 54923, legal = 57722; time = 0.20s
Info: at iteration #13, type ALL: wirelen solved = 20616, spread = 55531, legal = 58601; time = 0.20s
Info: at iteration #14, type ALL: wirelen solved = 22199, spread = 54496, legal = 57216; time = 0.20s
Info: at iteration #15, type ALL: wirelen solved = 22794, spread = 53658, legal = 56555; time = 0.20s
Info: at iteration #16, type ALL: wirelen solved = 22485, spread = 53992, legal = 55942; time = 0.20s
Info: at iteration #17, type ALL: wirelen solved = 24118, spread = 52870, legal = 55422; time = 0.20s
Info: at iteration #18, type ALL: wirelen solved = 24392, spread = 52233, legal = 54546; time = 0.20s
Info: at iteration #19, type ALL: wirelen solved = 25274, spread = 51558, legal = 53780; time = 0.20s
Info: at iteration #20, type ALL: wirelen solved = 25389, spread = 51157, legal = 53369; time = 0.19s
Info: at iteration #21, type ALL: wirelen solved = 26463, spread = 50501, legal = 52361; time = 0.19s
Info: at iteration #22, type ALL: wirelen solved = 27284, spread = 50361, legal = 52179; time = 0.19s
Info: at iteration #23, type ALL: wirelen solved = 27183, spread = 50093, legal = 52219; time = 0.19s
Info: at iteration #24, type ALL: wirelen solved = 28061, spread = 49820, legal = 51791; time = 0.19s
Info: at iteration #25, type ALL: wirelen solved = 29086, spread = 49419, legal = 51884; time = 0.19s
Info: at iteration #26, type ALL: wirelen solved = 29870, spread = 49072, legal = 51226; time = 0.19s
Info: at iteration #27, type ALL: wirelen solved = 30222, spread = 49468, legal = 51683; time = 0.19s
Info: at iteration #28, type ALL: wirelen solved = 31319, spread = 49969, legal = 52110; time = 0.19s
Info: at iteration #29, type ALL: wirelen solved = 31405, spread = 49731, legal = 51994; time = 0.19s
Info: at iteration #30, type ALL: wirelen solved = 32045, spread = 49241, legal = 51840; time = 0.19s
Info: at iteration #31, type ALL: wirelen solved = 32420, spread = 48625, legal = 50546; time = 0.19s
Info: at iteration #32, type ALL: wirelen solved = 33353, spread = 49015, legal = 51185; time = 0.19s
Info: at iteration #33, type ALL: wirelen solved = 34542, spread = 49012, legal = 52281; time = 0.19s
Info: at iteration #34, type ALL: wirelen solved = 34355, spread = 48804, legal = 51129; time = 0.19s
Info: at iteration #35, type ALL: wirelen solved = 34861, spread = 48477, legal = 50545; time = 0.19s
Info: at iteration #36, type ALL: wirelen solved = 35244, spread = 48569, legal = 50970; time = 0.19s
Info: at iteration #37, type ALL: wirelen solved = 34874, spread = 48174, legal = 51148; time = 0.19s
Info: at iteration #38, type ALL: wirelen solved = 36076, spread = 48428, legal = 51368; time = 0.19s
Info: at iteration #39, type ALL: wirelen solved = 36549, spread = 49354, legal = 51923; time = 0.19s
Info: at iteration #40, type ALL: wirelen solved = 38511, spread = 51040, legal = 52475; time = 0.19s
Info: HeAP Placer Time: 13.46s
Info: of which solving equations: 6.53s
Info: of which spreading cells: 0.86s
Info: of which strict legalisation: 0.23s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 10621, wirelen = 50545
Info: at iteration #5: temp = 0.000000, timing cost = 7260, wirelen = 46779
Info: at iteration #10: temp = 0.000000, timing cost = 5028, wirelen = 45479
Info: at iteration #15: temp = 0.000000, timing cost = 5833, wirelen = 45113
Info: at iteration #19: temp = 0.000000, timing cost = 4903, wirelen = 45041
Info: SA placement time 7.42s
Info: Max frequency for clock '$glbnet$sram_clk': 41.42 MHz (PASS at 12.00 MHz)
Info: Max delay posedge $glbnet$sram_clk -> <async>: 13.96 ns
Info: Slack histogram:
Info: legend: * represents 6 endpoint(s)
Info: + represents [1,6) endpoint(s)
Info: [ 59191, 60336) |***+
Info: [ 60336, 61481) |**+
Info: [ 61481, 62626) |*******+
Info: [ 62626, 63771) |********************************+
Info: [ 63771, 64916) |****************************************************+
Info: [ 64916, 66061) |************************************************************
Info: [ 66061, 67206) |**********************************************************+
Info: [ 67206, 68351) |**********************************************+
Info: [ 68351, 69496) |*********************************+
Info: [ 69496, 70641) |************************+
Info: [ 70641, 71786) |*******************+
Info: [ 71786, 72931) |*********+
Info: [ 72931, 74076) |**************************+
Info: [ 74076, 75221) |*****************+
Info: [ 75221, 76366) |********************+
Info: [ 76366, 77511) |******************+
Info: [ 77511, 78656) |***************************+
Info: [ 78656, 79801) |**************************+
Info: [ 79801, 80946) |****************+
Info: [ 80946, 82091) |********+
Info: Checksum: 0x5ddaa182
Info: Routing globals...
Info: routing clock net $glbnet$sram_clk using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 54131 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 3 996 | 3 996 | 53136| 0.14 0.14|
Info: 2000 | 4 1995 | 1 999 | 52137| 0.08 0.22|
Info: 3000 | 7 2992 | 3 997 | 51145| 0.18 0.39|
Info: 4000 | 20 3979 | 13 987 | 50197| 0.17 0.57|
Info: 5000 | 28 4971 | 8 992 | 49226| 0.19 0.75|
Info: 6000 | 40 5959 | 12 988 | 48261| 0.19 0.94|
Info: 7000 | 55 6944 | 15 985 | 47399| 0.19 1.13|
Info: 8000 | 80 7919 | 25 975 | 46493| 0.23 1.36|
Info: 9000 | 98 8901 | 18 982 | 45657| 0.23 1.59|
Info: 10000 | 120 9879 | 22 978 | 44933| 0.24 1.82|
Info: 11000 | 147 10852 | 27 973 | 44333| 0.24 2.06|
Info: 12000 | 173 11826 | 26 974 | 43785| 0.23 2.30|
Info: 13000 | 203 12796 | 30 970 | 43231| 0.28 2.58|
Info: 14000 | 227 13772 | 24 976 | 42319| 0.27 2.85|
Info: 15000 | 251 14748 | 24 976 | 41407| 0.28 3.13|
Info: 16000 | 283 15716 | 32 968 | 40678| 0.28 3.40|
Info: 17000 | 337 16662 | 54 946 | 39964| 0.30 3.70|
Info: 18000 | 382 17617 | 45 955 | 41718| 0.34 4.04|
Info: 19000 | 402 18597 | 20 980 | 40834| 0.30 4.33|
Info: 20000 | 423 19576 | 21 979 | 40145| 0.34 4.67|
Info: 21000 | 456 20543 | 33 967 | 39218| 0.32 4.99|
Info: 22000 | 511 21488 | 55 945 | 39299| 0.33 5.32|
Info: 23000 | 559 22440 | 48 952 | 38459| 0.34 5.66|
Info: 24000 | 629 23370 | 70 930 | 37817| 0.35 6.01|
Info: 25000 | 713 24286 | 84 916 | 37127| 0.39 6.39|
Info: 26000 | 780 25219 | 67 933 | 37037| 0.37 6.77|
Info: 27000 | 887 26112 | 107 893 | 36638| 0.45 7.21|
Info: 28000 | 944 27055 | 57 943 | 36095| 0.36 7.57|
Info: 29000 | 1046 27953 | 102 898 | 35768| 0.43 8.00|
Info: 30000 | 1117 28882 | 71 929 | 35084| 0.39 8.39|
Info: 31000 | 1195 29804 | 78 922 | 35400| 0.39 8.78|
Info: 32000 | 1292 30707 | 97 903 | 34723| 0.49 9.27|
Info: 33000 | 1434 31565 | 142 858 | 34550| 0.59 9.86|
Info: 34000 | 1538 32461 | 104 896 | 34395| 0.53 10.39|
Info: 35000 | 1596 33403 | 58 942 | 34147| 0.38 10.77|
Info: 36000 | 1664 34335 | 68 932 | 33356| 0.41 11.19|
Info: 37000 | 1825 35174 | 161 839 | 33230| 0.63 11.82|
Info: 38000 | 1917 36082 | 92 908 | 32886| 0.59 12.41|
Info: 39000 | 2028 36971 | 111 889 | 32453| 0.55 12.97|
Info: 40000 | 2081 37918 | 53 947 | 31885| 0.42 13.39|
Info: 41000 | 2173 38826 | 92 908 | 31655| 0.54 13.93|
Info: 42000 | 2296 39703 | 123 877 | 31265| 0.64 14.57|
Info: 43000 | 2361 40638 | 65 935 | 30796| 0.58 15.15|
Info: 44000 | 2472 41527 | 111 889 | 30458| 0.59 15.74|
Info: 45000 | 2531 42468 | 59 941 | 29810| 0.56 16.30|
Info: 46000 | 2624 43375 | 93 907 | 29245| 0.61 16.91|
Info: 47000 | 2708 44291 | 84 916 | 28556| 0.56 17.47|
Info: 48000 | 2823 45176 | 115 885 | 28187| 0.68 18.16|
Info: 49000 | 2972 46027 | 149 851 | 27813| 0.89 19.05|
Info: 50000 | 3046 46953 | 74 926 | 27322| 0.54 19.58|
Info: 51000 | 3199 47800 | 153 847 | 27212| 1.16 20.74|
Info: 52000 | 3309 48690 | 110 890 | 26609| 0.65 21.39|
Info: 53000 | 3461 49538 | 152 848 | 26602| 0.90 22.29|
Info: 54000 | 3555 50444 | 94 906 | 26002| 0.58 22.87|
Info: 55000 | 3667 51332 | 112 888 | 25414| 0.70 23.57|
Info: 56000 | 3811 52188 | 144 856 | 24973| 0.71 24.28|
Info: 57000 | 3935 53064 | 124 876 | 24620| 0.88 25.16|
Info: 58000 | 3988 54011 | 53 947 | 23748| 0.47 25.63|
Info: 59000 | 4124 54875 | 136 864 | 23402| 0.72 26.34|
Info: 60000 | 4306 55693 | 182 818 | 23110| 1.33 27.67|
Info: 61000 | 4453 56546 | 147 853 | 22907| 1.04 28.71|
Info: 62000 | 4580 57419 | 127 873 | 22619| 0.77 29.48|
Info: 63000 | 4698 58301 | 118 882 | 22092| 0.85 30.33|
Info: 64000 | 4765 59234 | 67 933 | 21323| 0.55 30.88|
Info: 65000 | 4846 60153 | 81 919 | 20842| 0.62 31.50|
Info: 66000 | 4961 61038 | 115 885 | 20120| 0.68 32.18|
Info: 67000 | 5046 61953 | 85 915 | 19426| 0.62 32.80|
Info: 68000 | 5127 62872 | 81 919 | 18600| 0.57 33.37|
Info: 69000 | 5237 63762 | 110 890 | 17861| 0.66 34.02|
Info: 70000 | 5355 64644 | 118 882 | 17354| 0.64 34.66|
Info: 71000 | 5449 65550 | 94 906 | 16588| 0.61 35.27|
Info: 72000 | 5500 66499 | 51 949 | 16132| 0.45 35.72|
Info: 73000 | 5571 67428 | 71 929 | 15919| 0.87 36.59|
Info: 74000 | 5639 68360 | 68 932 | 15930| 0.70 37.29|
Info: 75000 | 5828 69171 | 189 811 | 15677| 1.13 38.41|
Info: 76000 | 6092 69907 | 264 736 | 15476| 1.72 40.13|
Info: 77000 | 6292 70707 | 200 800 | 15181| 2.16 42.29|
Info: 78000 | 6495 71504 | 203 797 | 15104| 2.13 44.42|
Info: 79000 | 6724 72275 | 229 771 | 14829| 1.56 45.98|
Info: 80000 | 6933 73066 | 209 791 | 14747| 2.31 48.29|
Info: 81000 | 7185 73814 | 252 748 | 14807| 1.80 50.09|
Info: 82000 | 7303 74696 | 118 882 | 14827| 2.59 52.67|
Info: 83000 | 7533 75466 | 230 770 | 14590| 1.79 54.46|
Info: 84000 | 7678 76321 | 145 855 | 14564| 1.74 56.20|
Info: 85000 | 7902 77097 | 224 776 | 14341| 1.71 57.92|
Info: 86000 | 8147 77852 | 245 755 | 14256| 1.72 59.64|
Info: 87000 | 8377 78622 | 230 770 | 14036| 2.08 61.71|
Info: 88000 | 8574 79425 | 197 803 | 13971| 1.52 63.23|
Info: 89000 | 8788 80211 | 214 786 | 13948| 1.80 65.03|
Info: 90000 | 9033 80966 | 245 755 | 13857| 2.08 67.12|
Info: 91000 | 9247 81752 | 214 786 | 13789| 2.12 69.24|
Info: 92000 | 9472 82527 | 225 775 | 13492| 2.14 71.38|
Info: 93000 | 9693 83306 | 221 779 | 13249| 1.96 73.34|
Info: 94000 | 9957 84042 | 264 736 | 13199| 2.22 75.55|
Info: 95000 | 10280 84719 | 323 677 | 13026| 2.32 77.87|
Info: 96000 | 10483 85516 | 203 797 | 12788| 2.14 80.02|
Info: 97000 | 10682 86317 | 199 801 | 12668| 1.92 81.94|
Info: 98000 | 10948 87051 | 266 734 | 12436| 2.62 84.55|
Info: 99000 | 11171 87828 | 223 777 | 12241| 2.42 86.97|
Info: 100000 | 11394 88605 | 223 777 | 12104| 1.56 88.53|
Info: 101000 | 11643 89356 | 249 751 | 11922| 2.21 90.74|
Info: 102000 | 11857 90142 | 214 786 | 11904| 1.88 92.62|
Info: 103000 | 12078 90921 | 221 779 | 11715| 1.86 94.48|
Info: 104000 | 12335 91664 | 257 743 | 11603| 2.04 96.52|
Info: 105000 | 12536 92463 | 201 799 | 11285| 1.54 98.06|
Info: 106000 | 12794 93205 | 258 742 | 11213| 1.88 99.94|
Info: 107000 | 13037 93962 | 243 757 | 10896| 1.98 101.93|
Info: 108000 | 13366 94633 | 329 671 | 10679| 2.47 104.40|
Info: 109000 | 13558 95441 | 192 808 | 10521| 1.26 105.66|
Info: 110000 | 13835 96164 | 277 723 | 10442| 1.72 107.38|
Info: 111000 | 14061 96938 | 226 774 | 10540| 2.75 110.14|
Info: 112000 | 14372 97627 | 311 689 | 10375| 4.05 114.19|
Info: 113000 | 14573 98426 | 201 799 | 10340| 2.31 116.50|
Info: 114000 | 14772 99227 | 199 801 | 10330| 2.11 118.62|
Info: 115000 | 14988 100011 | 216 784 | 10259| 1.99 120.60|
Info: 116000 | 15234 100765 | 246 754 | 9936| 1.46 122.07|
Info: 117000 | 15490 101509 | 256 744 | 9421| 1.05 123.12|
Info: 118000 | 15511 102488 | 21 979 | 8471| 0.31 123.43|
Info: 119000 | 15511 103488 | 0 1000 | 7471| 0.22 123.64|
Info: 120000 | 15511 104488 | 0 1000 | 6471| 0.22 123.86|
Info: 121000 | 15511 105488 | 0 1000 | 5471| 0.22 124.08|
Info: 122000 | 15511 106488 | 0 1000 | 4471| 0.22 124.30|
Info: 123000 | 15511 107488 | 0 1000 | 3471| 0.22 124.52|
Info: 124000 | 15511 108488 | 0 1000 | 2471| 0.22 124.74|
Info: 125000 | 15511 109488 | 0 1000 | 1471| 0.22 124.96|
Info: 126000 | 15511 110488 | 0 1000 | 471| 0.23 125.20|
Info: 126470 | 15511 110959 | 0 471 | 0| 0.22 125.42|
Info: Routing complete.
Info: Router1 time 125.42s
Info: Checksum: 0x15b2f95d
Info: Critical path report for clock '$glbnet$sram_clk' (posedge -> posedge):
Info: curr total
Info: 5.8 5.8 Source d.fifo.unbuffered.storage.0.0.0.DOB1
Info: 3.1 8.9 Net w_data__data[1] budget 0.000000 ns (4,25) -> (6,42)
Info: Sink w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_D_CCU2C_COUT_S0_CCU2C_S0_2$CCU2_SLICE.B1
Info: 0.4 9.3 Source w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_D_CCU2C_COUT_S0_CCU2C_S0_2$CCU2_SLICE.FCO
Info: 0.0 9.3 Net w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_D_CCU2C_COUT_S0_CCU2C_S0_COUT[2] budget 0.000000 ns (6,42) -> (6,42)
Info: Sink w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_D_CCU2C_COUT_S0_CCU2C_S0_1$CCU2_SLICE.FCI
Info: 0.1 9.4 Source w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_D_CCU2C_COUT_S0_CCU2C_S0_1$CCU2_SLICE.FCO
Info: 0.0 9.4 Net w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_D_CCU2C_COUT_S0_CCU2C_S0_COUT[4] budget 0.000000 ns (6,42) -> (6,42)
Info: Sink w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_D_CCU2C_COUT_S0_CCU2C_S0$CCU2_SLICE.FCI
Info: 0.1 9.5 Source w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_D_CCU2C_COUT_S0_CCU2C_S0$CCU2_SLICE.FCO
Info: 0.0 9.5 Net w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_D_CCU2C_COUT_S0_CCU2C_S0_COUT[6] budget 0.000000 ns (6,42) -> (7,42)
Info: Sink w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_D_CCU2C_COUT$CCU2_SLICE.FCI
Info: 0.1 9.5 Source w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_D_CCU2C_COUT$CCU2_SLICE.FCO
Info: 0.0 9.5 Net $nextpnr_CCU2C_99$CIN budget 0.000000 ns (7,42) -> (7,42)
Info: Sink $nextpnr_CCU2C_99$CCU2_SLICE.FCI
Info: 0.4 10.0 Source $nextpnr_CCU2C_99$CCU2_SLICE.F0
Info: 0.2 10.2 Net w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_D budget 11.655000 ns (7,42) -> (7,42)
Info: Sink w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_SLICE.D1
Info: 0.2 10.4 Source w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0_LUT4_Z_SLICE.F1
Info: 1.5 11.9 Net w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0_A0 budget 11.655000 ns (7,42) -> (4,36)
Info: Sink w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0$CCU2_SLICE.A0
Info: 0.4 12.4 Source w.tcount$next_LUT4_Z_D_LUT4_Z_C_CCU2C_S0$CCU2_SLICE.FCO
Info: 0.0 12.4 Net w.tcount$next_LUT4_Z_8_D_LUT4_Z_C_CCU2C_S0_COUT[0] budget 0.000000 ns (4,36) -> (4,36)
Info: Sink w.tcount$next_LUT4_Z_2_D_LUT4_Z_C_CCU2C_S0$CCU2_SLICE.FCI
Info: 0.1 12.4 Source w.tcount$next_LUT4_Z_2_D_LUT4_Z_C_CCU2C_S0$CCU2_SLICE.FCO
Info: 0.0 12.4 Net w.tcount$next_LUT4_Z_8_D_LUT4_Z_C_CCU2C_S0_COUT[2] budget 0.000000 ns (4,36) -> (4,36)
Info: Sink w.tcount$next_LUT4_Z_4_D_LUT4_Z_C_CCU2C_S0$CCU2_SLICE.FCI
Info: 0.1 12.5 Source w.tcount$next_LUT4_Z_4_D_LUT4_Z_C_CCU2C_S0$CCU2_SLICE.FCO
Info: 0.0 12.5 Net w.tcount$next_LUT4_Z_8_D_LUT4_Z_C_CCU2C_S0_COUT[4] budget 0.000000 ns (4,36) -> (5,36)
Info: Sink w.tcount$next_LUT4_Z_6_D_LUT4_Z_C_CCU2C_S0$CCU2_SLICE.FCI
Info: 0.4 12.9 Source w.tcount$next_LUT4_Z_6_D_LUT4_Z_C_CCU2C_S0$CCU2_SLICE.F0
Info: 0.8 13.7 Net w.tcount$next_LUT4_Z_6_D_LUT4_Z_C budget 15.554000 ns (5,36) -> (4,39)
Info: Sink w.tcount$next_LUT4_Z_6_D_LUT4_Z_SLICE.D1
Info: 0.2 14.0 Source w.tcount$next_LUT4_Z_6_D_LUT4_Z_SLICE.F1
Info: 0.9 14.9 Net w.tcount$next_LUT4_Z_6_D budget 15.554000 ns (4,39) -> (3,38)
Info: Sink w.tcount$next_LUT4_Z_6_SLICE.D0
Info: 0.2 15.1 Source w.tcount$next_LUT4_Z_6_SLICE.F0
Info: 0.1 15.3 Net w.tcount$next[6] budget 12.443000 ns (3,38) -> (3,38)
Info: Sink w.tcount$next_LUT4_Z_6_SLICE.DI0
Info: 0.0 15.3 Setup w.tcount$next_LUT4_Z_6_SLICE.DI0
Info: 8.7 ns logic, 6.6 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sram_clk' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source sram.fsm_state$next_LUT4_Z_2_SLICE.Q1
Info: 1.0 1.5 Net sram.fsm_state[3] budget 20.525000 ns (65,17) -> (65,17)
Info: Sink pin_sram_0__d.sram_0__d__o_LUT4_Z_SLICE.A1
Info: 0.2 1.7 Source pin_sram_0__d.sram_0__d__o_LUT4_Z_SLICE.F1
Info: 1.7 3.4 Net pin_sram_0__d.sram_0__d__o_LUT4_Z_A budget 27.445000 ns (65,17) -> (52,12)
Info: Sink pin_sram_0__d.sram_0__d__o_LUT4_Z_7_SLICE.C0
Info: 0.2 3.7 Source pin_sram_0__d.sram_0__d__o_LUT4_Z_7_SLICE.F0
Info: 3.7 7.4 Net sram_sram_0__d__o[8] budget 27.445000 ns (52,12) -> (72,41)
Info: Sink pin_sram_0__d.sram_0__d_8.I
Info: 1.0 ns logic, 6.4 ns routing
Info: Max frequency for clock '$glbnet$sram_clk': 65.48 MHz (PASS at 12.00 MHz)
Info: Max delay posedge $glbnet$sram_clk -> <async>: 7.35 ns
Info: Slack histogram:
Info: legend: * represents 8 endpoint(s)
Info: + represents [1,8) endpoint(s)
Info: [ 68060, 68791) |*+
Info: [ 68791, 69522) |*+
Info: [ 69522, 70253) |***+
Info: [ 70253, 70984) |****+
Info: [ 70984, 71715) |*********+
Info: [ 71715, 72446) |********************************+
Info: [ 72446, 73177) |**************************************************+
Info: [ 73177, 73908) |************************************************************
Info: [ 73908, 74639) |****************************************+
Info: [ 74639, 75370) |*******************+
Info: [ 75370, 76101) |**************+
Info: [ 76101, 76832) |***********+
Info: [ 76832, 77563) |******+
Info: [ 77563, 78294) |**************+
Info: [ 78294, 79025) |*************************+
Info: [ 79025, 79756) |*****************+
Info: [ 79756, 80487) |****************+
Info: [ 80487, 81218) |*****************+
Info: [ 81218, 81949) |*******+
Info: [ 81949, 82680) |*+
+ ecppack --verbose --idcode 0x21111043 --input top.config --bit top.bit --svf top.svf
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment