Skip to content

Instantly share code, notes, and snippets.

@damageboy

damageboy/IntrinsicsUnrolled.jitdump.txt

Created August 21, 2018 15:10
Show Gist options
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save damageboy/c73959ad3dfe31e5d65e6bf273f53211 to your computer and use it in GitHub Desktop.
Save damageboy/c73959ad3dfe31e5d65e6bf273f53211 to your computer and use it in GitHub Desktop.
Download ZIP
Raw
IntrinsicsUnrolled.jitdump.txt
****** START compiling Program:IntrinsicsUnrolled(int):int (MethodHash=6b9d3a1b)
Generating code for Unix x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 7e 03 00 00 04 ldsfld 0x4000003
IL_0005 20 00 04 00 00 ldc.i4 0x400
IL_000a 02 ldarg.0
IL_000b 28 14 00 00 0a call 0xA000014
IL_0010 2a ret
Arg #0 passed in register(s) rdi
lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk (na)
*************** In compInitDebuggingInfo() for Program:IntrinsicsUnrolled(int):int
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 1
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 011h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program:IntrinsicsUnrolled(int):int
Jump targets:
none
New Basic Block BB01 [0000] created.
BB01 [000..011)
IL Code Size,Instr 17, 5, Basic Block count 1, Local Variable Num,Ref count 2, 1 for method Program:IntrinsicsUnrolled(int):int
OPTIONS: opts.MinOpts() == false
Basic block list for 'Program:IntrinsicsUnrolled(int):int'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Program:IntrinsicsUnrolled(int):int
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program:IntrinsicsUnrolled(int):int'
[ 0] 0 (0x000) ldsfld 04000003
[ 1] 5 (0x005) ldc.i4 1024
[ 2] 10 (0x00a) ldarg.0
[ 3] 11 (0x00b) call 0A000014 (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT)
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
info.compCompHnd->canTailCall returned false for call [000004]
[000008] ------------ * STMT void (IL 0x000... ???)
[000004] I-C-G------- \--* CALL int GetNthBitOffset.IntrinsicsUnrolled (exactContextHnd=0x00007F08AB887599)
[000001] ----G------- arg0 +--* FIELD long _bits
[000002] ------------ arg1 +--* CNS_INT int 0x400
[000003] ------------ arg2 \--* LCL_VAR int V00 arg0
[ 1] 16 (0x010) ret
[000011] ------------ * STMT void (IL ???... ???)
[000010] --C--------- \--* RETURN int
[000009] --C--------- \--* RET_EXPR int (inl return from call [000004])
New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** In fgInline()
Expanding INLINE_CANDIDATE in statement [000008] in BB01:
[000008] ------------ * STMT void (IL 0x000...0x010)
[000004] I-C-G------- \--* CALL int GetNthBitOffset.IntrinsicsUnrolled (exactContextHnd=0x00007F08AB887599)
[000001] ----G------- arg0 +--* FIELD long _bits
[000002] ------------ arg1 +--* CNS_INT int 0x400
[000003] ------------ arg2 \--* LCL_VAR int V00 arg0
Argument #0: has global refs
[000001] ----G------- * FIELD long _bits
Argument #1: is a constant
[000002] ------------ * CNS_INT int 0x400
Argument #2: is a local var
[000003] ------------ * LCL_VAR int V00 arg0
INLINER: inlineInfo.tokenLookupContextHandle for GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int set to 0x00007F08AB887599:
Invoking compiler for the inlinee method GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int :
IL to import:
IL_0000 02 ldarg.0
IL_0001 0a stloc.0
IL_0002 2b 37 br.s 55 (IL_003b)
IL_0004 04 ldarg.2
IL_0005 06 ldloc.0
IL_0006 4c ldind.i8
IL_0007 28 0d 00 00 0a call 0xA00000D
IL_000c 06 ldloc.0
IL_000d 1e ldc.i4.8
IL_000e 58 add
IL_000f 4c ldind.i8
IL_0010 28 0d 00 00 0a call 0xA00000D
IL_0015 58 add
IL_0016 06 ldloc.0
IL_0017 18 ldc.i4.2
IL_0018 d3 conv.i
IL_0019 1e ldc.i4.8
IL_001a 5a mul
IL_001b 58 add
IL_001c 4c ldind.i8
IL_001d 28 0d 00 00 0a call 0xA00000D
IL_0022 58 add
IL_0023 06 ldloc.0
IL_0024 19 ldc.i4.3
IL_0025 d3 conv.i
IL_0026 1e ldc.i4.8
IL_0027 5a mul
IL_0028 58 add
IL_0029 4c ldind.i8
IL_002a 28 0d 00 00 0a call 0xA00000D
IL_002f 58 add
IL_0030 69 conv.i4
IL_0031 59 sub
IL_0032 10 02 starg.s 0x2
IL_0034 06 ldloc.0
IL_0035 1a ldc.i4.4
IL_0036 d3 conv.i
IL_0037 1e ldc.i4.8
IL_0038 5a mul
IL_0039 58 add
IL_003a 0a stloc.0
IL_003b 04 ldarg.2
IL_003c 20 00 01 00 00 ldc.i4 0x100
IL_0041 2f c1 bge.s -63 (IL_0004)
IL_0043 04 ldarg.2
IL_0044 0b stloc.1
IL_0045 2b 12 br.s 18 (IL_0059)
IL_0047 04 ldarg.2
IL_0048 0b stloc.1
IL_0049 04 ldarg.2
IL_004a 06 ldloc.0
IL_004b 4c ldind.i8
IL_004c 28 0d 00 00 0a call 0xA00000D
IL_0051 69 conv.i4
IL_0052 59 sub
IL_0053 10 02 starg.s 0x2
IL_0055 06 ldloc.0
IL_0056 1e ldc.i4.8
IL_0057 58 add
IL_0058 0a stloc.0
IL_0059 04 ldarg.2
IL_005a 16 ldc.i4.0
IL_005b 30 ea bgt.s -22 (IL_0047)
IL_005d 06 ldloc.0
IL_005e 1e ldc.i4.8
IL_005f 59 sub
IL_0060 0a stloc.0
IL_0061 17 ldc.i4.1
IL_0062 6a conv.i8
IL_0063 07 ldloc.1
IL_0064 17 ldc.i4.1
IL_0065 59 sub
IL_0066 1f 3f ldc.i4.s 0x3F
IL_0068 5f and
IL_0069 62 shl
IL_006a 06 ldloc.0
IL_006b 4c ldind.i8
IL_006c 28 0f 00 00 0a call 0xA00000F
IL_0071 28 10 00 00 0a call 0xA000010
IL_0076 69 conv.i4
IL_0077 0c stloc.2
IL_0078 06 ldloc.0
IL_0079 02 ldarg.0
IL_007a 59 sub
IL_007b 1e ldc.i4.8
IL_007c 5b div
IL_007d 6a conv.i8
IL_007e 1f 40 ldc.i4.s 0x40
IL_0080 6a conv.i8
IL_0081 5a mul
IL_0082 69 conv.i4
IL_0083 08 ldloc.2
IL_0084 58 add
IL_0085 2a ret
INLINER impTokenLookupContextHandle for GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int is 0x00007F08AB887599.
*************** In fgFindBasicBlocks() for GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int
Jump targets:
IL_0004
IL_003b
IL_0047
IL_0059
New Basic Block BB02 [0001] created.
BB02 [000..004)
New Basic Block BB03 [0002] created.
BB03 [004..03B)
New Basic Block BB04 [0003] created.
BB04 [03B..043)
New Basic Block BB05 [0004] created.
BB05 [043..047)
New Basic Block BB06 [0005] created.
BB06 [047..059)
New Basic Block BB07 [0006] created.
BB07 [059..05D)
New Basic Block BB08 [0007] created.
BB08 [05D..086)
Basic block list for 'GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB02 [0001] 1 1 [000..004)-> BB04 (always)
BB03 [0002] 1 1 [004..03B) bwd
BB04 [0003] 2 1 [03B..043)-> BB03 ( cond ) bwd
BB05 [0004] 1 1 [043..047)-> BB07 (always)
BB06 [0005] 1 1 [047..059) bwd
BB07 [0006] 2 1 [059..05D)-> BB06 ( cond ) bwd
BB08 [0007] 1 1 [05D..086) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int
impImportBlockPending for BB02
Importing BB02 (PC=000) of 'GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int'
[ 0] 0 (0x000) ldarg.0
lvaGrabTemp returning 2 (V02 tmp1) called for Inlining Arg.
[ 1] 1 (0x001) stloc.0
lvaGrabTemp returning 3 (V03 tmp2) (a long lifetime temp) called for Inline stloc first use temp.
[000016] ------------ * STMT void
[000013] ------------ | /--* LCL_VAR long V02 tmp1
[000015] -A---------- \--* ASG long
[000014] D------N---- \--* LCL_VAR long V03 tmp2
[ 0] 2 (0x002) br.s
impImportBlockPending for BB04
Importing BB04 (PC=059) of 'GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int'
[ 0] 59 (0x03b) ldarg.2
lvaGrabTemp returning 4 (V04 tmp3) called for Inlining Arg.
[ 1] 60 (0x03c) ldc.i4 256
[ 2] 65 (0x041) bge.s
[000022] ------------ * STMT void
[000021] ------------ \--* JTRUE void
[000019] ------------ | /--* CNS_INT int 256
[000020] ------------ \--* GE int
[000018] ------------ \--* LCL_VAR int V04 tmp3
impImportBlockPending for BB05
impImportBlockPending for BB03
Importing BB03 (PC=004) of 'GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int'
[ 0] 4 (0x004) ldarg.2
[ 1] 5 (0x005) ldloc.0
[ 2] 6 (0x006) ldind.i8
[ 2] 7 (0x007) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 2] 12 (0x00c) ldloc.0
[ 3] 13 (0x00d) ldc.i4.8 8
[ 4] 14 (0x00e) add
[ 3] 15 (0x00f) ldind.i8
[ 3] 16 (0x010) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 3] 21 (0x015) add
[ 2] 22 (0x016) ldloc.0
[ 3] 23 (0x017) ldc.i4.2 2
[ 4] 24 (0x018) conv.i
[ 4] 25 (0x019) ldc.i4.8 8
[ 5] 26 (0x01a) mul
[ 4] 27 (0x01b) add
[ 3] 28 (0x01c) ldind.i8
[ 3] 29 (0x01d) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 3] 34 (0x022) add
[ 2] 35 (0x023) ldloc.0
[ 3] 36 (0x024) ldc.i4.3 3
[ 4] 37 (0x025) conv.i
[ 4] 38 (0x026) ldc.i4.8 8
[ 5] 39 (0x027) mul
[ 4] 40 (0x028) add
[ 3] 41 (0x029) ldind.i8
[ 3] 42 (0x02a) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 3] 47 (0x02f) add
[ 2] 48 (0x030) conv.i4
[ 2] 49 (0x031) sub
[ 1] 50 (0x032) starg.s 2
[000060] ------------ * STMT void
[000055] ---XG------- | /--* CAST int <- long
[000053] ---XG------- | | | /--* HWIntrinsic long PopCount
[000052] *--XG------- | | | | \--* IND long
[000049] ------------ | | | | | /--* CAST long <- int
[000048] ------------ | | | | | | \--* CNS_INT int 8
[000050] ------------ | | | | | /--* MUL long
[000047] ------------ | | | | | | \--* CAST long <- int
[000046] ------------ | | | | | | \--* CNS_INT int 3
[000051] ------------ | | | | \--* ADD long
[000045] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000054] ---XG------- | | \--* ADD long
[000043] ---XG------- | | | /--* HWIntrinsic long PopCount
[000042] *--XG------- | | | | \--* IND long
[000039] ------------ | | | | | /--* CAST long <- int
[000038] ------------ | | | | | | \--* CNS_INT int 8
[000040] ------------ | | | | | /--* MUL long
[000037] ------------ | | | | | | \--* CAST long <- int
[000036] ------------ | | | | | | \--* CNS_INT int 2
[000041] ------------ | | | | \--* ADD long
[000035] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000044] ---XG------- | | \--* ADD long
[000033] ---XG------- | | | /--* HWIntrinsic long PopCount
[000032] *--XG------- | | | | \--* IND long
[000030] ------------ | | | | | /--* CAST long <- int
[000029] ------------ | | | | | | \--* CNS_INT int 8
[000031] ------------ | | | | \--* ADD long
[000028] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000034] ---XG------- | | \--* ADD long
[000027] ---XG------- | | \--* HWIntrinsic long PopCount
[000026] *--XG------- | | \--* IND long
[000025] ------------ | | \--* LCL_VAR long V03 tmp2
[000056] ---XG------- | /--* SUB int
[000024] ------------ | | \--* LCL_VAR int V04 tmp3
[000059] -A-XG------- \--* ASG int
[000058] D------N---- \--* LCL_VAR int V04 tmp3
[ 0] 52 (0x034) ldloc.0
[ 1] 53 (0x035) ldc.i4.4 4
[ 2] 54 (0x036) conv.i
[ 2] 55 (0x037) ldc.i4.8 8
[ 3] 56 (0x038) mul
[ 2] 57 (0x039) add
[ 1] 58 (0x03a) stloc.0
[000070] ------------ * STMT void
[000065] ------------ | /--* CAST long <- int
[000064] ------------ | | \--* CNS_INT int 8
[000066] ------------ | /--* MUL long
[000063] ------------ | | \--* CAST long <- int
[000062] ------------ | | \--* CNS_INT int 4
[000067] ------------ | /--* ADD long
[000061] ------------ | | \--* LCL_VAR long V03 tmp2
[000069] -A---------- \--* ASG long
[000068] D------N---- \--* LCL_VAR long V03 tmp2
impImportBlockPending for BB04
Importing BB05 (PC=067) of 'GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int'
[ 0] 67 (0x043) ldarg.2
[ 1] 68 (0x044) stloc.1
lvaGrabTemp returning 5 (V05 tmp4) (a long lifetime temp) called for Inline stloc first use temp.
[000075] ------------ * STMT void
[000072] ------------ | /--* LCL_VAR int V04 tmp3
[000074] -A---------- \--* ASG int
[000073] D------N---- \--* LCL_VAR int V05 tmp4
[ 0] 69 (0x045) br.s
impImportBlockPending for BB07
Importing BB07 (PC=089) of 'GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int'
[ 0] 89 (0x059) ldarg.2
[ 1] 90 (0x05a) ldc.i4.0 0
[ 2] 91 (0x05b) bgt.s
[000081] ------------ * STMT void
[000080] ------------ \--* JTRUE void
[000078] ------------ | /--* CNS_INT int 0
[000079] ------------ \--* GT int
[000077] ------------ \--* LCL_VAR int V04 tmp3
impImportBlockPending for BB08
impImportBlockPending for BB06
Importing BB06 (PC=071) of 'GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int'
[ 0] 71 (0x047) ldarg.2
[ 1] 72 (0x048) stloc.1
[000086] ------------ * STMT void
[000083] ------------ | /--* LCL_VAR int V04 tmp3
[000085] -A---------- \--* ASG int
[000084] D------N---- \--* LCL_VAR int V05 tmp4
[ 0] 73 (0x049) ldarg.2
[ 1] 74 (0x04a) ldloc.0
[ 2] 75 (0x04b) ldind.i8
[ 2] 76 (0x04c) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 2] 81 (0x051) conv.i4
[ 2] 82 (0x052) sub
[ 1] 83 (0x053) starg.s 2
[000096] ------------ * STMT void
[000091] ---XG------- | /--* CAST int <- long
[000090] ---XG------- | | \--* HWIntrinsic long PopCount
[000089] *--XG------- | | \--* IND long
[000088] ------------ | | \--* LCL_VAR long V03 tmp2
[000092] ---XG------- | /--* SUB int
[000087] ------------ | | \--* LCL_VAR int V04 tmp3
[000095] -A-XG------- \--* ASG int
[000094] D------N---- \--* LCL_VAR int V04 tmp3
[ 0] 85 (0x055) ldloc.0
[ 1] 86 (0x056) ldc.i4.8 8
[ 2] 87 (0x057) add
[ 1] 88 (0x058) stloc.0
[000103] ------------ * STMT void
[000099] ------------ | /--* CAST long <- int
[000098] ------------ | | \--* CNS_INT int 8
[000100] ------------ | /--* ADD long
[000097] ------------ | | \--* LCL_VAR long V03 tmp2
[000102] -A---------- \--* ASG long
[000101] D------N---- \--* LCL_VAR long V03 tmp2
impImportBlockPending for BB07
Importing BB08 (PC=093) of 'GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int'
[ 0] 93 (0x05d) ldloc.0
[ 1] 94 (0x05e) ldc.i4.8 8
[ 2] 95 (0x05f) sub
[ 1] 96 (0x060) stloc.0
[000111] ------------ * STMT void
[000107] ------------ | /--* CAST long <- int
[000106] ------------ | | \--* CNS_INT int 8
[000108] ------------ | /--* SUB long
[000105] ------------ | | \--* LCL_VAR long V03 tmp2
[000110] -A---------- \--* ASG long
[000109] D------N---- \--* LCL_VAR long V03 tmp2
[ 0] 97 (0x061) ldc.i4.1 1
[ 1] 98 (0x062) conv.i8
[ 1] 99 (0x063) ldloc.1
[ 2] 100 (0x064) ldc.i4.1 1
[ 3] 101 (0x065) sub
[ 2] 102 (0x066) ldc.i4.s 63
[ 3] 104 (0x068) and
[ 2] 105 (0x069) shl
[ 1] 106 (0x06a) ldloc.0
[ 2] 107 (0x06b) ldind.i8
[ 2] 108 (0x06c) call 0A00000F
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 1] 113 (0x071) call 0A000010
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 1] 118 (0x076) conv.i4
[ 1] 119 (0x077) stloc.2
lvaGrabTemp returning 6 (V06 tmp5) (a long lifetime temp) called for Inline stloc first use temp.
[000127] ------------ * STMT void
[000124] ---XG------- | /--* CAST int <- long
[000123] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
[000121] *--XG------- | | | /--* IND long
[000120] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000122] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
[000117] ------------ | | | /--* CNS_INT int 63
[000118] ------------ | | | /--* AND int
[000115] ------------ | | | | | /--* CNS_INT int 1
[000116] ------------ | | | | \--* SUB int
[000114] ------------ | | | | \--* LCL_VAR int V05 tmp4
[000119] ------------ | | \--* LSH long
[000113] ------------ | | \--* CAST long <- int
[000112] ------------ | | \--* CNS_INT int 1
[000126] -A-XG------- \--* ASG int
[000125] D------N---- \--* LCL_VAR int V06 tmp5
[ 0] 120 (0x078) ldloc.0
[ 1] 121 (0x079) ldarg.0
[ 2] 122 (0x07a) sub
[ 1] 123 (0x07b) ldc.i4.8 8
[ 2] 124 (0x07c) div
[ 1] 125 (0x07d) conv.i8
[ 1] 126 (0x07e) ldc.i4.s 64
[ 2] 128 (0x080) conv.i8
[ 2] 129 (0x081) mul
[ 1] 130 (0x082) conv.i4
[ 1] 131 (0x083) ldloc.2
[ 2] 132 (0x084) add
[ 1] 133 (0x085) ret
Inlinee Return expression (before normalization) =>
[000138] ------------ /--* LCL_VAR int V06 tmp5
[000139] ---X-------- * ADD int
[000137] ---X-------- \--* CAST int <- long
[000135] ------------ | /--* CAST long <- int
[000134] ------------ | | \--* CNS_INT int 64
[000136] ---X-------- \--* MUL long
[000132] ------------ | /--* CAST long <- int
[000131] ------------ | | \--* CNS_INT int 8
[000133] ---X-------- \--* DIV long
[000129] ------------ | /--* LCL_VAR long V02 tmp1
[000130] ------------ \--* SUB long
[000128] ------------ \--* LCL_VAR long V03 tmp2
Inlinee Return expression (after normalization) =>
[000138] ------------ /--* LCL_VAR int V06 tmp5
[000139] ---X-------- * ADD int
[000137] ---X-------- \--* CAST int <- long
[000135] ------------ | /--* CAST long <- int
[000134] ------------ | | \--* CNS_INT int 64
[000136] ---X-------- \--* MUL long
[000132] ------------ | /--* CAST long <- int
[000131] ------------ | | \--* CNS_INT int 8
[000133] ---X-------- \--* DIV long
[000129] ------------ | /--* LCL_VAR long V02 tmp1
[000130] ------------ \--* SUB long
[000128] ------------ \--* LCL_VAR long V03 tmp2
----------- Statements (and blocks) added due to the inlining of call [000004] -----------
Arguments setup:
[000142] ------------ * STMT void (IL 0x000... ???)
[000001] ----G------- | /--* FIELD long _bits
[000141] -A--G------- \--* ASG long
[000140] D------N---- \--* LCL_VAR long V02 tmp1
[000145] ------------ * STMT void (IL 0x000... ???)
[000003] ------------ | /--* LCL_VAR int V00 arg0
[000144] -A---------- \--* ASG int
[000143] D------N---- \--* LCL_VAR int V04 tmp3
Zero init inlinee locals:
[000149] ------------ * STMT void (IL 0x000... ???)
[000146] ------------ | /--* CNS_INT long 0
[000148] -A---------- \--* ASG long
[000147] D------N---- \--* LCL_VAR long V03 tmp2
[000153] ------------ * STMT void (IL 0x000... ???)
[000150] ------------ | /--* CNS_INT int 0
[000152] -A---------- \--* ASG int
[000151] D------N---- \--* LCL_VAR int V05 tmp4
[000157] ------------ * STMT void (IL 0x000... ???)
[000154] ------------ | /--* CNS_INT int 0
[000156] -A---------- \--* ASG int
[000155] D------N---- \--* LCL_VAR int V06 tmp5
Inlinee method body:New Basic Block BB09 [0008] created.
Convert bbJumpKind of BB08 to BBJ_NONE
fgInlineAppendStatements: no gc ref inline locals.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB02 [0001] 1 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 0.50 [000..001) i bwd
BB04 [0003] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB05 [0004] 1 0.50 [000..001)-> BB07 (always) i
BB06 [0005] 1 0.50 [000..001) i bwd
BB07 [0006] 2 0.50 [000..001)-> BB06 ( cond ) i bwd
BB08 [0007] 1 1 [000..001) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB02 [000..001) -> BB04 (always), preds={} succs={BB04}
***** BB02, stmt 1
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] ------------ | /--* LCL_VAR long V02 tmp1
[000015] -A---------- \--* ASG long
[000014] D------N---- \--* LCL_VAR long V03 tmp2
------------ BB03 [000..001), preds={} succs={BB04}
***** BB03, stmt 2
[000060] ------------ * STMT void (IL 0x000... ???)
[000055] ---XG------- | /--* CAST int <- long
[000053] ---XG------- | | | /--* HWIntrinsic long PopCount
[000052] *--XG------- | | | | \--* IND long
[000049] ------------ | | | | | /--* CAST long <- int
[000048] ------------ | | | | | | \--* CNS_INT int 8
[000050] ------------ | | | | | /--* MUL long
[000047] ------------ | | | | | | \--* CAST long <- int
[000046] ------------ | | | | | | \--* CNS_INT int 3
[000051] ------------ | | | | \--* ADD long
[000045] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000054] ---XG------- | | \--* ADD long
[000043] ---XG------- | | | /--* HWIntrinsic long PopCount
[000042] *--XG------- | | | | \--* IND long
[000039] ------------ | | | | | /--* CAST long <- int
[000038] ------------ | | | | | | \--* CNS_INT int 8
[000040] ------------ | | | | | /--* MUL long
[000037] ------------ | | | | | | \--* CAST long <- int
[000036] ------------ | | | | | | \--* CNS_INT int 2
[000041] ------------ | | | | \--* ADD long
[000035] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000044] ---XG------- | | \--* ADD long
[000033] ---XG------- | | | /--* HWIntrinsic long PopCount
[000032] *--XG------- | | | | \--* IND long
[000030] ------------ | | | | | /--* CAST long <- int
[000029] ------------ | | | | | | \--* CNS_INT int 8
[000031] ------------ | | | | \--* ADD long
[000028] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000034] ---XG------- | | \--* ADD long
[000027] ---XG------- | | \--* HWIntrinsic long PopCount
[000026] *--XG------- | | \--* IND long
[000025] ------------ | | \--* LCL_VAR long V03 tmp2
[000056] ---XG------- | /--* SUB int
[000024] ------------ | | \--* LCL_VAR int V04 tmp3
[000059] -A-XG------- \--* ASG int
[000058] D------N---- \--* LCL_VAR int V04 tmp3
***** BB03, stmt 3
[000070] ------------ * STMT void (IL 0x000... ???)
[000065] ------------ | /--* CAST long <- int
[000064] ------------ | | \--* CNS_INT int 8
[000066] ------------ | /--* MUL long
[000063] ------------ | | \--* CAST long <- int
[000062] ------------ | | \--* CNS_INT int 4
[000067] ------------ | /--* ADD long
[000061] ------------ | | \--* LCL_VAR long V03 tmp2
[000069] -A---------- \--* ASG long
[000068] D------N---- \--* LCL_VAR long V03 tmp2
------------ BB04 [000..001) -> BB03 (cond), preds={} succs={BB05,BB03}
***** BB04, stmt 4
[000022] ------------ * STMT void (IL 0x000... ???)
[000021] ------------ \--* JTRUE void
[000019] ------------ | /--* CNS_INT int 256
[000020] ------------ \--* GE int
[000018] ------------ \--* LCL_VAR int V04 tmp3
------------ BB05 [000..001) -> BB07 (always), preds={} succs={BB07}
***** BB05, stmt 5
[000075] ------------ * STMT void (IL 0x000... ???)
[000072] ------------ | /--* LCL_VAR int V04 tmp3
[000074] -A---------- \--* ASG int
[000073] D------N---- \--* LCL_VAR int V05 tmp4
------------ BB06 [000..001), preds={} succs={BB07}
***** BB06, stmt 6
[000086] ------------ * STMT void (IL 0x000... ???)
[000083] ------------ | /--* LCL_VAR int V04 tmp3
[000085] -A---------- \--* ASG int
[000084] D------N---- \--* LCL_VAR int V05 tmp4
***** BB06, stmt 7
[000096] ------------ * STMT void (IL 0x000... ???)
[000091] ---XG------- | /--* CAST int <- long
[000090] ---XG------- | | \--* HWIntrinsic long PopCount
[000089] *--XG------- | | \--* IND long
[000088] ------------ | | \--* LCL_VAR long V03 tmp2
[000092] ---XG------- | /--* SUB int
[000087] ------------ | | \--* LCL_VAR int V04 tmp3
[000095] -A-XG------- \--* ASG int
[000094] D------N---- \--* LCL_VAR int V04 tmp3
***** BB06, stmt 8
[000103] ------------ * STMT void (IL 0x000... ???)
[000099] ------------ | /--* CAST long <- int
[000098] ------------ | | \--* CNS_INT int 8
[000100] ------------ | /--* ADD long
[000097] ------------ | | \--* LCL_VAR long V03 tmp2
[000102] -A---------- \--* ASG long
[000101] D------N---- \--* LCL_VAR long V03 tmp2
------------ BB07 [000..001) -> BB06 (cond), preds={} succs={BB08,BB06}
***** BB07, stmt 9
[000081] ------------ * STMT void (IL 0x000... ???)
[000080] ------------ \--* JTRUE void
[000078] ------------ | /--* CNS_INT int 0
[000079] ------------ \--* GT int
[000077] ------------ \--* LCL_VAR int V04 tmp3
------------ BB08 [000..001), preds={} succs={BB09}
***** BB08, stmt 10
[000111] ------------ * STMT void (IL 0x000... ???)
[000107] ------------ | /--* CAST long <- int
[000106] ------------ | | \--* CNS_INT int 8
[000108] ------------ | /--* SUB long
[000105] ------------ | | \--* LCL_VAR long V03 tmp2
[000110] -A---------- \--* ASG long
[000109] D------N---- \--* LCL_VAR long V03 tmp2
***** BB08, stmt 11
[000127] ------------ * STMT void (IL 0x000... ???)
[000124] ---XG------- | /--* CAST int <- long
[000123] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
[000121] *--XG------- | | | /--* IND long
[000120] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000122] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
[000117] ------------ | | | /--* CNS_INT int 63
[000118] ------------ | | | /--* AND int
[000115] ------------ | | | | | /--* CNS_INT int 1
[000116] ------------ | | | | \--* SUB int
[000114] ------------ | | | | \--* LCL_VAR int V05 tmp4
[000119] ------------ | | \--* LSH long
[000113] ------------ | | \--* CAST long <- int
[000112] ------------ | | \--* CNS_INT int 1
[000126] -A-XG------- \--* ASG int
[000125] D------N---- \--* LCL_VAR int V06 tmp5
-------------------------------------------------------------------------------------------------------------------
Return expression for call at [000004] is
[000138] ------------ /--* LCL_VAR int V06 tmp5
[000139] ---X-------- * ADD int
[000137] ---X-------- \--* CAST int <- long
[000135] ------------ | /--* CAST long <- int
[000134] ------------ | | \--* CNS_INT int 64
[000136] ---X-------- \--* MUL long
[000132] ------------ | /--* CAST long <- int
[000131] ------------ | | \--* CNS_INT int 8
[000133] ---X-------- \--* DIV long
[000129] ------------ | /--* LCL_VAR long V02 tmp1
[000130] ------------ \--* SUB long
[000128] ------------ \--* LCL_VAR long V03 tmp2
Successfully inlined GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int (134 IL bytes) (depth 1) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Program:IntrinsicsUnrolled(int):int' calling 'GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Replacing the return expression placeholder [000009] with [000139]
[000009] --C--------- * RET_EXPR int (inl return from call [000139])
Inserting the inline return expression
[000138] ------------ /--* LCL_VAR int V06 tmp5
[000139] ---X-------- * ADD int
[000137] ---X-------- \--* CAST int <- long
[000135] ------------ | /--* CAST long <- int
[000134] ------------ | | \--* CNS_INT int 64
[000136] ---X-------- \--* MUL long
[000132] ------------ | /--* CAST long <- int
[000131] ------------ | | \--* CNS_INT int 8
[000133] ---X-------- \--* DIV long
[000129] ------------ | /--* LCL_VAR long V02 tmp1
[000130] ------------ \--* SUB long
[000128] ------------ \--* LCL_VAR long V03 tmp2
*************** After fgInline()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i
BB02 [0001] 1 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 0.50 [000..001) i bwd
BB04 [0003] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB05 [0004] 1 0.50 [000..001)-> BB07 (always) i
BB06 [0005] 1 0.50 [000..001) i bwd
BB07 [0006] 2 0.50 [000..001)-> BB06 ( cond ) i bwd
BB08 [0007] 1 1 [000..001) i
BB09 [0008] 1 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
[000142] ------------ * STMT void (IL 0x000... ???)
[000001] ----G------- | /--* FIELD long _bits
[000141] -A--G------- \--* ASG long
[000140] D------N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000145] ------------ * STMT void (IL 0x000... ???)
[000003] ------------ | /--* LCL_VAR int V00 arg0
[000144] -A---------- \--* ASG int
[000143] D------N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000149] ------------ * STMT void (IL 0x000... ???)
[000146] ------------ | /--* CNS_INT long 0
[000148] -A---------- \--* ASG long
[000147] D------N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000153] ------------ * STMT void (IL 0x000... ???)
[000150] ------------ | /--* CNS_INT int 0
[000152] -A---------- \--* ASG int
[000151] D------N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000157] ------------ * STMT void (IL 0x000... ???)
[000154] ------------ | /--* CNS_INT int 0
[000156] -A---------- \--* ASG int
[000155] D------N---- \--* LCL_VAR int V06 tmp5
------------ BB02 [000..001) -> BB04 (always), preds={} succs={BB04}
***** BB02, stmt 6
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] ------------ | /--* LCL_VAR long V02 tmp1
[000015] -A---------- \--* ASG long
[000014] D------N---- \--* LCL_VAR long V03 tmp2
------------ BB03 [000..001), preds={} succs={BB04}
***** BB03, stmt 7
[000060] ------------ * STMT void (IL 0x000... ???)
[000055] ---XG------- | /--* CAST int <- long
[000053] ---XG------- | | | /--* HWIntrinsic long PopCount
[000052] *--XG------- | | | | \--* IND long
[000049] ------------ | | | | | /--* CAST long <- int
[000048] ------------ | | | | | | \--* CNS_INT int 8
[000050] ------------ | | | | | /--* MUL long
[000047] ------------ | | | | | | \--* CAST long <- int
[000046] ------------ | | | | | | \--* CNS_INT int 3
[000051] ------------ | | | | \--* ADD long
[000045] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000054] ---XG------- | | \--* ADD long
[000043] ---XG------- | | | /--* HWIntrinsic long PopCount
[000042] *--XG------- | | | | \--* IND long
[000039] ------------ | | | | | /--* CAST long <- int
[000038] ------------ | | | | | | \--* CNS_INT int 8
[000040] ------------ | | | | | /--* MUL long
[000037] ------------ | | | | | | \--* CAST long <- int
[000036] ------------ | | | | | | \--* CNS_INT int 2
[000041] ------------ | | | | \--* ADD long
[000035] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000044] ---XG------- | | \--* ADD long
[000033] ---XG------- | | | /--* HWIntrinsic long PopCount
[000032] *--XG------- | | | | \--* IND long
[000030] ------------ | | | | | /--* CAST long <- int
[000029] ------------ | | | | | | \--* CNS_INT int 8
[000031] ------------ | | | | \--* ADD long
[000028] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000034] ---XG------- | | \--* ADD long
[000027] ---XG------- | | \--* HWIntrinsic long PopCount
[000026] *--XG------- | | \--* IND long
[000025] ------------ | | \--* LCL_VAR long V03 tmp2
[000056] ---XG------- | /--* SUB int
[000024] ------------ | | \--* LCL_VAR int V04 tmp3
[000059] -A-XG------- \--* ASG int
[000058] D------N---- \--* LCL_VAR int V04 tmp3
***** BB03, stmt 8
[000070] ------------ * STMT void (IL 0x000... ???)
[000065] ------------ | /--* CAST long <- int
[000064] ------------ | | \--* CNS_INT int 8
[000066] ------------ | /--* MUL long
[000063] ------------ | | \--* CAST long <- int
[000062] ------------ | | \--* CNS_INT int 4
[000067] ------------ | /--* ADD long
[000061] ------------ | | \--* LCL_VAR long V03 tmp2
[000069] -A---------- \--* ASG long
[000068] D------N---- \--* LCL_VAR long V03 tmp2
------------ BB04 [000..001) -> BB03 (cond), preds={} succs={BB05,BB03}
***** BB04, stmt 9
[000022] ------------ * STMT void (IL 0x000... ???)
[000021] ------------ \--* JTRUE void
[000019] ------------ | /--* CNS_INT int 256
[000020] ------------ \--* GE int
[000018] ------------ \--* LCL_VAR int V04 tmp3
------------ BB05 [000..001) -> BB07 (always), preds={} succs={BB07}
***** BB05, stmt 10
[000075] ------------ * STMT void (IL 0x000... ???)
[000072] ------------ | /--* LCL_VAR int V04 tmp3
[000074] -A---------- \--* ASG int
[000073] D------N---- \--* LCL_VAR int V05 tmp4
------------ BB06 [000..001), preds={} succs={BB07}
***** BB06, stmt 11
[000086] ------------ * STMT void (IL 0x000... ???)
[000083] ------------ | /--* LCL_VAR int V04 tmp3
[000085] -A---------- \--* ASG int
[000084] D------N---- \--* LCL_VAR int V05 tmp4
***** BB06, stmt 12
[000096] ------------ * STMT void (IL 0x000... ???)
[000091] ---XG------- | /--* CAST int <- long
[000090] ---XG------- | | \--* HWIntrinsic long PopCount
[000089] *--XG------- | | \--* IND long
[000088] ------------ | | \--* LCL_VAR long V03 tmp2
[000092] ---XG------- | /--* SUB int
[000087] ------------ | | \--* LCL_VAR int V04 tmp3
[000095] -A-XG------- \--* ASG int
[000094] D------N---- \--* LCL_VAR int V04 tmp3
***** BB06, stmt 13
[000103] ------------ * STMT void (IL 0x000... ???)
[000099] ------------ | /--* CAST long <- int
[000098] ------------ | | \--* CNS_INT int 8
[000100] ------------ | /--* ADD long
[000097] ------------ | | \--* LCL_VAR long V03 tmp2
[000102] -A---------- \--* ASG long
[000101] D------N---- \--* LCL_VAR long V03 tmp2
------------ BB07 [000..001) -> BB06 (cond), preds={} succs={BB08,BB06}
***** BB07, stmt 14
[000081] ------------ * STMT void (IL 0x000... ???)
[000080] ------------ \--* JTRUE void
[000078] ------------ | /--* CNS_INT int 0
[000079] ------------ \--* GT int
[000077] ------------ \--* LCL_VAR int V04 tmp3
------------ BB08 [000..001), preds={} succs={BB09}
***** BB08, stmt 15
[000111] ------------ * STMT void (IL 0x000... ???)
[000107] ------------ | /--* CAST long <- int
[000106] ------------ | | \--* CNS_INT int 8
[000108] ------------ | /--* SUB long
[000105] ------------ | | \--* LCL_VAR long V03 tmp2
[000110] -A---------- \--* ASG long
[000109] D------N---- \--* LCL_VAR long V03 tmp2
***** BB08, stmt 16
[000127] ------------ * STMT void (IL 0x000... ???)
[000124] ---XG------- | /--* CAST int <- long
[000123] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
[000121] *--XG------- | | | /--* IND long
[000120] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000122] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
[000117] ------------ | | | /--* CNS_INT int 63
[000118] ------------ | | | /--* AND int
[000115] ------------ | | | | | /--* CNS_INT int 1
[000116] ------------ | | | | \--* SUB int
[000114] ------------ | | | | \--* LCL_VAR int V05 tmp4
[000119] ------------ | | \--* LSH long
[000113] ------------ | | \--* CAST long <- int
[000112] ------------ | | \--* CNS_INT int 1
[000126] -A-XG------- \--* ASG int
[000125] D------N---- \--* LCL_VAR int V06 tmp5
------------ BB09 [???..???) (return), preds={} succs={}
***** BB09, stmt 17
[000011] ------------ * STMT void (IL ???... ???)
[000010] --C--------- \--* RETURN int
[000138] ------------ | /--* LCL_VAR int V06 tmp5
[000139] ---X-------- \--* ADD int
[000137] ---X-------- \--* CAST int <- long
[000135] ------------ | /--* CAST long <- int
[000134] ------------ | | \--* CNS_INT int 64
[000136] ---X-------- \--* MUL long
[000132] ------------ | /--* CAST long <- int
[000131] ------------ | | \--* CNS_INT int 8
[000133] ---X-------- \--* DIV long
[000129] ------------ | /--* LCL_VAR long V02 tmp1
[000130] ------------ \--* SUB long
[000128] ------------ \--* LCL_VAR long V03 tmp2
-------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
**************** Inline Tree
Inlines into 06000007 Program:IntrinsicsUnrolled(int):int
[1 IL=0011 TR=000004 06000008] [aggressive inline attribute] GetNthBitOffset:IntrinsicsUnrolled(long,int,int):int
Budget: initialTime=111, finalTime=365, initialBudget=1110, currentBudget=1364
Budget: increased by 254 because of force inlines
Budget: initialSize=518, finalSize=518
*************** After fgAddInternal()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i
BB02 [0001] 1 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 0.50 [000..001) i bwd
BB04 [0003] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB05 [0004] 1 0.50 [000..001)-> BB07 (always) i
BB06 [0005] 1 0.50 [000..001) i bwd
BB07 [0006] 2 0.50 [000..001)-> BB06 ( cond ) i bwd
BB08 [0007] 1 1 [000..001) i
BB09 [0008] 1 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** In fgPromoteStructs()
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk (na)
; V02 tmp1 long
; V03 tmp2 long
; V04 tmp3 int
; V05 tmp4 int
; V06 tmp5 int
lvaTable after fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk (na)
; V02 tmp1 long
; V03 tmp2 long
; V04 tmp3 int
; V05 tmp4 int
; V06 tmp5 int
*************** In fgMarkAddressExposedLocals()
*************** In fgMorphBlocks()
Morphing BB01 of 'Program:IntrinsicsUnrolled(int):int'
fgMorphTree BB01, stmt 1 (before)
[000001] ----G------- /--* FIELD long _bits
[000141] -A--G------- * ASG long
[000140] D------N---- \--* LCL_VAR long V02 tmp1
fgMorphTree BB01, stmt 1 (after)
[000001] x---G+------ /--* IND long
[000159] -----+------ | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits]
[000141] -A--G+------ * ASG long
[000140] D----+-N---- \--* LCL_VAR long V02 tmp1
fgMorphTree BB01, stmt 2 (before)
[000003] ------------ /--* LCL_VAR int V00 arg0
[000144] -A---------- * ASG int
[000143] D------N---- \--* LCL_VAR int V04 tmp3
GenTreeNode creates assertion:
[000144] -A---------- * ASG int
In BB01 New Local Copy Assertion: V04 == V00 index=#01, mask=0000000000000001
fgMorphTree BB01, stmt 3 (before)
[000146] ------------ /--* CNS_INT long 0
[000148] -A---------- * ASG long
[000147] D------N---- \--* LCL_VAR long V03 tmp2
GenTreeNode creates assertion:
[000148] -A---------- * ASG long
In BB01 New Local Constant Assertion: V03 == 0 index=#02, mask=0000000000000002
fgMorphTree BB01, stmt 4 (before)
[000150] ------------ /--* CNS_INT int 0
[000152] -A---------- * ASG int
[000151] D------N---- \--* LCL_VAR int V05 tmp4
GenTreeNode creates assertion:
[000152] -A---------- * ASG int
In BB01 New Local Constant Assertion: V05 == 0 index=#03, mask=0000000000000004
fgMorphTree BB01, stmt 5 (before)
[000154] ------------ /--* CNS_INT int 0
[000156] -A---------- * ASG int
[000155] D------N---- \--* LCL_VAR int V06 tmp5
GenTreeNode creates assertion:
[000156] -A---------- * ASG int
In BB01 New Local Constant Assertion: V06 == 0 index=#04, mask=0000000000000008
Morphing BB02 of 'Program:IntrinsicsUnrolled(int):int'
fgMorphTree BB02, stmt 6 (before)
[000013] ------------ /--* LCL_VAR long V02 tmp1
[000015] -A---------- * ASG long
[000014] D------N---- \--* LCL_VAR long V03 tmp2
GenTreeNode creates assertion:
[000015] -A---------- * ASG long
In BB02 New Local Copy Assertion: V03 == V02 index=#01, mask=0000000000000001
Morphing BB03 of 'Program:IntrinsicsUnrolled(int):int'
fgMorphTree BB03, stmt 7 (before)
[000055] ---XG------- /--* CAST int <- long
[000053] ---XG------- | | /--* HWIntrinsic long PopCount
[000052] *--XG------- | | | \--* IND long
[000049] ------------ | | | | /--* CAST long <- int
[000048] ------------ | | | | | \--* CNS_INT int 8
[000050] ------------ | | | | /--* MUL long
[000047] ------------ | | | | | \--* CAST long <- int
[000046] ------------ | | | | | \--* CNS_INT int 3
[000051] ------------ | | | \--* ADD long
[000045] ------------ | | | \--* LCL_VAR long V03 tmp2
[000054] ---XG------- | \--* ADD long
[000043] ---XG------- | | /--* HWIntrinsic long PopCount
[000042] *--XG------- | | | \--* IND long
[000039] ------------ | | | | /--* CAST long <- int
[000038] ------------ | | | | | \--* CNS_INT int 8
[000040] ------------ | | | | /--* MUL long
[000037] ------------ | | | | | \--* CAST long <- int
[000036] ------------ | | | | | \--* CNS_INT int 2
[000041] ------------ | | | \--* ADD long
[000035] ------------ | | | \--* LCL_VAR long V03 tmp2
[000044] ---XG------- | \--* ADD long
[000033] ---XG------- | | /--* HWIntrinsic long PopCount
[000032] *--XG------- | | | \--* IND long
[000030] ------------ | | | | /--* CAST long <- int
[000029] ------------ | | | | | \--* CNS_INT int 8
[000031] ------------ | | | \--* ADD long
[000028] ------------ | | | \--* LCL_VAR long V03 tmp2
[000034] ---XG------- | \--* ADD long
[000027] ---XG------- | \--* HWIntrinsic long PopCount
[000026] *--XG------- | \--* IND long
[000025] ------------ | \--* LCL_VAR long V03 tmp2
[000056] ---XG------- /--* SUB int
[000024] ------------ | \--* LCL_VAR int V04 tmp3
[000059] -A-XG------- * ASG int
[000058] D------N---- \--* LCL_VAR int V04 tmp3
Folding long operator with constant nodes into a constant:
[000030] ------------ * CAST long <- int
[000029] -----+------ \--* CNS_INT int 8
Bashed to long constant:
[000030] ------------ * CNS_INT long 8
Folding long operator with constant nodes into a constant:
[000037] ------------ * CAST long <- int
[000036] -----+------ \--* CNS_INT int 2
Bashed to long constant:
[000037] ------------ * CNS_INT long 2
Folding long operator with constant nodes into a constant:
[000039] ------------ * CAST long <- int
[000038] -----+------ \--* CNS_INT int 8
Bashed to long constant:
[000039] ------------ * CNS_INT long 8
Folding long operator with constant nodes into a constant:
[000039] -----+------ /--* CNS_INT long 8
[000040] ------------ * MUL long
[000037] -----+------ \--* CNS_INT long 2
Bashed to long constant:
[000040] ------------ * CNS_INT long 16
Folding long operator with constant nodes into a constant:
[000047] ------------ * CAST long <- int
[000046] -----+------ \--* CNS_INT int 3
Bashed to long constant:
[000047] ------------ * CNS_INT long 3
Folding long operator with constant nodes into a constant:
[000049] ------------ * CAST long <- int
[000048] -----+------ \--* CNS_INT int 8
Bashed to long constant:
[000049] ------------ * CNS_INT long 8
Folding long operator with constant nodes into a constant:
[000049] -----+------ /--* CNS_INT long 8
[000050] ------------ * MUL long
[000047] -----+------ \--* CNS_INT long 3
Bashed to long constant:
[000050] ------------ * CNS_INT long 24
fgMorphTree BB03, stmt 7 (after)
[000161] ---XG+------ /--* CAST int <- long
[000053] ---XG+------ | \--* HWIntrinsic long PopCount
[000052] *--XG+------ | \--* IND long
[000050] -----+------ | | /--* CNS_INT long 24
[000051] -----+------ | \--* ADD long
[000045] -----+------ | \--* LCL_VAR long V03 tmp2
[000054] ---XG+------ /--* ADD int
[000163] ---XG+------ | | /--* CAST int <- long
[000043] ---XG+------ | | | \--* HWIntrinsic long PopCount
[000042] *--XG+------ | | | \--* IND long
[000040] -----+------ | | | | /--* CNS_INT long 16
[000041] -----+------ | | | \--* ADD long
[000035] -----+------ | | | \--* LCL_VAR long V03 tmp2
[000044] ---XG+------ | \--* ADD int
[000165] ---XG+------ | | /--* CAST int <- long
[000033] ---XG+------ | | | \--* HWIntrinsic long PopCount
[000032] *--XG+------ | | | \--* IND long
[000030] -----+------ | | | | /--* CNS_INT long 8
[000031] -----+------ | | | \--* ADD long
[000028] -----+------ | | | \--* LCL_VAR long V03 tmp2
[000034] ---XG+------ | \--* ADD int
[000164] ---XG+------ | \--* CAST int <- long
[000027] ---XG+------ | \--* HWIntrinsic long PopCount
[000026] *--XG+------ | \--* IND long
[000025] -----+------ | \--* LCL_VAR long V03 tmp2
[000056] ---XG+------ /--* SUB int
[000024] -----+------ | \--* LCL_VAR int V04 tmp3
[000059] -A-XG+------ * ASG int
[000058] D----+-N---- \--* LCL_VAR int V04 tmp3
fgMorphTree BB03, stmt 8 (before)
[000065] ------------ /--* CAST long <- int
[000064] ------------ | \--* CNS_INT int 8
[000066] ------------ /--* MUL long
[000063] ------------ | \--* CAST long <- int
[000062] ------------ | \--* CNS_INT int 4
[000067] ------------ /--* ADD long
[000061] ------------ | \--* LCL_VAR long V03 tmp2
[000069] -A---------- * ASG long
[000068] D------N---- \--* LCL_VAR long V03 tmp2
Folding long operator with constant nodes into a constant:
[000063] ------------ * CAST long <- int
[000062] -----+------ \--* CNS_INT int 4
Bashed to long constant:
[000063] ------------ * CNS_INT long 4
Folding long operator with constant nodes into a constant:
[000065] ------------ * CAST long <- int
[000064] -----+------ \--* CNS_INT int 8
Bashed to long constant:
[000065] ------------ * CNS_INT long 8
Folding long operator with constant nodes into a constant:
[000065] -----+------ /--* CNS_INT long 8
[000066] ------------ * MUL long
[000063] -----+------ \--* CNS_INT long 4
Bashed to long constant:
[000066] ------------ * CNS_INT long 32
fgMorphTree BB03, stmt 8 (after)
[000066] -----+------ /--* CNS_INT long 32
[000067] -----+------ /--* ADD long
[000061] -----+------ | \--* LCL_VAR long V03 tmp2
[000069] -A---+------ * ASG long
[000068] D----+-N---- \--* LCL_VAR long V03 tmp2
Morphing BB04 of 'Program:IntrinsicsUnrolled(int):int'
fgMorphTree BB04, stmt 9 (before)
[000021] ------------ * JTRUE void
[000019] ------------ | /--* CNS_INT int 256
[000020] ------------ \--* GE int
[000018] ------------ \--* LCL_VAR int V04 tmp3
Morphing BB05 of 'Program:IntrinsicsUnrolled(int):int'
fgMorphTree BB05, stmt 10 (before)
[000072] ------------ /--* LCL_VAR int V04 tmp3
[000074] -A---------- * ASG int
[000073] D------N---- \--* LCL_VAR int V05 tmp4
GenTreeNode creates assertion:
[000074] -A---------- * ASG int
In BB05 New Local Copy Assertion: V05 == V04 index=#01, mask=0000000000000001
Morphing BB06 of 'Program:IntrinsicsUnrolled(int):int'
fgMorphTree BB06, stmt 11 (before)
[000083] ------------ /--* LCL_VAR int V04 tmp3
[000085] -A---------- * ASG int
[000084] D------N---- \--* LCL_VAR int V05 tmp4
GenTreeNode creates assertion:
[000085] -A---------- * ASG int
In BB06 New Local Copy Assertion: V05 == V04 index=#01, mask=0000000000000001
fgMorphTree BB06, stmt 12 (before)
[000091] ---XG------- /--* CAST int <- long
[000090] ---XG------- | \--* HWIntrinsic long PopCount
[000089] *--XG------- | \--* IND long
[000088] ------------ | \--* LCL_VAR long V03 tmp2
[000092] ---XG------- /--* SUB int
[000087] ------------ | \--* LCL_VAR int V04 tmp3
[000095] -A-XG------- * ASG int
[000094] D------N---- \--* LCL_VAR int V04 tmp3
The assignment [000095] using V05 removes: Copy Assertion: V05 == V04
fgMorphTree BB06, stmt 13 (before)
[000099] ------------ /--* CAST long <- int
[000098] ------------ | \--* CNS_INT int 8
[000100] ------------ /--* ADD long
[000097] ------------ | \--* LCL_VAR long V03 tmp2
[000102] -A---------- * ASG long
[000101] D------N---- \--* LCL_VAR long V03 tmp2
Folding long operator with constant nodes into a constant:
[000099] ------------ * CAST long <- int
[000098] -----+------ \--* CNS_INT int 8
Bashed to long constant:
[000099] ------------ * CNS_INT long 8
fgMorphTree BB06, stmt 13 (after)
[000099] -----+------ /--* CNS_INT long 8
[000100] -----+------ /--* ADD long
[000097] -----+------ | \--* LCL_VAR long V03 tmp2
[000102] -A---+------ * ASG long
[000101] D----+-N---- \--* LCL_VAR long V03 tmp2
Morphing BB07 of 'Program:IntrinsicsUnrolled(int):int'
fgMorphTree BB07, stmt 14 (before)
[000080] ------------ * JTRUE void
[000078] ------------ | /--* CNS_INT int 0
[000079] ------------ \--* GT int
[000077] ------------ \--* LCL_VAR int V04 tmp3
Morphing BB08 of 'Program:IntrinsicsUnrolled(int):int'
fgMorphTree BB08, stmt 15 (before)
[000107] ------------ /--* CAST long <- int
[000106] ------------ | \--* CNS_INT int 8
[000108] ------------ /--* SUB long
[000105] ------------ | \--* LCL_VAR long V03 tmp2
[000110] -A---------- * ASG long
[000109] D------N---- \--* LCL_VAR long V03 tmp2
Folding long operator with constant nodes into a constant:
[000107] ------------ * CAST long <- int
[000106] -----+------ \--* CNS_INT int 8
Bashed to long constant:
[000107] ------------ * CNS_INT long 8
fgMorphTree BB08, stmt 15 (after)
[000107] -----+------ /--* CNS_INT long -8
[000108] -----+------ /--* ADD long
[000105] -----+------ | \--* LCL_VAR long V03 tmp2
[000110] -A---+------ * ASG long
[000109] D----+-N---- \--* LCL_VAR long V03 tmp2
fgMorphTree BB08, stmt 16 (before)
[000124] ---XG------- /--* CAST int <- long
[000123] ---XG------- | \--* HWIntrinsic long TrailingZeroCount
[000121] *--XG------- | | /--* IND long
[000120] ------------ | | | \--* LCL_VAR long V03 tmp2
[000122] ---XG------- | \--* HWIntrinsic long ParallelBitDeposit
[000117] ------------ | | /--* CNS_INT int 63
[000118] ------------ | | /--* AND int
[000115] ------------ | | | | /--* CNS_INT int 1
[000116] ------------ | | | \--* SUB int
[000114] ------------ | | | \--* LCL_VAR int V05 tmp4
[000119] ------------ | \--* LSH long
[000113] ------------ | \--* CAST long <- int
[000112] ------------ | \--* CNS_INT int 1
[000126] -A-XG------- * ASG int
[000125] D------N---- \--* LCL_VAR int V06 tmp5
Folding long operator with constant nodes into a constant:
[000113] ------------ * CAST long <- int
[000112] -----+------ \--* CNS_INT int 1
Bashed to long constant:
[000113] ------------ * CNS_INT long 1
GenTreeNode creates assertion:
[000126] -A-XG------- * ASG int
In BB08 New Local Subrange Assertion: V06 in [-2147483648..2147483647] index=#01, mask=0000000000000001
fgMorphTree BB08, stmt 16 (after)
[000124] ---XG+------ /--* CAST int <- long
[000123] ---XG+------ | \--* HWIntrinsic long TrailingZeroCount
[000121] *--XG+------ | | /--* IND long
[000120] -----+------ | | | \--* LCL_VAR long V03 tmp2
[000122] ---XG+------ | \--* HWIntrinsic long ParallelBitDeposit
[000117] -----+------ | | /--* CNS_INT int 63
[000118] -----+------ | | /--* AND int
[000115] -----+------ | | | | /--* CNS_INT int -1
[000116] -----+------ | | | \--* ADD int
[000114] -----+------ | | | \--* LCL_VAR int V05 tmp4
[000119] -----+------ | \--* LSH long
[000113] -----+------ | \--* CNS_INT long 1
[000126] -A-XG+------ * ASG int
[000125] D----+-N---- \--* LCL_VAR int V06 tmp5
Morphing BB09 of 'Program:IntrinsicsUnrolled(int):int'
fgMorphTree BB09, stmt 17 (before)
[000010] --C--------- * RETURN int
[000138] ------------ | /--* LCL_VAR int V06 tmp5
[000139] ---X-------- \--* ADD int
[000137] ---X-------- \--* CAST int <- long
[000135] ------------ | /--* CAST long <- int
[000134] ------------ | | \--* CNS_INT int 64
[000136] ---X-------- \--* MUL long
[000132] ------------ | /--* CAST long <- int
[000131] ------------ | | \--* CNS_INT int 8
[000133] ---X-------- \--* DIV long
[000129] ------------ | /--* LCL_VAR long V02 tmp1
[000130] ------------ \--* SUB long
[000128] ------------ \--* LCL_VAR long V03 tmp2
Folding long operator with constant nodes into a constant:
[000132] ------------ * CAST long <- int
[000131] ------------ \--* CNS_INT int 8
Bashed to long constant:
[000132] ------------ * CNS_INT long 8
Folding long operator with constant nodes into a constant:
[000135] ------------ * CAST long <- int
[000134] -----+------ \--* CNS_INT int 64
Bashed to long constant:
[000135] ------------ * CNS_INT long 64
fgMorphTree BB09, stmt 17 (after)
[000010] -----+------ * RETURN int
[000138] -----+------ | /--* LCL_VAR int V06 tmp5
[000139] -----+------ \--* ADD int
[000135] -----+------ | /--* CNS_INT int 6
[000136] -----+------ \--* LSH int
[000166] -----+------ \--* CAST int <- long
[000132] -----+------ | /--* CNS_INT long 8
[000133] -----+------ \--* DIV long
[000129] -----+------ | /--* LCL_VAR long V02 tmp1
[000130] -----+------ \--* SUB long
[000128] -----+------ \--* LCL_VAR long V03 tmp2
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i
BB02 [0001] 1 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 0.50 [000..001) i bwd
BB04 [0003] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB05 [0004] 1 0.50 [000..001)-> BB07 (always) i
BB06 [0005] 1 0.50 [000..001) i bwd
BB07 [0006] 2 0.50 [000..001)-> BB06 ( cond ) i bwd
BB08 [0007] 1 1 [000..001) i
BB09 [0008] 1 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
New BlockSet epoch 2, # of blocks (including unused BB00): 10, bitset array size: 1 (short)
*************** In fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i
BB02 [0001] 1 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 0.50 [000..001) i bwd
BB04 [0003] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB05 [0004] 1 0.50 [000..001)-> BB07 (always) i
BB06 [0005] 1 0.50 [000..001) i bwd
BB07 [0006] 2 0.50 [000..001)-> BB06 ( cond ) i bwd
BB08 [0007] 1 1 [000..001) i
BB09 [0008] 1 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 BB04 0.50 [000..001) i label target bwd
BB04 [0003] 2 BB02,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 1 BB04 0.50 [000..001)-> BB07 (always) i
BB06 [0005] 1 BB07 0.50 [000..001) i label target bwd
BB07 [0006] 2 BB05,BB06 0.50 [000..001)-> BB06 ( cond ) i label target bwd
BB08 [0007] 1 BB07 1 [000..001) i
BB09 [0008] 1 BB08 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeEdgeWeights()
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 BB04 0.50 [000..001) i label target bwd
BB04 [0003] 2 BB02,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 1 BB04 0.50 [000..001)-> BB07 (always) i
BB06 [0005] 1 BB07 0.50 [000..001) i label target bwd
BB07 [0006] 2 BB05,BB06 0.50 [000..001)-> BB06 ( cond ) i label target bwd
BB08 [0007] 1 BB07 1 [000..001) i
BB09 [0008] 1 BB08 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights
*************** In fgCreateFunclets()
After fgCreateFunclets()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 BB04 0.50 [000..001) i label target bwd
BB04 [0003] 2 BB02,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 1 BB04 0.50 [000..001)-> BB07 (always) i
BB06 [0005] 1 BB07 0.50 [000..001) i label target bwd
BB07 [0006] 2 BB05,BB06 0.50 [000..001)-> BB06 ( cond ) i label target bwd
BB08 [0007] 1 BB07 1 [000..001) i
BB09 [0008] 1 BB08 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In optOptimizeLayout()
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
Duplication of loop condition [000020] is performed, because the cost of duplication (7) is less or equal than 32,
loopIterations = 8.000, countOfHelpers = 0, validProfileWeights = false
Duplicating loop condition in BB02 for loop (BB03 - BB04)
Estimated code size expansion is 7
[000172] ------------ * STMT void (IL 0x000... ???)
[000171] ------------ \--* JTRUE void
( 1, 4) [000170] ------------ | /--* CNS_INT int 256
( 5, 7) [000168] J------N---- \--* LT int
( 3, 2) [000169] ------------ \--* LCL_VAR int V04 tmp3
Duplication of loop condition [000079] is performed, because the cost of duplication (4) is less or equal than 32,
loopIterations = 8.000, countOfHelpers = 0, validProfileWeights = false
Duplicating loop condition in BB05 for loop (BB06 - BB07)
Estimated code size expansion is 4
[000177] ------------ * STMT void (IL 0x000... ???)
[000176] ------------ \--* JTRUE void
( 1, 1) [000175] ------------ | /--* CNS_INT int 0
( 5, 4) [000173] J------N---- \--* LE int
( 3, 2) [000174] ------------ \--* LCL_VAR int V04 tmp3
*************** In fgComputeEdgeWeights()
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001)-> BB05 ( cond ) i
BB03 [0002] 2 BB02,BB04 0.50 [000..001) i label target bwd
BB04 [0003] 1 BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 2 BB02,BB04 0.50 [000..001)-> BB08 ( cond ) i label target
BB06 [0005] 2 BB05,BB07 0.50 [000..001) i label target bwd
BB07 [0006] 1 BB06 0.50 [000..001)-> BB06 ( cond ) i label target bwd
BB08 [0007] 2 BB05,BB07 1 [000..001) i label target
BB09 [0008] 1 BB08 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001)-> BB05 ( cond ) i
BB03 [0002] 2 BB02,BB04 0.50 [000..001) i label target bwd
BB04 [0003] 1 BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 2 BB02,BB04 0.50 [000..001)-> BB08 ( cond ) i label target
BB06 [0005] 2 BB05,BB07 0.50 [000..001) i label target bwd
BB07 [0006] 1 BB06 0.50 [000..001)-> BB06 ( cond ) i label target bwd
BB08 [0007] 2 BB05,BB07 1 [000..001) i label target
BB09 [0008] 1 BB08 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
Compacting blocks BB01 and BB02:
*************** In fgDebugCheckBBlist
Compacting blocks BB03 and BB04:
*************** In fgDebugCheckBBlist
Compacting blocks BB06 and BB07:
*************** In fgDebugCheckBBlist
Compacting blocks BB08 and BB09:
*************** In fgDebugCheckBBlist
After updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB05 ( cond ) i label target
BB03 [0002] 2 BB01,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 2 BB01,BB03 0.50 [000..001)-> BB08 ( cond ) i label target
BB06 [0005] 2 BB05,BB06 0.50 [000..001)-> BB06 ( cond ) i label target bwd
BB08 [0007] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** In fgReorderBlocks()
Initial BasicBlocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB05 ( cond ) i label target
BB03 [0002] 2 BB01,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 2 BB01,BB03 0.50 [000..001)-> BB08 ( cond ) i label target
BB06 [0005] 2 BB05,BB06 0.50 [000..001)-> BB06 ( cond ) i label target bwd
BB08 [0007] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB05 ( cond ) i label target
BB03 [0002] 2 BB01,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 2 BB01,BB03 0.50 [000..001)-> BB08 ( cond ) i label target
BB06 [0005] 2 BB05,BB06 0.50 [000..001)-> BB06 ( cond ) i label target bwd
BB08 [0007] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB05 ( cond ) i label target
BB03 [0002] 2 BB01,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 2 BB01,BB03 0.50 [000..001)-> BB08 ( cond ) i label target
BB06 [0005] 2 BB05,BB06 0.50 [000..001)-> BB06 ( cond ) i label target bwd
BB08 [0007] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB05 to BB03
Renumber BB06 to BB04
Renumber BB08 to BB05
*************** After renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 0.50 [000..001)-> BB02 ( cond ) i label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 0.50 [000..001)-> BB04 ( cond ) i label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 3, # of blocks (including unused BB00): 6, bitset array size: 1 (short)
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
BB02 : BB01 BB02
BB03 : BB01 BB02 BB03
BB04 : BB01 BB02 BB03 BB04
BB05 : BB01 BB02 BB03 BB04 BB05
After computing reachability:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 0.50 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 0.50 [000..001)-> BB04 ( cond ) i Loop label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
BB02: BB02 BB01
BB03: BB03 BB01
BB04: BB04 BB03 BB01
BB05: BB05 BB03 BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB03 BB02
BB03 : BB05 BB04
*************** In Allocate Objects
Trees before Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 0.50 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 0.50 [000..001)-> BB04 ( cond ) i Loop label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000142] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000159] -----+------ | | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits]
[000141] -A--G+------ \--* ASG long
[000140] D----+-N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000145] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000144] -A---+------ \--* ASG int
[000143] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000149] ------------ * STMT void (IL 0x000... ???)
[000146] -----+------ | /--* CNS_INT long 0
[000148] -A---+------ \--* ASG long
[000147] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000153] ------------ * STMT void (IL 0x000... ???)
[000150] -----+------ | /--* CNS_INT int 0
[000152] -A---+------ \--* ASG int
[000151] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000157] ------------ * STMT void (IL 0x000... ???)
[000154] -----+------ | /--* CNS_INT int 0
[000156] -A---+------ \--* ASG int
[000155] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB01, stmt 6
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 7
[000172] ------------ * STMT void (IL 0x000... ???)
[000171] ------------ \--* JTRUE void
( 1, 4) [000170] ------------ | /--* CNS_INT int 256
( 5, 7) [000168] J------N---- \--* LT int
( 3, 2) [000169] ------------ \--* LCL_VAR int V04 tmp3
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 8
[000060] ------------ * STMT void (IL 0x000... ???)
[000161] ---XG+------ | /--* CAST int <- long
[000053] ---XG+------ | | \--* HWIntrinsic long PopCount
[000052] *--XG+------ | | \--* IND long
[000050] -----+------ | | | /--* CNS_INT long 24
[000051] -----+------ | | \--* ADD long
[000045] -----+------ | | \--* LCL_VAR long V03 tmp2
[000054] ---XG+------ | /--* ADD int
[000163] ---XG+------ | | | /--* CAST int <- long
[000043] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000042] *--XG+------ | | | | \--* IND long
[000040] -----+------ | | | | | /--* CNS_INT long 16
[000041] -----+------ | | | | \--* ADD long
[000035] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000044] ---XG+------ | | \--* ADD int
[000165] ---XG+------ | | | /--* CAST int <- long
[000033] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000032] *--XG+------ | | | | \--* IND long
[000030] -----+------ | | | | | /--* CNS_INT long 8
[000031] -----+------ | | | | \--* ADD long
[000028] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000034] ---XG+------ | | \--* ADD int
[000164] ---XG+------ | | \--* CAST int <- long
[000027] ---XG+------ | | \--* HWIntrinsic long PopCount
[000026] *--XG+------ | | \--* IND long
[000025] -----+------ | | \--* LCL_VAR long V03 tmp2
[000056] ---XG+------ | /--* SUB int
[000024] -----+------ | | \--* LCL_VAR int V04 tmp3
[000059] -A-XG+------ \--* ASG int
[000058] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 9
[000070] ------------ * STMT void (IL 0x000... ???)
[000066] -----+------ | /--* CNS_INT long 32
[000067] -----+------ | /--* ADD long
[000061] -----+------ | | \--* LCL_VAR long V03 tmp2
[000069] -A---+------ \--* ASG long
[000068] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 10
[000022] ------------ * STMT void (IL 0x000... ???)
[000021] -----+------ \--* JTRUE void
( 1, 4) [000019] ------------ | /--* CNS_INT int 256
( 5, 7) [000020] J------N---- \--* GE int
( 3, 2) [000018] ------------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 11
[000075] ------------ * STMT void (IL 0x000... ???)
[000072] -----+------ | /--* LCL_VAR int V04 tmp3
[000074] -A---+------ \--* ASG int
[000073] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB03, stmt 12
[000177] ------------ * STMT void (IL 0x000... ???)
[000176] ------------ \--* JTRUE void
( 1, 1) [000175] ------------ | /--* CNS_INT int 0
( 5, 4) [000173] J------N---- \--* LE int
( 3, 2) [000174] ------------ \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
***** BB04, stmt 13
[000086] ------------ * STMT void (IL 0x000... ???)
[000083] -----+------ | /--* LCL_VAR int V04 tmp3
[000085] -A---+------ \--* ASG int
[000084] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB04, stmt 14
[000096] ------------ * STMT void (IL 0x000... ???)
[000091] ---XG+------ | /--* CAST int <- long
[000090] ---XG+------ | | \--* HWIntrinsic long PopCount
[000089] *--XG+------ | | \--* IND long
[000088] -----+------ | | \--* LCL_VAR long V03 tmp2
[000092] ---XG+------ | /--* SUB int
[000087] -----+------ | | \--* LCL_VAR int V04 tmp3
[000095] -A-XG+------ \--* ASG int
[000094] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB04, stmt 15
[000103] ------------ * STMT void (IL 0x000... ???)
[000099] -----+------ | /--* CNS_INT long 8
[000100] -----+------ | /--* ADD long
[000097] -----+------ | | \--* LCL_VAR long V03 tmp2
[000102] -A---+------ \--* ASG long
[000101] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB04, stmt 16
[000081] ------------ * STMT void (IL 0x000... ???)
[000080] -----+------ \--* JTRUE void
( 1, 1) [000078] ------------ | /--* CNS_INT int 0
( 5, 4) [000079] J------N---- \--* GT int
( 3, 2) [000077] ------------ \--* LCL_VAR int V04 tmp3
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 17
[000111] ------------ * STMT void (IL 0x000... ???)
[000107] -----+------ | /--* CNS_INT long -8
[000108] -----+------ | /--* ADD long
[000105] -----+------ | | \--* LCL_VAR long V03 tmp2
[000110] -A---+------ \--* ASG long
[000109] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB05, stmt 18
[000127] ------------ * STMT void (IL 0x000... ???)
[000124] ---XG+------ | /--* CAST int <- long
[000123] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000121] *--XG+------ | | | /--* IND long
[000120] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000122] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000117] -----+------ | | | /--* CNS_INT int 63
[000118] -----+------ | | | /--* AND int
[000115] -----+------ | | | | | /--* CNS_INT int -1
[000116] -----+------ | | | | \--* ADD int
[000114] -----+------ | | | | \--* LCL_VAR int V05 tmp4
[000119] -----+------ | | \--* LSH long
[000113] -----+------ | | \--* CNS_INT long 1
[000126] -A-XG+------ \--* ASG int
[000125] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB05, stmt 19
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000138] -----+------ | /--* LCL_VAR int V06 tmp5
[000139] -----+------ \--* ADD int
[000135] -----+------ | /--* CNS_INT int 6
[000136] -----+------ \--* LSH int
[000166] -----+------ \--* CAST int <- long
[000132] -----+------ | /--* CNS_INT long 8
[000133] -----+------ \--* DIV long
[000129] -----+------ | /--* LCL_VAR long V02 tmp1
[000130] -----+------ \--* SUB long
[000128] -----+------ \--* LCL_VAR long V03 tmp2
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Allocate Objects
Trees after Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 0.50 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 0.50 [000..001)-> BB04 ( cond ) i Loop label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000142] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000159] -----+------ | | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits]
[000141] -A--G+------ \--* ASG long
[000140] D----+-N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000145] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000144] -A---+------ \--* ASG int
[000143] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000149] ------------ * STMT void (IL 0x000... ???)
[000146] -----+------ | /--* CNS_INT long 0
[000148] -A---+------ \--* ASG long
[000147] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000153] ------------ * STMT void (IL 0x000... ???)
[000150] -----+------ | /--* CNS_INT int 0
[000152] -A---+------ \--* ASG int
[000151] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000157] ------------ * STMT void (IL 0x000... ???)
[000154] -----+------ | /--* CNS_INT int 0
[000156] -A---+------ \--* ASG int
[000155] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB01, stmt 6
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 7
[000172] ------------ * STMT void (IL 0x000... ???)
[000171] ------------ \--* JTRUE void
( 1, 4) [000170] ------------ | /--* CNS_INT int 256
( 5, 7) [000168] J------N---- \--* LT int
( 3, 2) [000169] ------------ \--* LCL_VAR int V04 tmp3
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 8
[000060] ------------ * STMT void (IL 0x000... ???)
[000161] ---XG+------ | /--* CAST int <- long
[000053] ---XG+------ | | \--* HWIntrinsic long PopCount
[000052] *--XG+------ | | \--* IND long
[000050] -----+------ | | | /--* CNS_INT long 24
[000051] -----+------ | | \--* ADD long
[000045] -----+------ | | \--* LCL_VAR long V03 tmp2
[000054] ---XG+------ | /--* ADD int
[000163] ---XG+------ | | | /--* CAST int <- long
[000043] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000042] *--XG+------ | | | | \--* IND long
[000040] -----+------ | | | | | /--* CNS_INT long 16
[000041] -----+------ | | | | \--* ADD long
[000035] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000044] ---XG+------ | | \--* ADD int
[000165] ---XG+------ | | | /--* CAST int <- long
[000033] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000032] *--XG+------ | | | | \--* IND long
[000030] -----+------ | | | | | /--* CNS_INT long 8
[000031] -----+------ | | | | \--* ADD long
[000028] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000034] ---XG+------ | | \--* ADD int
[000164] ---XG+------ | | \--* CAST int <- long
[000027] ---XG+------ | | \--* HWIntrinsic long PopCount
[000026] *--XG+------ | | \--* IND long
[000025] -----+------ | | \--* LCL_VAR long V03 tmp2
[000056] ---XG+------ | /--* SUB int
[000024] -----+------ | | \--* LCL_VAR int V04 tmp3
[000059] -A-XG+------ \--* ASG int
[000058] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 9
[000070] ------------ * STMT void (IL 0x000... ???)
[000066] -----+------ | /--* CNS_INT long 32
[000067] -----+------ | /--* ADD long
[000061] -----+------ | | \--* LCL_VAR long V03 tmp2
[000069] -A---+------ \--* ASG long
[000068] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 10
[000022] ------------ * STMT void (IL 0x000... ???)
[000021] -----+------ \--* JTRUE void
( 1, 4) [000019] ------------ | /--* CNS_INT int 256
( 5, 7) [000020] J------N---- \--* GE int
( 3, 2) [000018] ------------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 11
[000075] ------------ * STMT void (IL 0x000... ???)
[000072] -----+------ | /--* LCL_VAR int V04 tmp3
[000074] -A---+------ \--* ASG int
[000073] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB03, stmt 12
[000177] ------------ * STMT void (IL 0x000... ???)
[000176] ------------ \--* JTRUE void
( 1, 1) [000175] ------------ | /--* CNS_INT int 0
( 5, 4) [000173] J------N---- \--* LE int
( 3, 2) [000174] ------------ \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
***** BB04, stmt 13
[000086] ------------ * STMT void (IL 0x000... ???)
[000083] -----+------ | /--* LCL_VAR int V04 tmp3
[000085] -A---+------ \--* ASG int
[000084] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB04, stmt 14
[000096] ------------ * STMT void (IL 0x000... ???)
[000091] ---XG+------ | /--* CAST int <- long
[000090] ---XG+------ | | \--* HWIntrinsic long PopCount
[000089] *--XG+------ | | \--* IND long
[000088] -----+------ | | \--* LCL_VAR long V03 tmp2
[000092] ---XG+------ | /--* SUB int
[000087] -----+------ | | \--* LCL_VAR int V04 tmp3
[000095] -A-XG+------ \--* ASG int
[000094] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB04, stmt 15
[000103] ------------ * STMT void (IL 0x000... ???)
[000099] -----+------ | /--* CNS_INT long 8
[000100] -----+------ | /--* ADD long
[000097] -----+------ | | \--* LCL_VAR long V03 tmp2
[000102] -A---+------ \--* ASG long
[000101] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB04, stmt 16
[000081] ------------ * STMT void (IL 0x000... ???)
[000080] -----+------ \--* JTRUE void
( 1, 1) [000078] ------------ | /--* CNS_INT int 0
( 5, 4) [000079] J------N---- \--* GT int
( 3, 2) [000077] ------------ \--* LCL_VAR int V04 tmp3
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 17
[000111] ------------ * STMT void (IL 0x000... ???)
[000107] -----+------ | /--* CNS_INT long -8
[000108] -----+------ | /--* ADD long
[000105] -----+------ | | \--* LCL_VAR long V03 tmp2
[000110] -A---+------ \--* ASG long
[000109] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB05, stmt 18
[000127] ------------ * STMT void (IL 0x000... ???)
[000124] ---XG+------ | /--* CAST int <- long
[000123] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000121] *--XG+------ | | | /--* IND long
[000120] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000122] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000117] -----+------ | | | /--* CNS_INT int 63
[000118] -----+------ | | | /--* AND int
[000115] -----+------ | | | | | /--* CNS_INT int -1
[000116] -----+------ | | | | \--* ADD int
[000114] -----+------ | | | | \--* LCL_VAR int V05 tmp4
[000119] -----+------ | | \--* LSH long
[000113] -----+------ | | \--* CNS_INT long 1
[000126] -A-XG+------ \--* ASG int
[000125] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB05, stmt 19
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000138] -----+------ | /--* LCL_VAR int V06 tmp5
[000139] -----+------ \--* ADD int
[000135] -----+------ | /--* CNS_INT int 6
[000136] -----+------ \--* LSH int
[000166] -----+------ \--* CAST int <- long
[000132] -----+------ | /--* CNS_INT long 8
[000133] -----+------ \--* DIV long
[000129] -----+------ | /--* LCL_VAR long V02 tmp1
[000130] -----+------ \--* SUB long
[000128] -----+------ \--* LCL_VAR long V03 tmp2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optOptimizeLoops()
After optSetBlockWeights:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 0.25 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 0.25 [000..001)-> BB04 ( cond ) i Loop label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optFindNaturalLoops()
Recorded loop L00, from BB02 to BB02 (Head=BB01, Entry=BB02, ExitCnt=1 at BB02)
Recorded loop L01, from BB04 to BB04 (Head=BB03, Entry=BB04, ExitCnt=1 at BB04)
Final natural loop table:
L00, from BB02 to BB02 (Head=BB01, Entry=BB02, ExitCnt=1 at BB02)
L01, from BB04 to BB04 (Head=BB03, Entry=BB04, ExitCnt=1 at BB04)
Marking loop L01
BB02(wt=2 )
Marking loop L02
BB04(wt=2 )
Found a total of 2 loops.
After loop weight marking:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In optCloneLoops()
Blocks/Trees at start of phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000142] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000159] -----+------ | | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits]
[000141] -A--G+------ \--* ASG long
[000140] D----+-N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000145] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000144] -A---+------ \--* ASG int
[000143] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000149] ------------ * STMT void (IL 0x000... ???)
[000146] -----+------ | /--* CNS_INT long 0
[000148] -A---+------ \--* ASG long
[000147] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000153] ------------ * STMT void (IL 0x000... ???)
[000150] -----+------ | /--* CNS_INT int 0
[000152] -A---+------ \--* ASG int
[000151] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000157] ------------ * STMT void (IL 0x000... ???)
[000154] -----+------ | /--* CNS_INT int 0
[000156] -A---+------ \--* ASG int
[000155] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB01, stmt 6
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 7
[000172] ------------ * STMT void (IL 0x000... ???)
[000171] ------------ \--* JTRUE void
( 1, 4) [000170] ------------ | /--* CNS_INT int 256
( 5, 7) [000168] J------N---- \--* LT int
( 3, 2) [000169] ------------ \--* LCL_VAR int V04 tmp3
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 8
[000060] ------------ * STMT void (IL 0x000... ???)
[000161] ---XG+------ | /--* CAST int <- long
[000053] ---XG+------ | | \--* HWIntrinsic long PopCount
[000052] *--XG+------ | | \--* IND long
[000050] -----+------ | | | /--* CNS_INT long 24
[000051] -----+------ | | \--* ADD long
[000045] -----+------ | | \--* LCL_VAR long V03 tmp2
[000054] ---XG+------ | /--* ADD int
[000163] ---XG+------ | | | /--* CAST int <- long
[000043] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000042] *--XG+------ | | | | \--* IND long
[000040] -----+------ | | | | | /--* CNS_INT long 16
[000041] -----+------ | | | | \--* ADD long
[000035] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000044] ---XG+------ | | \--* ADD int
[000165] ---XG+------ | | | /--* CAST int <- long
[000033] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000032] *--XG+------ | | | | \--* IND long
[000030] -----+------ | | | | | /--* CNS_INT long 8
[000031] -----+------ | | | | \--* ADD long
[000028] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000034] ---XG+------ | | \--* ADD int
[000164] ---XG+------ | | \--* CAST int <- long
[000027] ---XG+------ | | \--* HWIntrinsic long PopCount
[000026] *--XG+------ | | \--* IND long
[000025] -----+------ | | \--* LCL_VAR long V03 tmp2
[000056] ---XG+------ | /--* SUB int
[000024] -----+------ | | \--* LCL_VAR int V04 tmp3
[000059] -A-XG+------ \--* ASG int
[000058] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 9
[000070] ------------ * STMT void (IL 0x000... ???)
[000066] -----+------ | /--* CNS_INT long 32
[000067] -----+------ | /--* ADD long
[000061] -----+------ | | \--* LCL_VAR long V03 tmp2
[000069] -A---+------ \--* ASG long
[000068] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 10
[000022] ------------ * STMT void (IL 0x000... ???)
[000021] -----+------ \--* JTRUE void
( 1, 4) [000019] ------------ | /--* CNS_INT int 256
( 5, 7) [000020] J------N---- \--* GE int
( 3, 2) [000018] ------------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 11
[000075] ------------ * STMT void (IL 0x000... ???)
[000072] -----+------ | /--* LCL_VAR int V04 tmp3
[000074] -A---+------ \--* ASG int
[000073] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB03, stmt 12
[000177] ------------ * STMT void (IL 0x000... ???)
[000176] ------------ \--* JTRUE void
( 1, 1) [000175] ------------ | /--* CNS_INT int 0
( 5, 4) [000173] J------N---- \--* LE int
( 3, 2) [000174] ------------ \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
***** BB04, stmt 13
[000086] ------------ * STMT void (IL 0x000... ???)
[000083] -----+------ | /--* LCL_VAR int V04 tmp3
[000085] -A---+------ \--* ASG int
[000084] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB04, stmt 14
[000096] ------------ * STMT void (IL 0x000... ???)
[000091] ---XG+------ | /--* CAST int <- long
[000090] ---XG+------ | | \--* HWIntrinsic long PopCount
[000089] *--XG+------ | | \--* IND long
[000088] -----+------ | | \--* LCL_VAR long V03 tmp2
[000092] ---XG+------ | /--* SUB int
[000087] -----+------ | | \--* LCL_VAR int V04 tmp3
[000095] -A-XG+------ \--* ASG int
[000094] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB04, stmt 15
[000103] ------------ * STMT void (IL 0x000... ???)
[000099] -----+------ | /--* CNS_INT long 8
[000100] -----+------ | /--* ADD long
[000097] -----+------ | | \--* LCL_VAR long V03 tmp2
[000102] -A---+------ \--* ASG long
[000101] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB04, stmt 16
[000081] ------------ * STMT void (IL 0x000... ???)
[000080] -----+------ \--* JTRUE void
( 1, 1) [000078] ------------ | /--* CNS_INT int 0
( 5, 4) [000079] J------N---- \--* GT int
( 3, 2) [000077] ------------ \--* LCL_VAR int V04 tmp3
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 17
[000111] ------------ * STMT void (IL 0x000... ???)
[000107] -----+------ | /--* CNS_INT long -8
[000108] -----+------ | /--* ADD long
[000105] -----+------ | | \--* LCL_VAR long V03 tmp2
[000110] -A---+------ \--* ASG long
[000109] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB05, stmt 18
[000127] ------------ * STMT void (IL 0x000... ???)
[000124] ---XG+------ | /--* CAST int <- long
[000123] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000121] *--XG+------ | | | /--* IND long
[000120] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000122] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000117] -----+------ | | | /--* CNS_INT int 63
[000118] -----+------ | | | /--* AND int
[000115] -----+------ | | | | | /--* CNS_INT int -1
[000116] -----+------ | | | | \--* ADD int
[000114] -----+------ | | | | \--* LCL_VAR int V05 tmp4
[000119] -----+------ | | \--* LSH long
[000113] -----+------ | | \--* CNS_INT long 1
[000126] -A-XG+------ \--* ASG int
[000125] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB05, stmt 19
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000138] -----+------ | /--* LCL_VAR int V06 tmp5
[000139] -----+------ \--* ADD int
[000135] -----+------ | /--* CNS_INT int 6
[000136] -----+------ \--* LSH int
[000166] -----+------ \--* CAST int <- long
[000132] -----+------ | /--* CNS_INT long 8
[000133] -----+------ \--* DIV long
[000129] -----+------ | /--* LCL_VAR long V02 tmp1
[000130] -----+------ \--* SUB long
[000128] -----+------ \--* LCL_VAR long V03 tmp2
-------------------------------------------------------------------------------------------------------------------
Considering loop 0 to clone for optimizations.
> No iter flag on loop 0.
------------------------------------------------------------
Considering loop 1 to clone for optimizations.
> No iter flag on loop 1.
------------------------------------------------------------
After loop cloning:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000142] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000159] -----+------ | | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits]
[000141] -A--G+------ \--* ASG long
[000140] D----+-N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000145] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000144] -A---+------ \--* ASG int
[000143] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000149] ------------ * STMT void (IL 0x000... ???)
[000146] -----+------ | /--* CNS_INT long 0
[000148] -A---+------ \--* ASG long
[000147] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000153] ------------ * STMT void (IL 0x000... ???)
[000150] -----+------ | /--* CNS_INT int 0
[000152] -A---+------ \--* ASG int
[000151] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000157] ------------ * STMT void (IL 0x000... ???)
[000154] -----+------ | /--* CNS_INT int 0
[000156] -A---+------ \--* ASG int
[000155] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB01, stmt 6
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 7
[000172] ------------ * STMT void (IL 0x000... ???)
[000171] ------------ \--* JTRUE void
( 1, 4) [000170] ------------ | /--* CNS_INT int 256
( 5, 7) [000168] J------N---- \--* LT int
( 3, 2) [000169] ------------ \--* LCL_VAR int V04 tmp3
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 8
[000060] ------------ * STMT void (IL 0x000... ???)
[000161] ---XG+------ | /--* CAST int <- long
[000053] ---XG+------ | | \--* HWIntrinsic long PopCount
[000052] *--XG+------ | | \--* IND long
[000050] -----+------ | | | /--* CNS_INT long 24
[000051] -----+------ | | \--* ADD long
[000045] -----+------ | | \--* LCL_VAR long V03 tmp2
[000054] ---XG+------ | /--* ADD int
[000163] ---XG+------ | | | /--* CAST int <- long
[000043] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000042] *--XG+------ | | | | \--* IND long
[000040] -----+------ | | | | | /--* CNS_INT long 16
[000041] -----+------ | | | | \--* ADD long
[000035] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000044] ---XG+------ | | \--* ADD int
[000165] ---XG+------ | | | /--* CAST int <- long
[000033] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000032] *--XG+------ | | | | \--* IND long
[000030] -----+------ | | | | | /--* CNS_INT long 8
[000031] -----+------ | | | | \--* ADD long
[000028] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000034] ---XG+------ | | \--* ADD int
[000164] ---XG+------ | | \--* CAST int <- long
[000027] ---XG+------ | | \--* HWIntrinsic long PopCount
[000026] *--XG+------ | | \--* IND long
[000025] -----+------ | | \--* LCL_VAR long V03 tmp2
[000056] ---XG+------ | /--* SUB int
[000024] -----+------ | | \--* LCL_VAR int V04 tmp3
[000059] -A-XG+------ \--* ASG int
[000058] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 9
[000070] ------------ * STMT void (IL 0x000... ???)
[000066] -----+------ | /--* CNS_INT long 32
[000067] -----+------ | /--* ADD long
[000061] -----+------ | | \--* LCL_VAR long V03 tmp2
[000069] -A---+------ \--* ASG long
[000068] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 10
[000022] ------------ * STMT void (IL 0x000... ???)
[000021] -----+------ \--* JTRUE void
( 1, 4) [000019] ------------ | /--* CNS_INT int 256
( 5, 7) [000020] J------N---- \--* GE int
( 3, 2) [000018] ------------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 11
[000075] ------------ * STMT void (IL 0x000... ???)
[000072] -----+------ | /--* LCL_VAR int V04 tmp3
[000074] -A---+------ \--* ASG int
[000073] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB03, stmt 12
[000177] ------------ * STMT void (IL 0x000... ???)
[000176] ------------ \--* JTRUE void
( 1, 1) [000175] ------------ | /--* CNS_INT int 0
( 5, 4) [000173] J------N---- \--* LE int
( 3, 2) [000174] ------------ \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
***** BB04, stmt 13
[000086] ------------ * STMT void (IL 0x000... ???)
[000083] -----+------ | /--* LCL_VAR int V04 tmp3
[000085] -A---+------ \--* ASG int
[000084] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB04, stmt 14
[000096] ------------ * STMT void (IL 0x000... ???)
[000091] ---XG+------ | /--* CAST int <- long
[000090] ---XG+------ | | \--* HWIntrinsic long PopCount
[000089] *--XG+------ | | \--* IND long
[000088] -----+------ | | \--* LCL_VAR long V03 tmp2
[000092] ---XG+------ | /--* SUB int
[000087] -----+------ | | \--* LCL_VAR int V04 tmp3
[000095] -A-XG+------ \--* ASG int
[000094] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB04, stmt 15
[000103] ------------ * STMT void (IL 0x000... ???)
[000099] -----+------ | /--* CNS_INT long 8
[000100] -----+------ | /--* ADD long
[000097] -----+------ | | \--* LCL_VAR long V03 tmp2
[000102] -A---+------ \--* ASG long
[000101] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB04, stmt 16
[000081] ------------ * STMT void (IL 0x000... ???)
[000080] -----+------ \--* JTRUE void
( 1, 1) [000078] ------------ | /--* CNS_INT int 0
( 5, 4) [000079] J------N---- \--* GT int
( 3, 2) [000077] ------------ \--* LCL_VAR int V04 tmp3
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 17
[000111] ------------ * STMT void (IL 0x000... ???)
[000107] -----+------ | /--* CNS_INT long -8
[000108] -----+------ | /--* ADD long
[000105] -----+------ | | \--* LCL_VAR long V03 tmp2
[000110] -A---+------ \--* ASG long
[000109] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB05, stmt 18
[000127] ------------ * STMT void (IL 0x000... ???)
[000124] ---XG+------ | /--* CAST int <- long
[000123] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000121] *--XG+------ | | | /--* IND long
[000120] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000122] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000117] -----+------ | | | /--* CNS_INT int 63
[000118] -----+------ | | | /--* AND int
[000115] -----+------ | | | | | /--* CNS_INT int -1
[000116] -----+------ | | | | \--* ADD int
[000114] -----+------ | | | | \--* LCL_VAR int V05 tmp4
[000119] -----+------ | | \--* LSH long
[000113] -----+------ | | \--* CNS_INT long 1
[000126] -A-XG+------ \--* ASG int
[000125] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB05, stmt 19
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000138] -----+------ | /--* LCL_VAR int V06 tmp5
[000139] -----+------ \--* ADD int
[000135] -----+------ | /--* CNS_INT int 6
[000136] -----+------ \--* LSH int
[000166] -----+------ \--* CAST int <- long
[000132] -----+------ | /--* CNS_INT long 8
[000133] -----+------ \--* DIV long
[000129] -----+------ | /--* LCL_VAR long V02 tmp1
[000130] -----+------ \--* SUB long
[000128] -----+------ \--* LCL_VAR long V03 tmp2
-------------------------------------------------------------------------------------------------------------------
*************** In optUnrollLoops()
*************** In fgDebugCheckBBlist
*************** In lvaMarkLocalVars()
*** marking local variables in block BB01 (weight=1 )
[000142] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000159] -----+------ | | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits]
[000141] -A--G+------ \--* ASG long
[000140] D----+-N---- \--* LCL_VAR long V02 tmp1
New refCnts for V02: refCnt = 1, refCntWtd = 2
[000145] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000144] -A---+------ \--* ASG int
[000143] D----+-N---- \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 1, refCntWtd = 1
[000149] ------------ * STMT void (IL 0x000... ???)
[000146] -----+------ | /--* CNS_INT long 0
[000148] -A---+------ \--* ASG long
[000147] D----+-N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 1, refCntWtd = 1
[000153] ------------ * STMT void (IL 0x000... ???)
[000150] -----+------ | /--* CNS_INT int 0
[000152] -A---+------ \--* ASG int
[000151] D----+-N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 1, refCntWtd = 1
[000157] ------------ * STMT void (IL 0x000... ???)
[000154] -----+------ | /--* CNS_INT int 0
[000156] -A---+------ \--* ASG int
[000155] D----+-N---- \--* LCL_VAR int V06 tmp5
New refCnts for V06: refCnt = 1, refCntWtd = 1
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 2, refCntWtd = 4
[000172] ------------ * STMT void (IL 0x000... ???)
[000171] ------------ \--* JTRUE void
( 1, 4) [000170] ------------ | /--* CNS_INT int 256
( 5, 7) [000168] J------N---- \--* LT int
( 3, 2) [000169] ------------ \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 2, refCntWtd = 4
*** marking local variables in block BB02 (weight=2 )
[000060] ------------ * STMT void (IL 0x000... ???)
[000161] ---XG+------ | /--* CAST int <- long
[000053] ---XG+------ | | \--* HWIntrinsic long PopCount
[000052] *--XG+------ | | \--* IND long
[000050] -----+------ | | | /--* CNS_INT long 24
[000051] -----+------ | | \--* ADD long
[000045] -----+------ | | \--* LCL_VAR long V03 tmp2
[000054] ---XG+------ | /--* ADD int
[000163] ---XG+------ | | | /--* CAST int <- long
[000043] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000042] *--XG+------ | | | | \--* IND long
[000040] -----+------ | | | | | /--* CNS_INT long 16
[000041] -----+------ | | | | \--* ADD long
[000035] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000044] ---XG+------ | | \--* ADD int
[000165] ---XG+------ | | | /--* CAST int <- long
[000033] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000032] *--XG+------ | | | | \--* IND long
[000030] -----+------ | | | | | /--* CNS_INT long 8
[000031] -----+------ | | | | \--* ADD long
[000028] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000034] ---XG+------ | | \--* ADD int
[000164] ---XG+------ | | \--* CAST int <- long
[000027] ---XG+------ | | \--* HWIntrinsic long PopCount
[000026] *--XG+------ | | \--* IND long
[000025] -----+------ | | \--* LCL_VAR long V03 tmp2
[000056] ---XG+------ | /--* SUB int
[000024] -----+------ | | \--* LCL_VAR int V04 tmp3
[000059] -A-XG+------ \--* ASG int
[000058] D----+-N---- \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 3, refCntWtd = 8
New refCnts for V04: refCnt = 4, refCntWtd = 12
New refCnts for V03: refCnt = 3, refCntWtd = 4
New refCnts for V03: refCnt = 4, refCntWtd = 6
New refCnts for V03: refCnt = 5, refCntWtd = 8
New refCnts for V03: refCnt = 6, refCntWtd = 10
[000070] ------------ * STMT void (IL 0x000... ???)
[000066] -----+------ | /--* CNS_INT long 32
[000067] -----+------ | /--* ADD long
[000061] -----+------ | | \--* LCL_VAR long V03 tmp2
[000069] -A---+------ \--* ASG long
[000068] D----+-N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 7, refCntWtd = 12
New refCnts for V03: refCnt = 8, refCntWtd = 14
[000022] ------------ * STMT void (IL 0x000... ???)
[000021] -----+------ \--* JTRUE void
( 1, 4) [000019] ------------ | /--* CNS_INT int 256
( 5, 7) [000020] J------N---- \--* GE int
( 3, 2) [000018] ------------ \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 5, refCntWtd = 16
*** marking local variables in block BB03 (weight=0.50)
[000075] ------------ * STMT void (IL 0x000... ???)
[000072] -----+------ | /--* LCL_VAR int V04 tmp3
[000074] -A---+------ \--* ASG int
[000073] D----+-N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 2, refCntWtd = 1.50
New refCnts for V04: refCnt = 6, refCntWtd = 17
[000177] ------------ * STMT void (IL 0x000... ???)
[000176] ------------ \--* JTRUE void
( 1, 1) [000175] ------------ | /--* CNS_INT int 0
( 5, 4) [000173] J------N---- \--* LE int
( 3, 2) [000174] ------------ \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 7, refCntWtd = 18
*** marking local variables in block BB04 (weight=2 )
[000086] ------------ * STMT void (IL 0x000... ???)
[000083] -----+------ | /--* LCL_VAR int V04 tmp3
[000085] -A---+------ \--* ASG int
[000084] D----+-N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 3, refCntWtd = 3.50
New refCnts for V04: refCnt = 8, refCntWtd = 22
[000096] ------------ * STMT void (IL 0x000... ???)
[000091] ---XG+------ | /--* CAST int <- long
[000090] ---XG+------ | | \--* HWIntrinsic long PopCount
[000089] *--XG+------ | | \--* IND long
[000088] -----+------ | | \--* LCL_VAR long V03 tmp2
[000092] ---XG+------ | /--* SUB int
[000087] -----+------ | | \--* LCL_VAR int V04 tmp3
[000095] -A-XG+------ \--* ASG int
[000094] D----+-N---- \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 9, refCntWtd = 26
New refCnts for V04: refCnt = 10, refCntWtd = 30
New refCnts for V03: refCnt = 9, refCntWtd = 16
[000103] ------------ * STMT void (IL 0x000... ???)
[000099] -----+------ | /--* CNS_INT long 8
[000100] -----+------ | /--* ADD long
[000097] -----+------ | | \--* LCL_VAR long V03 tmp2
[000102] -A---+------ \--* ASG long
[000101] D----+-N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 10, refCntWtd = 18
New refCnts for V03: refCnt = 11, refCntWtd = 20
[000081] ------------ * STMT void (IL 0x000... ???)
[000080] -----+------ \--* JTRUE void
( 1, 1) [000078] ------------ | /--* CNS_INT int 0
( 5, 4) [000079] J------N---- \--* GT int
( 3, 2) [000077] ------------ \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 11, refCntWtd = 34
*** marking local variables in block BB05 (weight=1 )
[000111] ------------ * STMT void (IL 0x000... ???)
[000107] -----+------ | /--* CNS_INT long -8
[000108] -----+------ | /--* ADD long
[000105] -----+------ | | \--* LCL_VAR long V03 tmp2
[000110] -A---+------ \--* ASG long
[000109] D----+-N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 12, refCntWtd = 21
New refCnts for V03: refCnt = 13, refCntWtd = 22
[000127] ------------ * STMT void (IL 0x000... ???)
[000124] ---XG+------ | /--* CAST int <- long
[000123] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000121] *--XG+------ | | | /--* IND long
[000120] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000122] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000117] -----+------ | | | /--* CNS_INT int 63
[000118] -----+------ | | | /--* AND int
[000115] -----+------ | | | | | /--* CNS_INT int -1
[000116] -----+------ | | | | \--* ADD int
[000114] -----+------ | | | | \--* LCL_VAR int V05 tmp4
[000119] -----+------ | | \--* LSH long
[000113] -----+------ | | \--* CNS_INT long 1
[000126] -A-XG+------ \--* ASG int
[000125] D----+-N---- \--* LCL_VAR int V06 tmp5
New refCnts for V06: refCnt = 2, refCntWtd = 2
New refCnts for V05: refCnt = 4, refCntWtd = 4.50
New refCnts for V03: refCnt = 14, refCntWtd = 23
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000138] -----+------ | /--* LCL_VAR int V06 tmp5
[000139] -----+------ \--* ADD int
[000135] -----+------ | /--* CNS_INT int 6
[000136] -----+------ \--* LSH int
[000166] -----+------ \--* CAST int <- long
[000132] -----+------ | /--* CNS_INT long 8
[000133] -----+------ \--* DIV long
[000129] -----+------ | /--* LCL_VAR long V02 tmp1
[000130] -----+------ \--* SUB long
[000128] -----+------ \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 15, refCntWtd = 24
New refCnts for V02: refCnt = 3, refCntWtd = 6
New refCnts for V06: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
*************** In optAddCopies()
refCnt table for 'IntrinsicsUnrolled':
V04 tmp3 [ int]: refCnt = 11, refCntWtd = 34
V03 tmp2 [ long]: refCnt = 15, refCntWtd = 24
V02 tmp1 [ long]: refCnt = 3, refCntWtd = 6
V00 arg0 [ int]: refCnt = 3, refCntWtd = 3
V05 tmp4 [ int]: refCnt = 4, refCntWtd = 4.50
V06 tmp5 [ int]: refCnt = 3, refCntWtd = 3
V01 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
fgMarkLoopHead: Checking loop head block BB02: no guaranteed callsite exits, marking method as fully interruptible
fgMarkLoopHead: Checking loop head block BB04: method is already fully interruptible
The biggest BB has 29 tree nodes
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000142] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long
N001 ( 3, 10) [000159] ------------ | | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits]
N004 ( 5, 12) [000141] -A--G---R--- \--* ASG long
N003 ( 1, 1) [000140] D------N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
( 1, 3) [000145] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0
N003 ( 1, 3) [000144] -A------R--- \--* ASG int
N002 ( 1, 1) [000143] D------N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
( 1, 3) [000149] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000146] ------------ | /--* CNS_INT long 0
N003 ( 1, 3) [000148] -A------R--- \--* ASG long
N002 ( 1, 1) [000147] D------N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
( 1, 3) [000153] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000150] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000152] -A------R--- \--* ASG int
N002 ( 1, 1) [000151] D------N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
( 1, 3) [000157] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000154] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000156] -A------R--- \--* ASG int
N002 ( 1, 1) [000155] D------N---- \--* LCL_VAR int V06 tmp5
***** BB01, stmt 6
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1
N003 ( 1, 3) [000015] -A------R--- \--* ASG long
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 7
( 5, 8) [000172] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000171] ------------ \--* JTRUE void
N002 ( 1, 4) [000170] ------------ | /--* CNS_INT int 256
N003 ( 3, 6) [000168] J------N---- \--* LT int
N001 ( 1, 1) [000169] ------------ \--* LCL_VAR int V04 tmp3
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 8
( 28, 31) [000060] ------------ * STMT void (IL 0x000... ???)
N024 ( 6, 7) [000161] ---XG------- | /--* CAST int <- long
N023 ( 5, 5) [000053] ---XG------- | | \--* HWIntrinsic long PopCount
N022 ( 4, 4) [000052] *--XG------- | | \--* IND long
N020 ( 1, 1) [000050] ------------ | | | /--* CNS_INT long 24
N021 ( 2, 2) [000051] -------N---- | | \--* ADD long
N019 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2
N025 ( 26, 29) [000054] ---XG------- | /--* ADD int
N017 ( 6, 7) [000163] ---XG------- | | | /--* CAST int <- long
N016 ( 5, 5) [000043] ---XG------- | | | | \--* HWIntrinsic long PopCount
N015 ( 4, 4) [000042] *--XG------- | | | | \--* IND long
N013 ( 1, 1) [000040] ------------ | | | | | /--* CNS_INT long 16
N014 ( 2, 2) [000041] -------N---- | | | | \--* ADD long
N012 ( 1, 1) [000035] ------------ | | | | \--* LCL_VAR long V03 tmp2
N018 ( 19, 21) [000044] ---XG------- | | \--* ADD int
N010 ( 6, 7) [000165] ---XG------- | | | /--* CAST int <- long
N009 ( 5, 5) [000033] ---XG------- | | | | \--* HWIntrinsic long PopCount
N008 ( 4, 4) [000032] *--XG------- | | | | \--* IND long
N006 ( 1, 1) [000030] ------------ | | | | | /--* CNS_INT long 8
N007 ( 2, 2) [000031] -------N---- | | | | \--* ADD long
N005 ( 1, 1) [000028] ------------ | | | | \--* LCL_VAR long V03 tmp2
N011 ( 12, 13) [000034] ---XG------- | | \--* ADD int
N004 ( 5, 5) [000164] ---XG------- | | \--* CAST int <- long
N003 ( 4, 3) [000027] ---XG------- | | \--* HWIntrinsic long PopCount
N002 ( 3, 2) [000026] *--XG------- | | \--* IND long
N001 ( 1, 1) [000025] ------------ | | \--* LCL_VAR long V03 tmp2
N027 ( 28, 31) [000056] ---XG---R--- | /--* SUB int
N026 ( 1, 1) [000024] ------------ | | \--* LCL_VAR int V04 tmp3
N029 ( 28, 31) [000059] -A-XG---R--- \--* ASG int
N028 ( 1, 1) [000058] D------N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 9
( 3, 3) [000070] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000066] ------------ | /--* CNS_INT long 32
N003 ( 3, 3) [000067] ------------ | /--* ADD long
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR long V03 tmp2
N005 ( 3, 3) [000069] -A------R--- \--* ASG long
N004 ( 1, 1) [000068] D------N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 10
( 5, 8) [000022] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000021] ------------ \--* JTRUE void
N002 ( 1, 4) [000019] ------------ | /--* CNS_INT int 256
N003 ( 3, 6) [000020] J------N---- \--* GE int
N001 ( 1, 1) [000018] ------------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 11
( 1, 3) [000075] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000072] ------------ | /--* LCL_VAR int V04 tmp3
N003 ( 1, 3) [000074] -A------R--- \--* ASG int
N002 ( 1, 1) [000073] D------N---- \--* LCL_VAR int V05 tmp4
***** BB03, stmt 12
( 5, 5) [000177] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000176] ------------ \--* JTRUE void
N002 ( 1, 1) [000175] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000173] J------N---- \--* LE int
N001 ( 1, 1) [000174] ------------ \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
***** BB04, stmt 13
( 1, 3) [000086] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000083] ------------ | /--* LCL_VAR int V04 tmp3
N003 ( 1, 3) [000085] -A------R--- \--* ASG int
N002 ( 1, 1) [000084] D------N---- \--* LCL_VAR int V05 tmp4
***** BB04, stmt 14
( 7, 7) [000096] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000091] ---XG------- | /--* CAST int <- long
N004 ( 4, 3) [000090] ---XG------- | | \--* HWIntrinsic long PopCount
N003 ( 3, 2) [000089] *--XG------- | | \--* IND long
N002 ( 1, 1) [000088] ------------ | | \--* LCL_VAR long V03 tmp2
N006 ( 7, 7) [000092] ---XG------- | /--* SUB int
N001 ( 1, 1) [000087] ------------ | | \--* LCL_VAR int V04 tmp3
N008 ( 7, 7) [000095] -A-XG---R--- \--* ASG int
N007 ( 1, 1) [000094] D------N---- \--* LCL_VAR int V04 tmp3
***** BB04, stmt 15
( 3, 3) [000103] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000099] ------------ | /--* CNS_INT long 8
N003 ( 3, 3) [000100] ------------ | /--* ADD long
N001 ( 1, 1) [000097] ------------ | | \--* LCL_VAR long V03 tmp2
N005 ( 3, 3) [000102] -A------R--- \--* ASG long
N004 ( 1, 1) [000101] D------N---- \--* LCL_VAR long V03 tmp2
***** BB04, stmt 16
( 5, 5) [000081] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000080] ------------ \--* JTRUE void
N002 ( 1, 1) [000078] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000079] J------N---- \--* GT int
N001 ( 1, 1) [000077] ------------ \--* LCL_VAR int V04 tmp3
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 17
( 3, 3) [000111] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000107] ------------ | /--* CNS_INT long -8
N003 ( 3, 3) [000108] ------------ | /--* ADD long
N001 ( 1, 1) [000105] ------------ | | \--* LCL_VAR long V03 tmp2
N005 ( 3, 3) [000110] -A------R--- \--* ASG long
N004 ( 1, 1) [000109] D------N---- \--* LCL_VAR long V03 tmp2
***** BB05, stmt 18
( 16, 13) [000127] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000124] ---XG------- | /--* CAST int <- long
N011 ( 15, 11) [000123] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
N009 ( 3, 2) [000121] *--XG------- | | | /--* IND long
N008 ( 1, 1) [000120] ------------ | | | | \--* LCL_VAR long V03 tmp2
N010 ( 14, 10) [000122] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
N004 ( 1, 1) [000117] ------------ | | | /--* CNS_INT int 63
N005 ( 5, 5) [000118] ------------ | | | /--* AND int
N002 ( 1, 1) [000115] ------------ | | | | | /--* CNS_INT int -1
N003 ( 3, 3) [000116] ------------ | | | | \--* ADD int
N001 ( 1, 1) [000114] ------------ | | | | \--* LCL_VAR int V05 tmp4
N007 ( 10, 7) [000119] --------R--- | | \--* LSH long
N006 ( 1, 1) [000113] ------------ | | \--* CNS_INT long 1
N014 ( 16, 13) [000126] -A-XG---R--- \--* ASG int
N013 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V06 tmp5
***** BB05, stmt 19
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int
N009 ( 1, 1) [000138] ------------ | /--* LCL_VAR int V06 tmp5
N010 ( 29, 13) [000139] ------------ \--* ADD int
N007 ( 1, 1) [000135] ------------ | /--* CNS_INT int 6
N008 ( 27, 11) [000136] ------------ \--* LSH int
N006 ( 25, 9) [000166] ------------ \--* CAST int <- long
N004 ( 1, 1) [000132] ------------ | /--* CNS_INT long 8
N005 ( 24, 7) [000133] ------------ \--* DIV long
N002 ( 1, 1) [000129] ------------ | /--* LCL_VAR long V02 tmp1
N003 ( 3, 3) [000130] ------------ \--* SUB long
N001 ( 1, 1) [000128] ------------ \--* LCL_VAR long V03 tmp2
-------------------------------------------------------------------------------------------------------------------
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 6.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
*************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...)
*************** In SsaBuilder::InsertPhiFunctions()
*************** In fgLocalVarLiveness()
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={ V00 } + ByrefExposed + GcHeap
DEF(5)={V04 V03 V02 V05 V06}
BB02 USE(2)={V04 V03} + ByrefExposed + GcHeap
DEF(2)={V04 V03}
BB03 USE(1)={V04 }
DEF(1)={ V05}
BB04 USE(2)={V04 V03 } + ByrefExposed + GcHeap
DEF(3)={V04 V03 V05}
BB05 USE(3)={V03 V02 V05 } + ByrefExposed + GcHeap
DEF(2)={V03 V06}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={ V00} + ByrefExposed + GcHeap
OUT(3)={V04 V03 V02 } + ByrefExposed + GcHeap
BB02 IN (3)={V04 V03 V02} + ByrefExposed + GcHeap
OUT(3)={V04 V03 V02} + ByrefExposed + GcHeap
BB03 IN (3)={V04 V03 V02 } + ByrefExposed + GcHeap
OUT(4)={V04 V03 V02 V05} + ByrefExposed + GcHeap
BB04 IN (3)={V04 V03 V02 } + ByrefExposed + GcHeap
OUT(4)={V04 V03 V02 V05} + ByrefExposed + GcHeap
BB05 IN (3)={V03 V02 V05} + ByrefExposed + GcHeap
OUT(0)={ }
top level assign
removing stmt with no side effects
Removing statement [000157] in BB01 as useless:
( 1, 3) [000157] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000154] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000156] -A------R--- \--* ASG int
N002 ( 1, 1) [000155] D------N---- \--* LCL_VAR int V06 tmp5
New refCnts for V06: refCnt = 2, refCntWtd = 2
top level assign
removing stmt with no side effects
Removing statement [000153] in BB01 as useless:
( 1, 3) [000153] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000150] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000152] -A------R--- \--* ASG int
N002 ( 1, 1) [000151] D------N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 3, refCntWtd = 3.50
top level assign
removing stmt with no side effects
Removing statement [000149] in BB01 as useless:
( 1, 3) [000149] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000146] ------------ | /--* CNS_INT long 0
N003 ( 1, 3) [000148] -A------R--- \--* ASG long
N002 ( 1, 1) [000147] D------N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 14, refCntWtd = 23
In fgLocalVarLiveness, setting lvaSortAgain back to false (set during dead-code removal)
Inserting phi functions:
Inserting phi definition for V04 at start of BB04.
Inserting phi definition for V03 at start of BB05.
Inserting phi definition for V03 at start of BB04.
Inserting phi definition for V05 at start of BB05.
Inserting phi definition for V04 at start of BB03.
Inserting phi definition for V04 at start of BB02.
Inserting phi definition for V03 at start of BB03.
Inserting phi definition for V03 at start of BB02.
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000142] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long
N001 ( 3, 10) [000159] ------------ | | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits]
N004 ( 5, 12) [000141] -A--G---R--- \--* ASG long
N003 ( 1, 1) [000140] D------N---- \--* LCL_VAR long V02 tmp1 d:2
***** BB01, stmt 2
( 1, 3) [000145] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use)
N003 ( 1, 3) [000144] -A------R--- \--* ASG int
N002 ( 1, 1) [000143] D------N---- \--* LCL_VAR int V04 tmp3 d:2
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2
N003 ( 1, 3) [000015] -A------R--- \--* ASG long
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2
***** BB01, stmt 4
( 5, 8) [000172] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000171] ------------ \--* JTRUE void
N002 ( 1, 4) [000170] ------------ | /--* CNS_INT int 256
N003 ( 3, 6) [000168] J------N---- \--* LT int
N001 ( 1, 1) [000169] ------------ \--* LCL_VAR int V04 tmp3 u:2
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 5
( 2, 3) [000209] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000207] ------------ | * PHI long
N001 ( 0, 0) [000222] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ | \--* PHI_ARG long V03 tmp2 u:2
N007 ( 2, 3) [000208] -A------R--- \--* ASG long
N006 ( 1, 1) [000206] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 6
( 2, 3) [000201] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000199] ------------ | * PHI int
N001 ( 0, 0) [000224] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ | \--* PHI_ARG int V04 tmp3 u:2
N007 ( 2, 3) [000200] -A------R--- \--* ASG int
N006 ( 1, 1) [000198] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 7
( 28, 31) [000060] ------------ * STMT void (IL 0x000... ???)
N024 ( 6, 7) [000161] ---XG------- | /--* CAST int <- long
N023 ( 5, 5) [000053] ---XG------- | | \--* HWIntrinsic long PopCount
N022 ( 4, 4) [000052] *--XG------- | | \--* IND long
N020 ( 1, 1) [000050] ------------ | | | /--* CNS_INT long 24
N021 ( 2, 2) [000051] -------N---- | | \--* ADD long
N019 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2 u:3
N025 ( 26, 29) [000054] ---XG------- | /--* ADD int
N017 ( 6, 7) [000163] ---XG------- | | | /--* CAST int <- long
N016 ( 5, 5) [000043] ---XG------- | | | | \--* HWIntrinsic long PopCount
N015 ( 4, 4) [000042] *--XG------- | | | | \--* IND long
N013 ( 1, 1) [000040] ------------ | | | | | /--* CNS_INT long 16
N014 ( 2, 2) [000041] -------N---- | | | | \--* ADD long
N012 ( 1, 1) [000035] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:3
N018 ( 19, 21) [000044] ---XG------- | | \--* ADD int
N010 ( 6, 7) [000165] ---XG------- | | | /--* CAST int <- long
N009 ( 5, 5) [000033] ---XG------- | | | | \--* HWIntrinsic long PopCount
N008 ( 4, 4) [000032] *--XG------- | | | | \--* IND long
N006 ( 1, 1) [000030] ------------ | | | | | /--* CNS_INT long 8
N007 ( 2, 2) [000031] -------N---- | | | | \--* ADD long
N005 ( 1, 1) [000028] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:3
N011 ( 12, 13) [000034] ---XG------- | | \--* ADD int
N004 ( 5, 5) [000164] ---XG------- | | \--* CAST int <- long
N003 ( 4, 3) [000027] ---XG------- | | \--* HWIntrinsic long PopCount
N002 ( 3, 2) [000026] *--XG------- | | \--* IND long
N001 ( 1, 1) [000025] ------------ | | \--* LCL_VAR long V03 tmp2 u:3
N027 ( 28, 31) [000056] ---XG---R--- | /--* SUB int
N026 ( 1, 1) [000024] ------------ | | \--* LCL_VAR int V04 tmp3 u:3 (last use)
N029 ( 28, 31) [000059] -A-XG---R--- \--* ASG int
N028 ( 1, 1) [000058] D------N---- \--* LCL_VAR int V04 tmp3 d:4
***** BB02, stmt 8
( 3, 3) [000070] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000066] ------------ | /--* CNS_INT long 32
N003 ( 3, 3) [000067] ------------ | /--* ADD long
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use)
N005 ( 3, 3) [000069] -A------R--- \--* ASG long
N004 ( 1, 1) [000068] D------N---- \--* LCL_VAR long V03 tmp2 d:4
***** BB02, stmt 9
( 5, 8) [000022] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000021] ------------ \--* JTRUE void
N002 ( 1, 4) [000019] ------------ | /--* CNS_INT int 256
N003 ( 3, 6) [000020] J------N---- \--* GE int
N001 ( 1, 1) [000018] ------------ \--* LCL_VAR int V04 tmp3 u:4
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 10
( 2, 3) [000205] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000203] ------------ | * PHI long
N001 ( 0, 0) [000218] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ | \--* PHI_ARG long V03 tmp2 u:2
N007 ( 2, 3) [000204] -A------R--- \--* ASG long
N006 ( 1, 1) [000202] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 11
( 2, 3) [000197] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000195] ------------ | * PHI int
N001 ( 0, 0) [000220] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ | \--* PHI_ARG int V04 tmp3 u:2
N007 ( 2, 3) [000196] -A------R--- \--* ASG int
N006 ( 1, 1) [000194] D------N---- \--* LCL_VAR int V04 tmp3 d:5
***** BB03, stmt 12
( 1, 3) [000075] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000072] ------------ | /--* LCL_VAR int V04 tmp3 u:5
N003 ( 1, 3) [000074] -A------R--- \--* ASG int
N002 ( 1, 1) [000073] D------N---- \--* LCL_VAR int V05 tmp4 d:2
***** BB03, stmt 13
( 5, 5) [000177] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000176] ------------ \--* JTRUE void
N002 ( 1, 1) [000175] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000173] J------N---- \--* LE int
N001 ( 1, 1) [000174] ------------ \--* LCL_VAR int V04 tmp3 u:5
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
***** BB04, stmt 14
( 2, 3) [000189] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000187] ------------ | * PHI long
N001 ( 0, 0) [000238] ------------ | /--* PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ | \--* PHI_ARG long V03 tmp2 u:5
N007 ( 2, 3) [000188] -A------R--- \--* ASG long
N006 ( 1, 1) [000186] D------N---- \--* LCL_VAR long V03 tmp2 d:6
***** BB04, stmt 15
( 2, 3) [000181] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000179] ------------ | * PHI int
N001 ( 0, 0) [000240] ------------ | /--* PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ | \--* PHI_ARG int V04 tmp3 u:5
N007 ( 2, 3) [000180] -A------R--- \--* ASG int
N006 ( 1, 1) [000178] D------N---- \--* LCL_VAR int V04 tmp3 d:6
***** BB04, stmt 16
( 1, 3) [000086] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000083] ------------ | /--* LCL_VAR int V04 tmp3 u:6
N003 ( 1, 3) [000085] -A------R--- \--* ASG int
N002 ( 1, 1) [000084] D------N---- \--* LCL_VAR int V05 tmp4 d:3
***** BB04, stmt 17
( 7, 7) [000096] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000091] ---XG------- | /--* CAST int <- long
N004 ( 4, 3) [000090] ---XG------- | | \--* HWIntrinsic long PopCount
N003 ( 3, 2) [000089] *--XG------- | | \--* IND long
N002 ( 1, 1) [000088] ------------ | | \--* LCL_VAR long V03 tmp2 u:6
N006 ( 7, 7) [000092] ---XG------- | /--* SUB int
N001 ( 1, 1) [000087] ------------ | | \--* LCL_VAR int V04 tmp3 u:6 (last use)
N008 ( 7, 7) [000095] -A-XG---R--- \--* ASG int
N007 ( 1, 1) [000094] D------N---- \--* LCL_VAR int V04 tmp3 d:7
***** BB04, stmt 18
( 3, 3) [000103] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000099] ------------ | /--* CNS_INT long 8
N003 ( 3, 3) [000100] ------------ | /--* ADD long
N001 ( 1, 1) [000097] ------------ | | \--* LCL_VAR long V03 tmp2 u:6 (last use)
N005 ( 3, 3) [000102] -A------R--- \--* ASG long
N004 ( 1, 1) [000101] D------N---- \--* LCL_VAR long V03 tmp2 d:7
***** BB04, stmt 19
( 5, 5) [000081] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000080] ------------ \--* JTRUE void
N002 ( 1, 1) [000078] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000079] J------N---- \--* GT int
N001 ( 1, 1) [000077] ------------ \--* LCL_VAR int V04 tmp3 u:7
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 20
( 2, 3) [000193] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000191] ------------ | * PHI int
N001 ( 0, 0) [000234] ------------ | /--* PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ | \--* PHI_ARG int V05 tmp4 u:2
N007 ( 2, 3) [000192] -A------R--- \--* ASG int
N006 ( 1, 1) [000190] D------N---- \--* LCL_VAR int V05 tmp4 d:4
***** BB05, stmt 21
( 2, 3) [000185] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000183] ------------ | * PHI long
N001 ( 0, 0) [000236] ------------ | /--* PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ | \--* PHI_ARG long V03 tmp2 u:5
N007 ( 2, 3) [000184] -A------R--- \--* ASG long
N006 ( 1, 1) [000182] D------N---- \--* LCL_VAR long V03 tmp2 d:8
***** BB05, stmt 22
( 3, 3) [000111] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000107] ------------ | /--* CNS_INT long -8
N003 ( 3, 3) [000108] ------------ | /--* ADD long
N001 ( 1, 1) [000105] ------------ | | \--* LCL_VAR long V03 tmp2 u:8 (last use)
N005 ( 3, 3) [000110] -A------R--- \--* ASG long
N004 ( 1, 1) [000109] D------N---- \--* LCL_VAR long V03 tmp2 d:9
***** BB05, stmt 23
( 16, 13) [000127] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000124] ---XG------- | /--* CAST int <- long
N011 ( 15, 11) [000123] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
N009 ( 3, 2) [000121] *--XG------- | | | /--* IND long
N008 ( 1, 1) [000120] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:9
N010 ( 14, 10) [000122] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
N004 ( 1, 1) [000117] ------------ | | | /--* CNS_INT int 63
N005 ( 5, 5) [000118] ------------ | | | /--* AND int
N002 ( 1, 1) [000115] ------------ | | | | | /--* CNS_INT int -1
N003 ( 3, 3) [000116] ------------ | | | | \--* ADD int
N001 ( 1, 1) [000114] ------------ | | | | \--* LCL_VAR int V05 tmp4 u:4 (last use)
N007 ( 10, 7) [000119] --------R--- | | \--* LSH long
N006 ( 1, 1) [000113] ------------ | | \--* CNS_INT long 1
N014 ( 16, 13) [000126] -A-XG---R--- \--* ASG int
N013 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V06 tmp5 d:2
***** BB05, stmt 24
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int
N009 ( 1, 1) [000138] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use)
N010 ( 29, 13) [000139] ------------ \--* ADD int
N007 ( 1, 1) [000135] ------------ | /--* CNS_INT int 6
N008 ( 27, 11) [000136] ------------ \--* LSH int
N006 ( 25, 9) [000166] ------------ \--* CAST int <- long
N004 ( 1, 1) [000132] ------------ | /--* CNS_INT long 8
N005 ( 24, 7) [000133] ------------ \--* DIV long
N002 ( 1, 1) [000129] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use)
N003 ( 3, 3) [000130] ------------ \--* SUB long
N001 ( 1, 1) [000128] ------------ \--* LCL_VAR long V03 tmp2 u:9 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In optEarlyProp()
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $c0
The SSA definition for ByrefExposed (#2) at start of BB01 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB01 is $c0 {InitVal($41)}
***** BB01, stmt 1 (before)
N002 ( 5, 12) [000001] x---G------- /--* IND long
N001 ( 3, 10) [000159] ------------ | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits]
N004 ( 5, 12) [000141] -A--G---R--- * ASG long
N003 ( 1, 1) [000140] D------N---- \--* LCL_VAR long V02 tmp1 d:2
N001 [000159] CNS_INT(h) 0x7f08ab884498 static Fseq[_bits] => $100 {Hnd const: 0x00007F08AB884498}
N002 [000001] IND => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N003 [000140] LCL_VAR V02 tmp1 d:2 => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N004 [000141] ASG => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
***** BB01, stmt 1 (after)
N002 ( 5, 12) [000001] x---G------- /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000159] ------------ | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
N004 ( 5, 12) [000141] -A--G---R--- * ASG long <l:$140, c:$180>
N003 ( 1, 1) [000140] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
---------
***** BB01, stmt 2 (before)
N001 ( 1, 1) [000003] ------------ /--* LCL_VAR int V00 arg0 u:2 (last use)
N003 ( 1, 3) [000144] -A------R--- * ASG int
N002 ( 1, 1) [000143] D------N---- \--* LCL_VAR int V04 tmp3 d:2
N001 [000003] LCL_VAR V00 arg0 u:2 (last use) => $80 {InitVal($40)}
N002 [000143] LCL_VAR V04 tmp3 d:2 => $80 {InitVal($40)}
N003 [000144] ASG => $80 {InitVal($40)}
***** BB01, stmt 2 (after)
N001 ( 1, 1) [000003] ------------ /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000144] -A------R--- * ASG int $80
N002 ( 1, 1) [000143] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
---------
***** BB01, stmt 3 (before)
N001 ( 1, 1) [000013] ------------ /--* LCL_VAR long V02 tmp1 u:2
N003 ( 1, 3) [000015] -A------R--- * ASG long
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2
N001 [000013] LCL_VAR V02 tmp1 u:2 => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N002 [000014] LCL_VAR V03 tmp2 d:2 => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N003 [000015] ASG => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
***** BB01, stmt 3 (after)
N001 ( 1, 1) [000013] ------------ /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- * ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
---------
***** BB01, stmt 4 (before)
N004 ( 5, 8) [000171] ------------ * JTRUE void
N002 ( 1, 4) [000170] ------------ | /--* CNS_INT int 256
N003 ( 3, 6) [000168] J------N---- \--* LT int
N001 ( 1, 1) [000169] ------------ \--* LCL_VAR int V04 tmp3 u:2
N001 [000169] LCL_VAR V04 tmp3 u:2 => $80 {InitVal($40)}
N002 [000170] CNS_INT 256 => $43 {IntCns 256}
N003 [000168] LT => $200 {LT($80, $43)}
***** BB01, stmt 4 (after)
N004 ( 5, 8) [000171] ------------ * JTRUE void
N002 ( 1, 4) [000170] ------------ | /--* CNS_INT int 256 $43
N003 ( 3, 6) [000168] J------N---- \--* LT int $200
N001 ( 1, 1) [000169] ------------ \--* LCL_VAR int V04 tmp3 u:2 $80
finish(BB01).
Succ(BB02).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
Succ(BB03).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
SSA definition: set VN of local 3/3 to $141 {PhiDef($3, $3, $240)}.
SSA definition: set VN of local 4/3 to $280 {PhiDef($4, $3, $240)}.
The SSA definition for ByrefExposed (#2) at start of BB02 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB02 is $c0 {InitVal($41)}
***** BB02, stmt 5 (before)
N024 ( 6, 7) [000161] ---XG------- /--* CAST int <- long
N023 ( 5, 5) [000053] ---XG------- | \--* HWIntrinsic long PopCount
N022 ( 4, 4) [000052] *--XG------- | \--* IND long
N020 ( 1, 1) [000050] ------------ | | /--* CNS_INT long 24
N021 ( 2, 2) [000051] -------N---- | \--* ADD long
N019 ( 1, 1) [000045] ------------ | \--* LCL_VAR long V03 tmp2 u:3
N025 ( 26, 29) [000054] ---XG------- /--* ADD int
N017 ( 6, 7) [000163] ---XG------- | | /--* CAST int <- long
N016 ( 5, 5) [000043] ---XG------- | | | \--* HWIntrinsic long PopCount
N015 ( 4, 4) [000042] *--XG------- | | | \--* IND long
N013 ( 1, 1) [000040] ------------ | | | | /--* CNS_INT long 16
N014 ( 2, 2) [000041] -------N---- | | | \--* ADD long
N012 ( 1, 1) [000035] ------------ | | | \--* LCL_VAR long V03 tmp2 u:3
N018 ( 19, 21) [000044] ---XG------- | \--* ADD int
N010 ( 6, 7) [000165] ---XG------- | | /--* CAST int <- long
N009 ( 5, 5) [000033] ---XG------- | | | \--* HWIntrinsic long PopCount
N008 ( 4, 4) [000032] *--XG------- | | | \--* IND long
N006 ( 1, 1) [000030] ------------ | | | | /--* CNS_INT long 8
N007 ( 2, 2) [000031] -------N---- | | | \--* ADD long
N005 ( 1, 1) [000028] ------------ | | | \--* LCL_VAR long V03 tmp2 u:3
N011 ( 12, 13) [000034] ---XG------- | \--* ADD int
N004 ( 5, 5) [000164] ---XG------- | \--* CAST int <- long
N003 ( 4, 3) [000027] ---XG------- | \--* HWIntrinsic long PopCount
N002 ( 3, 2) [000026] *--XG------- | \--* IND long
N001 ( 1, 1) [000025] ------------ | \--* LCL_VAR long V03 tmp2 u:3
N027 ( 28, 31) [000056] ---XG---R--- /--* SUB int
N026 ( 1, 1) [000024] ------------ | \--* LCL_VAR int V04 tmp3 u:3 (last use)
N029 ( 28, 31) [000059] -A-XG---R--- * ASG int
N028 ( 1, 1) [000058] D------N---- \--* LCL_VAR int V04 tmp3 d:4
N001 [000025] LCL_VAR V03 tmp2 u:3 => $141 {PhiDef($3, $3, $240)}
N002 [000026] IND => <l:$142 {ByrefExposedLoad($42, $141, $c0)}, c:$2c0 {2c0}>
VNForCastOper(int) is $46
N004 [000164] CAST => $201 {Cast($300, $46)}
N005 [000028] LCL_VAR V03 tmp2 u:3 => $141 {PhiDef($3, $3, $240)}
N006 [000030] CNS_INT 8 => $340 {LngCns: 8}
N007 [000031] ADD => $241 {ADD($141, $340)}
N008 [000032] IND => <l:$143 {ByrefExposedLoad($42, $241, $c0)}, c:$2c1 {2c1}>
VNForCastOper(int) is $46
N010 [000165] CAST => $202 {Cast($301, $46)}
N011 [000034] ADD => $203 {ADD($201, $202)}
N012 [000035] LCL_VAR V03 tmp2 u:3 => $141 {PhiDef($3, $3, $240)}
N013 [000040] CNS_INT 16 => $342 {LngCns: 16}
N014 [000041] ADD => $242 {ADD($141, $342)}
N015 [000042] IND => <l:$144 {ByrefExposedLoad($42, $242, $c0)}, c:$2c2 {2c2}>
VNForCastOper(int) is $46
N017 [000163] CAST => $204 {Cast($302, $46)}
N018 [000044] ADD => $205 {ADD($203, $204)}
N019 [000045] LCL_VAR V03 tmp2 u:3 => $141 {PhiDef($3, $3, $240)}
N020 [000050] CNS_INT 24 => $343 {LngCns: 24}
N021 [000051] ADD => $243 {ADD($141, $343)}
N022 [000052] IND => <l:$145 {ByrefExposedLoad($42, $243, $c0)}, c:$2c3 {2c3}>
VNForCastOper(int) is $46
N024 [000161] CAST => $206 {Cast($303, $46)}
N025 [000054] ADD => $207 {ADD($205, $206)}
N026 [000024] LCL_VAR V04 tmp3 u:3 (last use) => $280 {PhiDef($4, $3, $240)}
N027 [000056] SUB => $208 {SUB($280, $207)}
N028 [000058] LCL_VAR V04 tmp3 d:4 => $208 {SUB($280, $207)}
N029 [000059] ASG => $208 {SUB($280, $207)}
***** BB02, stmt 5 (after)
N024 ( 6, 7) [000161] ---XG------- /--* CAST int <- long $206
N023 ( 5, 5) [000053] ---XG------- | \--* HWIntrinsic long PopCount $303
N022 ( 4, 4) [000052] *--XG------- | \--* IND long <l:$145, c:$2c3>
N020 ( 1, 1) [000050] ------------ | | /--* CNS_INT long 24 $343
N021 ( 2, 2) [000051] -------N---- | \--* ADD long $243
N019 ( 1, 1) [000045] ------------ | \--* LCL_VAR long V03 tmp2 u:3 $141
N025 ( 26, 29) [000054] ---XG------- /--* ADD int $207
N017 ( 6, 7) [000163] ---XG------- | | /--* CAST int <- long $204
N016 ( 5, 5) [000043] ---XG------- | | | \--* HWIntrinsic long PopCount $302
N015 ( 4, 4) [000042] *--XG------- | | | \--* IND long <l:$144, c:$2c2>
N013 ( 1, 1) [000040] ------------ | | | | /--* CNS_INT long 16 $342
N014 ( 2, 2) [000041] -------N---- | | | \--* ADD long $242
N012 ( 1, 1) [000035] ------------ | | | \--* LCL_VAR long V03 tmp2 u:3 $141
N018 ( 19, 21) [000044] ---XG------- | \--* ADD int $205
N010 ( 6, 7) [000165] ---XG------- | | /--* CAST int <- long $202
N009 ( 5, 5) [000033] ---XG------- | | | \--* HWIntrinsic long PopCount $301
N008 ( 4, 4) [000032] *--XG------- | | | \--* IND long <l:$143, c:$2c1>
N006 ( 1, 1) [000030] ------------ | | | | /--* CNS_INT long 8 $340
N007 ( 2, 2) [000031] -------N---- | | | \--* ADD long $241
N005 ( 1, 1) [000028] ------------ | | | \--* LCL_VAR long V03 tmp2 u:3 $141
N011 ( 12, 13) [000034] ---XG------- | \--* ADD int $203
N004 ( 5, 5) [000164] ---XG------- | \--* CAST int <- long $201
N003 ( 4, 3) [000027] ---XG------- | \--* HWIntrinsic long PopCount $300
N002 ( 3, 2) [000026] *--XG------- | \--* IND long <l:$142, c:$2c0>
N001 ( 1, 1) [000025] ------------ | \--* LCL_VAR long V03 tmp2 u:3 $141
N027 ( 28, 31) [000056] ---XG---R--- /--* SUB int $208
N026 ( 1, 1) [000024] ------------ | \--* LCL_VAR int V04 tmp3 u:3 (last use) $280
N029 ( 28, 31) [000059] -A-XG---R--- * ASG int $208
N028 ( 1, 1) [000058] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $208
---------
***** BB02, stmt 6 (before)
N002 ( 1, 1) [000066] ------------ /--* CNS_INT long 32
N003 ( 3, 3) [000067] ------------ /--* ADD long
N001 ( 1, 1) [000061] ------------ | \--* LCL_VAR long V03 tmp2 u:3 (last use)
N005 ( 3, 3) [000069] -A------R--- * ASG long
N004 ( 1, 1) [000068] D------N---- \--* LCL_VAR long V03 tmp2 d:4
N001 [000061] LCL_VAR V03 tmp2 u:3 (last use) => $141 {PhiDef($3, $3, $240)}
N002 [000066] CNS_INT 32 => $344 {LngCns: 32}
N003 [000067] ADD => $244 {ADD($141, $344)}
N004 [000068] LCL_VAR V03 tmp2 d:4 => $244 {ADD($141, $344)}
N005 [000069] ASG => $244 {ADD($141, $344)}
***** BB02, stmt 6 (after)
N002 ( 1, 1) [000066] ------------ /--* CNS_INT long 32 $344
N003 ( 3, 3) [000067] ------------ /--* ADD long $244
N001 ( 1, 1) [000061] ------------ | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000069] -A------R--- * ASG long $244
N004 ( 1, 1) [000068] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $244
---------
***** BB02, stmt 7 (before)
N004 ( 5, 8) [000021] ------------ * JTRUE void
N002 ( 1, 4) [000019] ------------ | /--* CNS_INT int 256
N003 ( 3, 6) [000020] J------N---- \--* GE int
N001 ( 1, 1) [000018] ------------ \--* LCL_VAR int V04 tmp3 u:4
N001 [000018] LCL_VAR V04 tmp3 u:4 => $208 {SUB($280, $207)}
N002 [000019] CNS_INT 256 => $43 {IntCns 256}
N003 [000020] GE => $209 {GE($208, $43)}
***** BB02, stmt 7 (after)
N004 ( 5, 8) [000021] ------------ * JTRUE void
N002 ( 1, 4) [000019] ------------ | /--* CNS_INT int 256 $43
N003 ( 3, 6) [000020] J------N---- \--* GE int $209
N001 ( 1, 1) [000018] ------------ \--* LCL_VAR int V04 tmp3 u:4 $208
finish(BB02).
Succ(BB03).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB02).
SSA definition: set VN of local 3/5 to $146 {PhiDef($3, $5, $240)}.
SSA definition: set VN of local 4/5 to $281 {PhiDef($4, $5, $240)}.
The SSA definition for ByrefExposed (#2) at start of BB03 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB03 is $c0 {InitVal($41)}
***** BB03, stmt 10 (before)
N001 ( 1, 1) [000072] ------------ /--* LCL_VAR int V04 tmp3 u:5
N003 ( 1, 3) [000074] -A------R--- * ASG int
N002 ( 1, 1) [000073] D------N---- \--* LCL_VAR int V05 tmp4 d:2
N001 [000072] LCL_VAR V04 tmp3 u:5 => $281 {PhiDef($4, $5, $240)}
N002 [000073] LCL_VAR V05 tmp4 d:2 => $281 {PhiDef($4, $5, $240)}
N003 [000074] ASG => $281 {PhiDef($4, $5, $240)}
***** BB03, stmt 10 (after)
N001 ( 1, 1) [000072] ------------ /--* LCL_VAR int V04 tmp3 u:5 $281
N003 ( 1, 3) [000074] -A------R--- * ASG int $281
N002 ( 1, 1) [000073] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $281
---------
***** BB03, stmt 11 (before)
N004 ( 5, 5) [000176] ------------ * JTRUE void
N002 ( 1, 1) [000175] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000173] J------N---- \--* LE int
N001 ( 1, 1) [000174] ------------ \--* LCL_VAR int V04 tmp3 u:5
N001 [000174] LCL_VAR V04 tmp3 u:5 => $281 {PhiDef($4, $5, $240)}
N002 [000175] CNS_INT 0 => $40 {IntCns 0}
N003 [000173] LE => $20a {LE($281, $40)}
***** BB03, stmt 11 (after)
N004 ( 5, 5) [000176] ------------ * JTRUE void
N002 ( 1, 1) [000175] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000173] J------N---- \--* LE int $20a
N001 ( 1, 1) [000174] ------------ \--* LCL_VAR int V04 tmp3 u:5 $281
finish(BB03).
Succ(BB04).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
Succ(BB05).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
SSA definition: set VN of local 3/6 to $147 {PhiDef($3, $6, $245)}.
SSA definition: set VN of local 4/6 to $282 {PhiDef($4, $6, $245)}.
The SSA definition for ByrefExposed (#2) at start of BB04 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB04 is $c0 {InitVal($41)}
***** BB04, stmt 14 (before)
N001 ( 1, 1) [000083] ------------ /--* LCL_VAR int V04 tmp3 u:6
N003 ( 1, 3) [000085] -A------R--- * ASG int
N002 ( 1, 1) [000084] D------N---- \--* LCL_VAR int V05 tmp4 d:3
N001 [000083] LCL_VAR V04 tmp3 u:6 => $282 {PhiDef($4, $6, $245)}
N002 [000084] LCL_VAR V05 tmp4 d:3 => $282 {PhiDef($4, $6, $245)}
N003 [000085] ASG => $282 {PhiDef($4, $6, $245)}
***** BB04, stmt 14 (after)
N001 ( 1, 1) [000083] ------------ /--* LCL_VAR int V04 tmp3 u:6 $282
N003 ( 1, 3) [000085] -A------R--- * ASG int $282
N002 ( 1, 1) [000084] D------N---- \--* LCL_VAR int V05 tmp4 d:3 $282
---------
***** BB04, stmt 15 (before)
N005 ( 5, 5) [000091] ---XG------- /--* CAST int <- long
N004 ( 4, 3) [000090] ---XG------- | \--* HWIntrinsic long PopCount
N003 ( 3, 2) [000089] *--XG------- | \--* IND long
N002 ( 1, 1) [000088] ------------ | \--* LCL_VAR long V03 tmp2 u:6
N006 ( 7, 7) [000092] ---XG------- /--* SUB int
N001 ( 1, 1) [000087] ------------ | \--* LCL_VAR int V04 tmp3 u:6 (last use)
N008 ( 7, 7) [000095] -A-XG---R--- * ASG int
N007 ( 1, 1) [000094] D------N---- \--* LCL_VAR int V04 tmp3 d:7
N001 [000087] LCL_VAR V04 tmp3 u:6 (last use) => $282 {PhiDef($4, $6, $245)}
N002 [000088] LCL_VAR V03 tmp2 u:6 => $147 {PhiDef($3, $6, $245)}
N003 [000089] IND => <l:$148 {ByrefExposedLoad($42, $147, $c0)}, c:$400 {400}>
VNForCastOper(int) is $46
N005 [000091] CAST => $20b {Cast($440, $46)}
N006 [000092] SUB => $20c {SUB($282, $20b)}
N007 [000094] LCL_VAR V04 tmp3 d:7 => $20c {SUB($282, $20b)}
N008 [000095] ASG => $20c {SUB($282, $20b)}
***** BB04, stmt 15 (after)
N005 ( 5, 5) [000091] ---XG------- /--* CAST int <- long $20b
N004 ( 4, 3) [000090] ---XG------- | \--* HWIntrinsic long PopCount $440
N003 ( 3, 2) [000089] *--XG------- | \--* IND long <l:$148, c:$400>
N002 ( 1, 1) [000088] ------------ | \--* LCL_VAR long V03 tmp2 u:6 $147
N006 ( 7, 7) [000092] ---XG------- /--* SUB int $20c
N001 ( 1, 1) [000087] ------------ | \--* LCL_VAR int V04 tmp3 u:6 (last use) $282
N008 ( 7, 7) [000095] -A-XG---R--- * ASG int $20c
N007 ( 1, 1) [000094] D------N---- \--* LCL_VAR int V04 tmp3 d:7 $20c
---------
***** BB04, stmt 16 (before)
N002 ( 1, 1) [000099] ------------ /--* CNS_INT long 8
N003 ( 3, 3) [000100] ------------ /--* ADD long
N001 ( 1, 1) [000097] ------------ | \--* LCL_VAR long V03 tmp2 u:6 (last use)
N005 ( 3, 3) [000102] -A------R--- * ASG long
N004 ( 1, 1) [000101] D------N---- \--* LCL_VAR long V03 tmp2 d:7
N001 [000097] LCL_VAR V03 tmp2 u:6 (last use) => $147 {PhiDef($3, $6, $245)}
N002 [000099] CNS_INT 8 => $340 {LngCns: 8}
N003 [000100] ADD => $246 {ADD($147, $340)}
N004 [000101] LCL_VAR V03 tmp2 d:7 => $246 {ADD($147, $340)}
N005 [000102] ASG => $246 {ADD($147, $340)}
***** BB04, stmt 16 (after)
N002 ( 1, 1) [000099] ------------ /--* CNS_INT long 8 $340
N003 ( 3, 3) [000100] ------------ /--* ADD long $246
N001 ( 1, 1) [000097] ------------ | \--* LCL_VAR long V03 tmp2 u:6 (last use) $147
N005 ( 3, 3) [000102] -A------R--- * ASG long $246
N004 ( 1, 1) [000101] D------N---- \--* LCL_VAR long V03 tmp2 d:7 $246
---------
***** BB04, stmt 17 (before)
N004 ( 5, 5) [000080] ------------ * JTRUE void
N002 ( 1, 1) [000078] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000079] J------N---- \--* GT int
N001 ( 1, 1) [000077] ------------ \--* LCL_VAR int V04 tmp3 u:7
N001 [000077] LCL_VAR V04 tmp3 u:7 => $20c {SUB($282, $20b)}
N002 [000078] CNS_INT 0 => $40 {IntCns 0}
N003 [000079] GT => $20d {GT($20c, $40)}
***** BB04, stmt 17 (after)
N004 ( 5, 5) [000080] ------------ * JTRUE void
N002 ( 1, 1) [000078] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000079] J------N---- \--* GT int $20d
N001 ( 1, 1) [000077] ------------ \--* LCL_VAR int V04 tmp3 u:7 $20c
finish(BB04).
Succ(BB05).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB04).
SSA definition: set VN of local 5/4 to $283 {PhiDef($5, $4, $20e)}.
SSA definition: set VN of local 3/8 to $149 {PhiDef($3, $8, $245)}.
The SSA definition for ByrefExposed (#2) at start of BB05 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB05 is $c0 {InitVal($41)}
***** BB05, stmt 20 (before)
N002 ( 1, 1) [000107] ------------ /--* CNS_INT long -8
N003 ( 3, 3) [000108] ------------ /--* ADD long
N001 ( 1, 1) [000105] ------------ | \--* LCL_VAR long V03 tmp2 u:8 (last use)
N005 ( 3, 3) [000110] -A------R--- * ASG long
N004 ( 1, 1) [000109] D------N---- \--* LCL_VAR long V03 tmp2 d:9
N001 [000105] LCL_VAR V03 tmp2 u:8 (last use) => $149 {PhiDef($3, $8, $245)}
N002 [000107] CNS_INT -8 => $345 {LngCns: -8}
N003 [000108] ADD => $247 {ADD($149, $345)}
N004 [000109] LCL_VAR V03 tmp2 d:9 => $247 {ADD($149, $345)}
N005 [000110] ASG => $247 {ADD($149, $345)}
***** BB05, stmt 20 (after)
N002 ( 1, 1) [000107] ------------ /--* CNS_INT long -8 $345
N003 ( 3, 3) [000108] ------------ /--* ADD long $247
N001 ( 1, 1) [000105] ------------ | \--* LCL_VAR long V03 tmp2 u:8 (last use) $149
N005 ( 3, 3) [000110] -A------R--- * ASG long $247
N004 ( 1, 1) [000109] D------N---- \--* LCL_VAR long V03 tmp2 d:9 $247
---------
***** BB05, stmt 21 (before)
N012 ( 16, 13) [000124] ---XG------- /--* CAST int <- long
N011 ( 15, 11) [000123] ---XG------- | \--* HWIntrinsic long TrailingZeroCount
N009 ( 3, 2) [000121] *--XG------- | | /--* IND long
N008 ( 1, 1) [000120] ------------ | | | \--* LCL_VAR long V03 tmp2 u:9
N010 ( 14, 10) [000122] ---XG------- | \--* HWIntrinsic long ParallelBitDeposit
N004 ( 1, 1) [000117] ------------ | | /--* CNS_INT int 63
N005 ( 5, 5) [000118] ------------ | | /--* AND int
N002 ( 1, 1) [000115] ------------ | | | | /--* CNS_INT int -1
N003 ( 3, 3) [000116] ------------ | | | \--* ADD int
N001 ( 1, 1) [000114] ------------ | | | \--* LCL_VAR int V05 tmp4 u:4 (last use)
N007 ( 10, 7) [000119] --------R--- | \--* LSH long
N006 ( 1, 1) [000113] ------------ | \--* CNS_INT long 1
N014 ( 16, 13) [000126] -A-XG---R--- * ASG int
N013 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V06 tmp5 d:2
N001 [000114] LCL_VAR V05 tmp4 u:4 (last use) => $283 {PhiDef($5, $4, $20e)}
N002 [000115] CNS_INT -1 => $41 {IntCns -1}
N003 [000116] ADD => $20f {ADD($41, $283)}
N004 [000117] CNS_INT 63 => $4a {IntCns 63}
N005 [000118] AND => $210 {AND($4a, $20f)}
N006 [000113] CNS_INT 1 => $346 {LngCns: 1}
N007 [000119] LSH => $248 {LSH($346, $210)}
N008 [000120] LCL_VAR V03 tmp2 u:9 => $247 {ADD($149, $345)}
N009 [000121] IND => <l:$14a {ByrefExposedLoad($42, $247, $c0)}, c:$184 {184}>
VNForCastOper(int) is $46
N012 [000124] CAST => $211 {Cast($481, $46)}
N013 [000125] LCL_VAR V06 tmp5 d:2 => $211 {Cast($481, $46)}
N014 [000126] ASG => $211 {Cast($481, $46)}
***** BB05, stmt 21 (after)
N012 ( 16, 13) [000124] ---XG------- /--* CAST int <- long $211
N011 ( 15, 11) [000123] ---XG------- | \--* HWIntrinsic long TrailingZeroCount $481
N009 ( 3, 2) [000121] *--XG------- | | /--* IND long <l:$14a, c:$184>
N008 ( 1, 1) [000120] ------------ | | | \--* LCL_VAR long V03 tmp2 u:9 $247
N010 ( 14, 10) [000122] ---XG------- | \--* HWIntrinsic long ParallelBitDeposit $480
N004 ( 1, 1) [000117] ------------ | | /--* CNS_INT int 63 $4a
N005 ( 5, 5) [000118] ------------ | | /--* AND int $210
N002 ( 1, 1) [000115] ------------ | | | | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000116] ------------ | | | \--* ADD int $20f
N001 ( 1, 1) [000114] ------------ | | | \--* LCL_VAR int V05 tmp4 u:4 (last use) $283
N007 ( 10, 7) [000119] --------R--- | \--* LSH long $248
N006 ( 1, 1) [000113] ------------ | \--* CNS_INT long 1 $346
N014 ( 16, 13) [000126] -A-XG---R--- * ASG int $211
N013 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V06 tmp5 d:2 $211
---------
***** BB05, stmt 22 (before)
N011 ( 30, 14) [000010] ------------ * RETURN int
N009 ( 1, 1) [000138] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use)
N010 ( 29, 13) [000139] ------------ \--* ADD int
N007 ( 1, 1) [000135] ------------ | /--* CNS_INT int 6
N008 ( 27, 11) [000136] ------------ \--* LSH int
N006 ( 25, 9) [000166] ------------ \--* CAST int <- long
N004 ( 1, 1) [000132] ------------ | /--* CNS_INT long 8
N005 ( 24, 7) [000133] ------------ \--* DIV long
N002 ( 1, 1) [000129] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use)
N003 ( 3, 3) [000130] ------------ \--* SUB long
N001 ( 1, 1) [000128] ------------ \--* LCL_VAR long V03 tmp2 u:9 (last use)
N001 [000128] LCL_VAR V03 tmp2 u:9 (last use) => $247 {ADD($149, $345)}
N002 [000129] LCL_VAR V02 tmp1 u:2 (last use) => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N003 [000130] SUB => <l:$249 {SUB($247, $140)}, c:$24a {SUB($247, $180)}>
N004 [000132] CNS_INT 8 => $340 {LngCns: 8}
N005 [000133] DIV => <l:$24b {DIV($249, $340)}, c:$24c {DIV($24a, $340)}>
VNForCastOper(int) is $46
N006 [000166] CAST => <l:$212 {Cast($24b, $46)}, c:$213 {Cast($24c, $46)}>
N007 [000135] CNS_INT 6 => $4b {IntCns 6}
N008 [000136] LSH => <l:$214 {LSH($212, $4b)}, c:$215 {LSH($213, $4b)}>
N009 [000138] LCL_VAR V06 tmp5 u:2 (last use) => $211 {Cast($481, $46)}
N010 [000139] ADD => <l:$216 {ADD($211, $214)}, c:$217 {ADD($211, $215)}>
N011 [000010] RETURN => $1c3 {1c3}
***** BB05, stmt 22 (after)
N011 ( 30, 14) [000010] ------------ * RETURN int $1c3
N009 ( 1, 1) [000138] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use) $211
N010 ( 29, 13) [000139] ------------ \--* ADD int <l:$216, c:$217>
N007 ( 1, 1) [000135] ------------ | /--* CNS_INT int 6 $4b
N008 ( 27, 11) [000136] ------------ \--* LSH int <l:$214, c:$215>
N006 ( 25, 9) [000166] ------------ \--* CAST int <- long <l:$212, c:$213>
N004 ( 1, 1) [000132] ------------ | /--* CNS_INT long 8 $340
N005 ( 24, 7) [000133] ------------ \--* DIV long <l:$24b, c:$24c>
N002 ( 1, 1) [000129] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000130] ------------ \--* SUB long <l:$249, c:$24a>
N001 ( 1, 1) [000128] ------------ \--* LCL_VAR long V03 tmp2 u:9 (last use) $247
finish(BB05).
*************** In optHoistLoopCode()
Blocks/Trees before phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000142] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000159] ------------ | | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
N004 ( 5, 12) [000141] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000140] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000145] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000144] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000143] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
***** BB01, stmt 4
( 5, 8) [000172] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000171] ------------ \--* JTRUE void
N002 ( 1, 4) [000170] ------------ | /--* CNS_INT int 256 $43
N003 ( 3, 6) [000168] J------N---- \--* LT int $200
N001 ( 1, 1) [000169] ------------ \--* LCL_VAR int V04 tmp3 u:2 $80
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 5
( 2, 3) [000209] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000207] ------------ | * PHI long
N001 ( 0, 0) [000222] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000208] -A------R--- \--* ASG long
N006 ( 1, 1) [000206] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 6
( 2, 3) [000201] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000199] ------------ | * PHI int
N001 ( 0, 0) [000224] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000200] -A------R--- \--* ASG int
N006 ( 1, 1) [000198] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 7
( 28, 31) [000060] ------------ * STMT void (IL 0x000... ???)
N024 ( 6, 7) [000161] ---XG------- | /--* CAST int <- long $206
N023 ( 5, 5) [000053] ---XG------- | | \--* HWIntrinsic long PopCount $303
N022 ( 4, 4) [000052] *--XG------- | | \--* IND long <l:$145, c:$2c3>
N020 ( 1, 1) [000050] ------------ | | | /--* CNS_INT long 24 $343
N021 ( 2, 2) [000051] -------N---- | | \--* ADD long $243
N019 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N025 ( 26, 29) [000054] ---XG------- | /--* ADD int $207
N017 ( 6, 7) [000163] ---XG------- | | | /--* CAST int <- long $204
N016 ( 5, 5) [000043] ---XG------- | | | | \--* HWIntrinsic long PopCount $302
N015 ( 4, 4) [000042] *--XG------- | | | | \--* IND long <l:$144, c:$2c2>
N013 ( 1, 1) [000040] ------------ | | | | | /--* CNS_INT long 16 $342
N014 ( 2, 2) [000041] -------N---- | | | | \--* ADD long $242
N012 ( 1, 1) [000035] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:3 $141
N018 ( 19, 21) [000044] ---XG------- | | \--* ADD int $205
N010 ( 6, 7) [000165] ---XG------- | | | /--* CAST int <- long $202
N009 ( 5, 5) [000033] ---XG------- | | | | \--* HWIntrinsic long PopCount $301
N008 ( 4, 4) [000032] *--XG------- | | | | \--* IND long <l:$143, c:$2c1>
N006 ( 1, 1) [000030] ------------ | | | | | /--* CNS_INT long 8 $340
N007 ( 2, 2) [000031] -------N---- | | | | \--* ADD long $241
N005 ( 1, 1) [000028] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:3 $141
N011 ( 12, 13) [000034] ---XG------- | | \--* ADD int $203
N004 ( 5, 5) [000164] ---XG------- | | \--* CAST int <- long $201
N003 ( 4, 3) [000027] ---XG------- | | \--* HWIntrinsic long PopCount $300
N002 ( 3, 2) [000026] *--XG------- | | \--* IND long <l:$142, c:$2c0>
N001 ( 1, 1) [000025] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N027 ( 28, 31) [000056] ---XG---R--- | /--* SUB int $208
N026 ( 1, 1) [000024] ------------ | | \--* LCL_VAR int V04 tmp3 u:3 (last use) $280
N029 ( 28, 31) [000059] -A-XG---R--- \--* ASG int $208
N028 ( 1, 1) [000058] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $208
***** BB02, stmt 8
( 3, 3) [000070] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000066] ------------ | /--* CNS_INT long 32 $344
N003 ( 3, 3) [000067] ------------ | /--* ADD long $244
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000069] -A------R--- \--* ASG long $244
N004 ( 1, 1) [000068] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $244
***** BB02, stmt 9
( 5, 8) [000022] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000021] ------------ \--* JTRUE void
N002 ( 1, 4) [000019] ------------ | /--* CNS_INT int 256 $43
N003 ( 3, 6) [000020] J------N---- \--* GE int $209
N001 ( 1, 1) [000018] ------------ \--* LCL_VAR int V04 tmp3 u:4 $208
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 10
( 2, 3) [000205] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000203] ------------ | * PHI long
N001 ( 0, 0) [000218] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000204] -A------R--- \--* ASG long
N006 ( 1, 1) [000202] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 11
( 2, 3) [000197] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000195] ------------ | * PHI int
N001 ( 0, 0) [000220] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000196] -A------R--- \--* ASG int
N006 ( 1, 1) [000194] D------N---- \--* LCL_VAR int V04 tmp3 d:5
***** BB03, stmt 12
( 1, 3) [000075] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000072] ------------ | /--* LCL_VAR int V04 tmp3 u:5 $281
N003 ( 1, 3) [000074] -A------R--- \--* ASG int $281
N002 ( 1, 1) [000073] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $281
***** BB03, stmt 13
( 5, 5) [000177] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000176] ------------ \--* JTRUE void
N002 ( 1, 1) [000175] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000173] J------N---- \--* LE int $20a
N001 ( 1, 1) [000174] ------------ \--* LCL_VAR int V04 tmp3 u:5 $281
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
***** BB04, stmt 14
( 2, 3) [000189] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000187] ------------ | * PHI long
N001 ( 0, 0) [000238] ------------ | /--* PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ | \--* PHI_ARG long V03 tmp2 u:5 $146
N007 ( 2, 3) [000188] -A------R--- \--* ASG long
N006 ( 1, 1) [000186] D------N---- \--* LCL_VAR long V03 tmp2 d:6
***** BB04, stmt 15
( 2, 3) [000181] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000179] ------------ | * PHI int
N001 ( 0, 0) [000240] ------------ | /--* PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ | \--* PHI_ARG int V04 tmp3 u:5 $281
N007 ( 2, 3) [000180] -A------R--- \--* ASG int
N006 ( 1, 1) [000178] D------N---- \--* LCL_VAR int V04 tmp3 d:6
***** BB04, stmt 16
( 1, 3) [000086] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000083] ------------ | /--* LCL_VAR int V04 tmp3 u:6 $282
N003 ( 1, 3) [000085] -A------R--- \--* ASG int $282
N002 ( 1, 1) [000084] D------N---- \--* LCL_VAR int V05 tmp4 d:3 $282
***** BB04, stmt 17
( 7, 7) [000096] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000091] ---XG------- | /--* CAST int <- long $20b
N004 ( 4, 3) [000090] ---XG------- | | \--* HWIntrinsic long PopCount $440
N003 ( 3, 2) [000089] *--XG------- | | \--* IND long <l:$148, c:$400>
N002 ( 1, 1) [000088] ------------ | | \--* LCL_VAR long V03 tmp2 u:6 $147
N006 ( 7, 7) [000092] ---XG------- | /--* SUB int $20c
N001 ( 1, 1) [000087] ------------ | | \--* LCL_VAR int V04 tmp3 u:6 (last use) $282
N008 ( 7, 7) [000095] -A-XG---R--- \--* ASG int $20c
N007 ( 1, 1) [000094] D------N---- \--* LCL_VAR int V04 tmp3 d:7 $20c
***** BB04, stmt 18
( 3, 3) [000103] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000099] ------------ | /--* CNS_INT long 8 $340
N003 ( 3, 3) [000100] ------------ | /--* ADD long $246
N001 ( 1, 1) [000097] ------------ | | \--* LCL_VAR long V03 tmp2 u:6 (last use) $147
N005 ( 3, 3) [000102] -A------R--- \--* ASG long $246
N004 ( 1, 1) [000101] D------N---- \--* LCL_VAR long V03 tmp2 d:7 $246
***** BB04, stmt 19
( 5, 5) [000081] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000080] ------------ \--* JTRUE void
N002 ( 1, 1) [000078] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000079] J------N---- \--* GT int $20d
N001 ( 1, 1) [000077] ------------ \--* LCL_VAR int V04 tmp3 u:7 $20c
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 20
( 2, 3) [000193] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000191] ------------ | * PHI int
N001 ( 0, 0) [000234] ------------ | /--* PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ | \--* PHI_ARG int V05 tmp4 u:2 $281
N007 ( 2, 3) [000192] -A------R--- \--* ASG int
N006 ( 1, 1) [000190] D------N---- \--* LCL_VAR int V05 tmp4 d:4
***** BB05, stmt 21
( 2, 3) [000185] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000183] ------------ | * PHI long
N001 ( 0, 0) [000236] ------------ | /--* PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ | \--* PHI_ARG long V03 tmp2 u:5 $146
N007 ( 2, 3) [000184] -A------R--- \--* ASG long
N006 ( 1, 1) [000182] D------N---- \--* LCL_VAR long V03 tmp2 d:8
***** BB05, stmt 22
( 3, 3) [000111] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000107] ------------ | /--* CNS_INT long -8 $345
N003 ( 3, 3) [000108] ------------ | /--* ADD long $247
N001 ( 1, 1) [000105] ------------ | | \--* LCL_VAR long V03 tmp2 u:8 (last use) $149
N005 ( 3, 3) [000110] -A------R--- \--* ASG long $247
N004 ( 1, 1) [000109] D------N---- \--* LCL_VAR long V03 tmp2 d:9 $247
***** BB05, stmt 23
( 16, 13) [000127] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000124] ---XG------- | /--* CAST int <- long $211
N011 ( 15, 11) [000123] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount $481
N009 ( 3, 2) [000121] *--XG------- | | | /--* IND long <l:$14a, c:$184>
N008 ( 1, 1) [000120] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:9 $247
N010 ( 14, 10) [000122] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit $480
N004 ( 1, 1) [000117] ------------ | | | /--* CNS_INT int 63 $4a
N005 ( 5, 5) [000118] ------------ | | | /--* AND int $210
N002 ( 1, 1) [000115] ------------ | | | | | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000116] ------------ | | | | \--* ADD int $20f
N001 ( 1, 1) [000114] ------------ | | | | \--* LCL_VAR int V05 tmp4 u:4 (last use) $283
N007 ( 10, 7) [000119] --------R--- | | \--* LSH long $248
N006 ( 1, 1) [000113] ------------ | | \--* CNS_INT long 1 $346
N014 ( 16, 13) [000126] -A-XG---R--- \--* ASG int $211
N013 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V06 tmp5 d:2 $211
***** BB05, stmt 24
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int $1c3
N009 ( 1, 1) [000138] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use) $211
N010 ( 29, 13) [000139] ------------ \--* ADD int <l:$216, c:$217>
N007 ( 1, 1) [000135] ------------ | /--* CNS_INT int 6 $4b
N008 ( 27, 11) [000136] ------------ \--* LSH int <l:$214, c:$215>
N006 ( 25, 9) [000166] ------------ \--* CAST int <- long <l:$212, c:$213>
N004 ( 1, 1) [000132] ------------ | /--* CNS_INT long 8 $340
N005 ( 24, 7) [000133] ------------ \--* DIV long <l:$24b, c:$24c>
N002 ( 1, 1) [000129] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000130] ------------ \--* SUB long <l:$249, c:$24a>
N001 ( 1, 1) [000128] ------------ \--* LCL_VAR long V03 tmp2 u:9 (last use) $247
-------------------------------------------------------------------------------------------------------------------
optHoistLoopCode for loop L00 <BB02..BB02>:
Loop body does not contain a call
USEDEF (2)={V04 V03}
INOUT (3)={V04 V03 V02}
LOOPVARS(2)={V04 V03}
optHoistLoopExprsForBlock BB02 (weight= 2 ) of loop L00 <BB02..BB02>, firstBlock is true
optHoistLoopCode for loop L01 <BB04..BB04>:
Loop body does not contain a call
USEDEF (3)={V04 V03 V05}
INOUT (4)={V04 V03 V02 V05}
LOOPVARS(3)={V04 V03 V05}
optHoistLoopExprsForBlock BB04 (weight= 2 ) of loop L01 <BB04..BB04>, firstBlock is true
*************** In optVnCopyProp()
*************** In SsaBuilder::ComputeDominators(Compiler*, ...)
Copy Assertion for BB01
curSsaName stack: { }
Live vars: {V00} => {V00 V02}
Live vars: {V00 V02} => {V02}
Live vars: {V02} => {V02 V04}
Live vars: {V02 V04} => {V02 V03 V04}
Copy Assertion for BB03
curSsaName stack: { 0-[000003]:V00 2-[000140]:V02 3-[000014]:V03 4-[000143]:V04 }
Live vars: {V02 V03 V04} => {V02 V03 V04 V05}
VN based copy assertion for [000174] V04 @00000281 by [000073] V05 @00000281.
N001 ( 1, 1) [000174] ------------ * LCL_VAR int V04 tmp3 u:5 $281
New refCnts for V04: refCnt = 10, refCntWtd = 33
New refCnts for V05: refCnt = 4, refCntWtd = 4
copy propagated to:
N001 ( 1, 1) [000174] ------------ * LCL_VAR int V05 tmp4 u:2 $281
Copy Assertion for BB05
curSsaName stack: { 0-[000003]:V00 2-[000140]:V02 3-[000202]:V03 4-[000194]:V04 5-[000073]:V05 }
Live vars: {V02 V03 V05} => {V02 V05}
Live vars: {V02 V05} => {V02 V03 V05}
Live vars: {V02 V03 V05} => {V02 V03}
Live vars: {V02 V03} => {V02 V03 V06}
Live vars: {V02 V03 V06} => {V02 V06}
Live vars: {V02 V06} => {V06}
Live vars: {V06} => {}
Copy Assertion for BB04
curSsaName stack: { 0-[000003]:V00 2-[000140]:V02 3-[000202]:V03 4-[000194]:V04 5-[000073]:V05 }
Live vars: {V02 V03 V04} => {V02 V03 V04 V05}
Live vars: {V02 V03 V04 V05} => {V02 V03 V05}
VN based copy assertion for [000087] V04 @00000282 by [000084] V05 @00000282.
N001 ( 1, 1) [000087] ------------ * LCL_VAR int V04 tmp3 u:6 (last use) $282
New refCnts for V04: refCnt = 9, refCntWtd = 29
New refCnts for V05: refCnt = 5, refCntWtd = 6
copy propagated to:
N001 ( 1, 1) [000087] ------------ * LCL_VAR int V05 tmp4 u:3 (last use) $282
Live vars: {V02 V03 V05} => {V02 V03 V04 V05}
Live vars: {V02 V03 V04 V05} => {V02 V04 V05}
Live vars: {V02 V04 V05} => {V02 V03 V04 V05}
Copy Assertion for BB02
curSsaName stack: { 0-[000003]:V00 2-[000140]:V02 3-[000014]:V03 4-[000143]:V04 }
Live vars: {V02 V03 V04} => {V02 V03}
Live vars: {V02 V03} => {V02 V03 V04}
Live vars: {V02 V03 V04} => {V02 V04}
Live vars: {V02 V04} => {V02 V03 V04}
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000142] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000159] ------------ | | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
N004 ( 5, 12) [000141] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000140] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000145] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000144] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000143] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
***** BB01, stmt 4
( 5, 8) [000172] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000171] ------------ \--* JTRUE void
N002 ( 1, 4) [000170] ------------ | /--* CNS_INT int 256 $43
N003 ( 3, 6) [000168] J------N---- \--* LT int $200
N001 ( 1, 1) [000169] ------------ \--* LCL_VAR int V04 tmp3 u:2 $80
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 5
( 2, 3) [000209] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000207] ------------ | * PHI long
N001 ( 0, 0) [000222] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000208] -A------R--- \--* ASG long
N006 ( 1, 1) [000206] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 6
( 2, 3) [000201] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000199] ------------ | * PHI int
N001 ( 0, 0) [000224] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000200] -A------R--- \--* ASG int
N006 ( 1, 1) [000198] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 7
( 28, 31) [000060] ------------ * STMT void (IL 0x000... ???)
N024 ( 6, 7) [000161] ---XG------- | /--* CAST int <- long $206
N023 ( 5, 5) [000053] ---XG------- | | \--* HWIntrinsic long PopCount $303
N022 ( 4, 4) [000052] *--XG------- | | \--* IND long <l:$145, c:$2c3>
N020 ( 1, 1) [000050] ------------ | | | /--* CNS_INT long 24 $343
N021 ( 2, 2) [000051] -------N---- | | \--* ADD long $243
N019 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N025 ( 26, 29) [000054] ---XG------- | /--* ADD int $207
N017 ( 6, 7) [000163] ---XG------- | | | /--* CAST int <- long $204
N016 ( 5, 5) [000043] ---XG------- | | | | \--* HWIntrinsic long PopCount $302
N015 ( 4, 4) [000042] *--XG------- | | | | \--* IND long <l:$144, c:$2c2>
N013 ( 1, 1) [000040] ------------ | | | | | /--* CNS_INT long 16 $342
N014 ( 2, 2) [000041] -------N---- | | | | \--* ADD long $242
N012 ( 1, 1) [000035] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:3 $141
N018 ( 19, 21) [000044] ---XG------- | | \--* ADD int $205
N010 ( 6, 7) [000165] ---XG------- | | | /--* CAST int <- long $202
N009 ( 5, 5) [000033] ---XG------- | | | | \--* HWIntrinsic long PopCount $301
N008 ( 4, 4) [000032] *--XG------- | | | | \--* IND long <l:$143, c:$2c1>
N006 ( 1, 1) [000030] ------------ | | | | | /--* CNS_INT long 8 $340
N007 ( 2, 2) [000031] -------N---- | | | | \--* ADD long $241
N005 ( 1, 1) [000028] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:3 $141
N011 ( 12, 13) [000034] ---XG------- | | \--* ADD int $203
N004 ( 5, 5) [000164] ---XG------- | | \--* CAST int <- long $201
N003 ( 4, 3) [000027] ---XG------- | | \--* HWIntrinsic long PopCount $300
N002 ( 3, 2) [000026] *--XG------- | | \--* IND long <l:$142, c:$2c0>
N001 ( 1, 1) [000025] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N027 ( 28, 31) [000056] ---XG---R--- | /--* SUB int $208
N026 ( 1, 1) [000024] ------------ | | \--* LCL_VAR int V04 tmp3 u:3 (last use) $280
N029 ( 28, 31) [000059] -A-XG---R--- \--* ASG int $208
N028 ( 1, 1) [000058] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $208
***** BB02, stmt 8
( 3, 3) [000070] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000066] ------------ | /--* CNS_INT long 32 $344
N003 ( 3, 3) [000067] ------------ | /--* ADD long $244
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000069] -A------R--- \--* ASG long $244
N004 ( 1, 1) [000068] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $244
***** BB02, stmt 9
( 5, 8) [000022] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000021] ------------ \--* JTRUE void
N002 ( 1, 4) [000019] ------------ | /--* CNS_INT int 256 $43
N003 ( 3, 6) [000020] J------N---- \--* GE int $209
N001 ( 1, 1) [000018] ------------ \--* LCL_VAR int V04 tmp3 u:4 $208
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 10
( 2, 3) [000205] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000203] ------------ | * PHI long
N001 ( 0, 0) [000218] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000204] -A------R--- \--* ASG long
N006 ( 1, 1) [000202] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 11
( 2, 3) [000197] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000195] ------------ | * PHI int
N001 ( 0, 0) [000220] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000196] -A------R--- \--* ASG int
N006 ( 1, 1) [000194] D------N---- \--* LCL_VAR int V04 tmp3 d:5
***** BB03, stmt 12
( 1, 3) [000075] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000072] ------------ | /--* LCL_VAR int V04 tmp3 u:5 $281
N003 ( 1, 3) [000074] -A------R--- \--* ASG int $281
N002 ( 1, 1) [000073] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $281
***** BB03, stmt 13
( 5, 5) [000177] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000176] ------------ \--* JTRUE void
N002 ( 1, 1) [000175] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000173] J------N---- \--* LE int $20a
N001 ( 1, 1) [000174] ------------ \--* LCL_VAR int V05 tmp4 u:2 $281
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
***** BB04, stmt 14
( 2, 3) [000189] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000187] ------------ | * PHI long
N001 ( 0, 0) [000238] ------------ | /--* PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ | \--* PHI_ARG long V03 tmp2 u:5 $146
N007 ( 2, 3) [000188] -A------R--- \--* ASG long
N006 ( 1, 1) [000186] D------N---- \--* LCL_VAR long V03 tmp2 d:6
***** BB04, stmt 15
( 2, 3) [000181] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000179] ------------ | * PHI int
N001 ( 0, 0) [000240] ------------ | /--* PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ | \--* PHI_ARG int V04 tmp3 u:5 $281
N007 ( 2, 3) [000180] -A------R--- \--* ASG int
N006 ( 1, 1) [000178] D------N---- \--* LCL_VAR int V04 tmp3 d:6
***** BB04, stmt 16
( 1, 3) [000086] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000083] ------------ | /--* LCL_VAR int V04 tmp3 u:6 $282
N003 ( 1, 3) [000085] -A------R--- \--* ASG int $282
N002 ( 1, 1) [000084] D------N---- \--* LCL_VAR int V05 tmp4 d:3 $282
***** BB04, stmt 17
( 7, 7) [000096] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000091] ---XG------- | /--* CAST int <- long $20b
N004 ( 4, 3) [000090] ---XG------- | | \--* HWIntrinsic long PopCount $440
N003 ( 3, 2) [000089] *--XG------- | | \--* IND long <l:$148, c:$400>
N002 ( 1, 1) [000088] ------------ | | \--* LCL_VAR long V03 tmp2 u:6 $147
N006 ( 7, 7) [000092] ---XG------- | /--* SUB int $20c
N001 ( 1, 1) [000087] ------------ | | \--* LCL_VAR int V05 tmp4 u:3 (last use) $282
N008 ( 7, 7) [000095] -A-XG---R--- \--* ASG int $20c
N007 ( 1, 1) [000094] D------N---- \--* LCL_VAR int V04 tmp3 d:7 $20c
***** BB04, stmt 18
( 3, 3) [000103] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000099] ------------ | /--* CNS_INT long 8 $340
N003 ( 3, 3) [000100] ------------ | /--* ADD long $246
N001 ( 1, 1) [000097] ------------ | | \--* LCL_VAR long V03 tmp2 u:6 (last use) $147
N005 ( 3, 3) [000102] -A------R--- \--* ASG long $246
N004 ( 1, 1) [000101] D------N---- \--* LCL_VAR long V03 tmp2 d:7 $246
***** BB04, stmt 19
( 5, 5) [000081] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000080] ------------ \--* JTRUE void
N002 ( 1, 1) [000078] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000079] J------N---- \--* GT int $20d
N001 ( 1, 1) [000077] ------------ \--* LCL_VAR int V04 tmp3 u:7 $20c
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 20
( 2, 3) [000193] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000191] ------------ | * PHI int
N001 ( 0, 0) [000234] ------------ | /--* PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ | \--* PHI_ARG int V05 tmp4 u:2 $281
N007 ( 2, 3) [000192] -A------R--- \--* ASG int
N006 ( 1, 1) [000190] D------N---- \--* LCL_VAR int V05 tmp4 d:4
***** BB05, stmt 21
( 2, 3) [000185] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000183] ------------ | * PHI long
N001 ( 0, 0) [000236] ------------ | /--* PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ | \--* PHI_ARG long V03 tmp2 u:5 $146
N007 ( 2, 3) [000184] -A------R--- \--* ASG long
N006 ( 1, 1) [000182] D------N---- \--* LCL_VAR long V03 tmp2 d:8
***** BB05, stmt 22
( 3, 3) [000111] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000107] ------------ | /--* CNS_INT long -8 $345
N003 ( 3, 3) [000108] ------------ | /--* ADD long $247
N001 ( 1, 1) [000105] ------------ | | \--* LCL_VAR long V03 tmp2 u:8 (last use) $149
N005 ( 3, 3) [000110] -A------R--- \--* ASG long $247
N004 ( 1, 1) [000109] D------N---- \--* LCL_VAR long V03 tmp2 d:9 $247
***** BB05, stmt 23
( 16, 13) [000127] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000124] ---XG------- | /--* CAST int <- long $211
N011 ( 15, 11) [000123] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount $481
N009 ( 3, 2) [000121] *--XG------- | | | /--* IND long <l:$14a, c:$184>
N008 ( 1, 1) [000120] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:9 $247
N010 ( 14, 10) [000122] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit $480
N004 ( 1, 1) [000117] ------------ | | | /--* CNS_INT int 63 $4a
N005 ( 5, 5) [000118] ------------ | | | /--* AND int $210
N002 ( 1, 1) [000115] ------------ | | | | | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000116] ------------ | | | | \--* ADD int $20f
N001 ( 1, 1) [000114] ------------ | | | | \--* LCL_VAR int V05 tmp4 u:4 (last use) $283
N007 ( 10, 7) [000119] --------R--- | | \--* LSH long $248
N006 ( 1, 1) [000113] ------------ | | \--* CNS_INT long 1 $346
N014 ( 16, 13) [000126] -A-XG---R--- \--* ASG int $211
N013 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V06 tmp5 d:2 $211
***** BB05, stmt 24
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int $1c3
N009 ( 1, 1) [000138] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use) $211
N010 ( 29, 13) [000139] ------------ \--* ADD int <l:$216, c:$217>
N007 ( 1, 1) [000135] ------------ | /--* CNS_INT int 6 $4b
N008 ( 27, 11) [000136] ------------ \--* LSH int <l:$214, c:$215>
N006 ( 25, 9) [000166] ------------ \--* CAST int <- long <l:$212, c:$213>
N004 ( 1, 1) [000132] ------------ | /--* CNS_INT long 8 $340
N005 ( 24, 7) [000133] ------------ \--* DIV long <l:$24b, c:$24c>
N002 ( 1, 1) [000129] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000130] ------------ \--* SUB long <l:$249, c:$24a>
N001 ( 1, 1) [000128] ------------ \--* LCL_VAR long V03 tmp2 u:9 (last use) $247
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
*************** In optAssertionPropMain()
Blocks/Trees at start of phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000142] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000159] ------------ | | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
N004 ( 5, 12) [000141] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000140] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000145] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000144] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000143] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
***** BB01, stmt 4
( 5, 8) [000172] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000171] ------------ \--* JTRUE void
N002 ( 1, 4) [000170] ------------ | /--* CNS_INT int 256 $43
N003 ( 3, 6) [000168] J------N---- \--* LT int $200
N001 ( 1, 1) [000169] ------------ \--* LCL_VAR int V04 tmp3 u:2 $80
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 5
( 2, 3) [000209] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000207] ------------ | * PHI long
N001 ( 0, 0) [000222] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000208] -A------R--- \--* ASG long
N006 ( 1, 1) [000206] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 6
( 2, 3) [000201] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000199] ------------ | * PHI int
N001 ( 0, 0) [000224] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000200] -A------R--- \--* ASG int
N006 ( 1, 1) [000198] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 7
( 28, 31) [000060] ------------ * STMT void (IL 0x000... ???)
N024 ( 6, 7) [000161] ---XG------- | /--* CAST int <- long $206
N023 ( 5, 5) [000053] ---XG------- | | \--* HWIntrinsic long PopCount $303
N022 ( 4, 4) [000052] *--XG------- | | \--* IND long <l:$145, c:$2c3>
N020 ( 1, 1) [000050] ------------ | | | /--* CNS_INT long 24 $343
N021 ( 2, 2) [000051] -------N---- | | \--* ADD long $243
N019 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N025 ( 26, 29) [000054] ---XG------- | /--* ADD int $207
N017 ( 6, 7) [000163] ---XG------- | | | /--* CAST int <- long $204
N016 ( 5, 5) [000043] ---XG------- | | | | \--* HWIntrinsic long PopCount $302
N015 ( 4, 4) [000042] *--XG------- | | | | \--* IND long <l:$144, c:$2c2>
N013 ( 1, 1) [000040] ------------ | | | | | /--* CNS_INT long 16 $342
N014 ( 2, 2) [000041] -------N---- | | | | \--* ADD long $242
N012 ( 1, 1) [000035] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:3 $141
N018 ( 19, 21) [000044] ---XG------- | | \--* ADD int $205
N010 ( 6, 7) [000165] ---XG------- | | | /--* CAST int <- long $202
N009 ( 5, 5) [000033] ---XG------- | | | | \--* HWIntrinsic long PopCount $301
N008 ( 4, 4) [000032] *--XG------- | | | | \--* IND long <l:$143, c:$2c1>
N006 ( 1, 1) [000030] ------------ | | | | | /--* CNS_INT long 8 $340
N007 ( 2, 2) [000031] -------N---- | | | | \--* ADD long $241
N005 ( 1, 1) [000028] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:3 $141
N011 ( 12, 13) [000034] ---XG------- | | \--* ADD int $203
N004 ( 5, 5) [000164] ---XG------- | | \--* CAST int <- long $201
N003 ( 4, 3) [000027] ---XG------- | | \--* HWIntrinsic long PopCount $300
N002 ( 3, 2) [000026] *--XG------- | | \--* IND long <l:$142, c:$2c0>
N001 ( 1, 1) [000025] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N027 ( 28, 31) [000056] ---XG---R--- | /--* SUB int $208
N026 ( 1, 1) [000024] ------------ | | \--* LCL_VAR int V04 tmp3 u:3 (last use) $280
N029 ( 28, 31) [000059] -A-XG---R--- \--* ASG int $208
N028 ( 1, 1) [000058] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $208
***** BB02, stmt 8
( 3, 3) [000070] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000066] ------------ | /--* CNS_INT long 32 $344
N003 ( 3, 3) [000067] ------------ | /--* ADD long $244
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000069] -A------R--- \--* ASG long $244
N004 ( 1, 1) [000068] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $244
***** BB02, stmt 9
( 5, 8) [000022] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000021] ------------ \--* JTRUE void
N002 ( 1, 4) [000019] ------------ | /--* CNS_INT int 256 $43
N003 ( 3, 6) [000020] J------N---- \--* GE int $209
N001 ( 1, 1) [000018] ------------ \--* LCL_VAR int V04 tmp3 u:4 $208
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 10
( 2, 3) [000205] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000203] ------------ | * PHI long
N001 ( 0, 0) [000218] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000204] -A------R--- \--* ASG long
N006 ( 1, 1) [000202] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 11
( 2, 3) [000197] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000195] ------------ | * PHI int
N001 ( 0, 0) [000220] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000196] -A------R--- \--* ASG int
N006 ( 1, 1) [000194] D------N---- \--* LCL_VAR int V04 tmp3 d:5
***** BB03, stmt 12
( 1, 3) [000075] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000072] ------------ | /--* LCL_VAR int V04 tmp3 u:5 $281
N003 ( 1, 3) [000074] -A------R--- \--* ASG int $281
N002 ( 1, 1) [000073] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $281
***** BB03, stmt 13
( 5, 5) [000177] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000176] ------------ \--* JTRUE void
N002 ( 1, 1) [000175] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000173] J------N---- \--* LE int $20a
N001 ( 1, 1) [000174] ------------ \--* LCL_VAR int V05 tmp4 u:2 $281
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
***** BB04, stmt 14
( 2, 3) [000189] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000187] ------------ | * PHI long
N001 ( 0, 0) [000238] ------------ | /--* PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ | \--* PHI_ARG long V03 tmp2 u:5 $146
N007 ( 2, 3) [000188] -A------R--- \--* ASG long
N006 ( 1, 1) [000186] D------N---- \--* LCL_VAR long V03 tmp2 d:6
***** BB04, stmt 15
( 2, 3) [000181] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000179] ------------ | * PHI int
N001 ( 0, 0) [000240] ------------ | /--* PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ | \--* PHI_ARG int V04 tmp3 u:5 $281
N007 ( 2, 3) [000180] -A------R--- \--* ASG int
N006 ( 1, 1) [000178] D------N---- \--* LCL_VAR int V04 tmp3 d:6
***** BB04, stmt 16
( 1, 3) [000086] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000083] ------------ | /--* LCL_VAR int V04 tmp3 u:6 $282
N003 ( 1, 3) [000085] -A------R--- \--* ASG int $282
N002 ( 1, 1) [000084] D------N---- \--* LCL_VAR int V05 tmp4 d:3 $282
***** BB04, stmt 17
( 7, 7) [000096] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000091] ---XG------- | /--* CAST int <- long $20b
N004 ( 4, 3) [000090] ---XG------- | | \--* HWIntrinsic long PopCount $440
N003 ( 3, 2) [000089] *--XG------- | | \--* IND long <l:$148, c:$400>
N002 ( 1, 1) [000088] ------------ | | \--* LCL_VAR long V03 tmp2 u:6 $147
N006 ( 7, 7) [000092] ---XG------- | /--* SUB int $20c
N001 ( 1, 1) [000087] ------------ | | \--* LCL_VAR int V05 tmp4 u:3 (last use) $282
N008 ( 7, 7) [000095] -A-XG---R--- \--* ASG int $20c
N007 ( 1, 1) [000094] D------N---- \--* LCL_VAR int V04 tmp3 d:7 $20c
***** BB04, stmt 18
( 3, 3) [000103] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000099] ------------ | /--* CNS_INT long 8 $340
N003 ( 3, 3) [000100] ------------ | /--* ADD long $246
N001 ( 1, 1) [000097] ------------ | | \--* LCL_VAR long V03 tmp2 u:6 (last use) $147
N005 ( 3, 3) [000102] -A------R--- \--* ASG long $246
N004 ( 1, 1) [000101] D------N---- \--* LCL_VAR long V03 tmp2 d:7 $246
***** BB04, stmt 19
( 5, 5) [000081] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000080] ------------ \--* JTRUE void
N002 ( 1, 1) [000078] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000079] J------N---- \--* GT int $20d
N001 ( 1, 1) [000077] ------------ \--* LCL_VAR int V04 tmp3 u:7 $20c
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 20
( 2, 3) [000193] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000191] ------------ | * PHI int
N001 ( 0, 0) [000234] ------------ | /--* PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ | \--* PHI_ARG int V05 tmp4 u:2 $281
N007 ( 2, 3) [000192] -A------R--- \--* ASG int
N006 ( 1, 1) [000190] D------N---- \--* LCL_VAR int V05 tmp4 d:4
***** BB05, stmt 21
( 2, 3) [000185] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000183] ------------ | * PHI long
N001 ( 0, 0) [000236] ------------ | /--* PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ | \--* PHI_ARG long V03 tmp2 u:5 $146
N007 ( 2, 3) [000184] -A------R--- \--* ASG long
N006 ( 1, 1) [000182] D------N---- \--* LCL_VAR long V03 tmp2 d:8
***** BB05, stmt 22
( 3, 3) [000111] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000107] ------------ | /--* CNS_INT long -8 $345
N003 ( 3, 3) [000108] ------------ | /--* ADD long $247
N001 ( 1, 1) [000105] ------------ | | \--* LCL_VAR long V03 tmp2 u:8 (last use) $149
N005 ( 3, 3) [000110] -A------R--- \--* ASG long $247
N004 ( 1, 1) [000109] D------N---- \--* LCL_VAR long V03 tmp2 d:9 $247
***** BB05, stmt 23
( 16, 13) [000127] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000124] ---XG------- | /--* CAST int <- long $211
N011 ( 15, 11) [000123] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount $481
N009 ( 3, 2) [000121] *--XG------- | | | /--* IND long <l:$14a, c:$184>
N008 ( 1, 1) [000120] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:9 $247
N010 ( 14, 10) [000122] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit $480
N004 ( 1, 1) [000117] ------------ | | | /--* CNS_INT int 63 $4a
N005 ( 5, 5) [000118] ------------ | | | /--* AND int $210
N002 ( 1, 1) [000115] ------------ | | | | | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000116] ------------ | | | | \--* ADD int $20f
N001 ( 1, 1) [000114] ------------ | | | | \--* LCL_VAR int V05 tmp4 u:4 (last use) $283
N007 ( 10, 7) [000119] --------R--- | | \--* LSH long $248
N006 ( 1, 1) [000113] ------------ | | \--* CNS_INT long 1 $346
N014 ( 16, 13) [000126] -A-XG---R--- \--* ASG int $211
N013 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V06 tmp5 d:2 $211
***** BB05, stmt 24
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int $1c3
N009 ( 1, 1) [000138] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use) $211
N010 ( 29, 13) [000139] ------------ \--* ADD int <l:$216, c:$217>
N007 ( 1, 1) [000135] ------------ | /--* CNS_INT int 6 $4b
N008 ( 27, 11) [000136] ------------ \--* LSH int <l:$214, c:$215>
N006 ( 25, 9) [000166] ------------ \--* CAST int <- long <l:$212, c:$213>
N004 ( 1, 1) [000132] ------------ | /--* CNS_INT long 8 $340
N005 ( 24, 7) [000133] ------------ \--* DIV long <l:$24b, c:$24c>
N002 ( 1, 1) [000129] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000130] ------------ \--* SUB long <l:$249, c:$24a>
N001 ( 1, 1) [000128] ------------ \--* LCL_VAR long V03 tmp2 u:9 (last use) $247
-------------------------------------------------------------------------------------------------------------------
GenTreeNode creates assertion:
N004 ( 5, 8) [000171] ------------ * JTRUE void
In BB01 New Global Constant Assertion: (512, 64) ($200,$40) Loop_Bnd {LT($80, $43)} is not {IntCns 0} index=#01, mask=0000000000000001
GenTreeNode creates assertion:
N004 ( 5, 8) [000171] ------------ * JTRUE void
In BB01 New Global Constant Assertion: (512, 64) ($200,$40) Loop_Bnd {LT($80, $43)} is {IntCns 0} index=#02, mask=0000000000000002
GenTreeNode creates assertion:
N004 ( 5, 8) [000021] ------------ * JTRUE void
In BB02 New Global Constant Assertion: (521, 64) ($209,$40) Loop_Bnd {GE($208, $43)} is not {IntCns 0} index=#03, mask=0000000000000004
GenTreeNode creates assertion:
N004 ( 5, 8) [000021] ------------ * JTRUE void
In BB02 New Global Constant Assertion: (521, 64) ($209,$40) Loop_Bnd {GE($208, $43)} is {IntCns 0} index=#04, mask=0000000000000008
GenTreeNode creates assertion:
N004 ( 5, 5) [000176] ------------ * JTRUE void
In BB03 New Global Constant Assertion: (522, 64) ($20a,$40) Loop_Bnd {LE($281, $40)} is not {IntCns 0} index=#05, mask=0000000000000010
GenTreeNode creates assertion:
N004 ( 5, 5) [000176] ------------ * JTRUE void
In BB03 New Global Constant Assertion: (522, 64) ($20a,$40) Loop_Bnd {LE($281, $40)} is {IntCns 0} index=#06, mask=0000000000000020
GenTreeNode creates assertion:
N004 ( 5, 5) [000080] ------------ * JTRUE void
In BB04 New Global Constant Assertion: (525, 64) ($20d,$40) Loop_Bnd {GT($20c, $40)} is not {IntCns 0} index=#07, mask=0000000000000040
GenTreeNode creates assertion:
N004 ( 5, 5) [000080] ------------ * JTRUE void
In BB04 New Global Constant Assertion: (525, 64) ($20d,$40) Loop_Bnd {GT($20c, $40)} is {IntCns 0} index=#08, mask=0000000000000080
BB01 valueGen = 0000000000000002 => BB03 valueGen = 0000000000000001,
BB02 valueGen = 0000000000000008 => BB02 valueGen = 0000000000000004,
BB03 valueGen = 0000000000000020 => BB05 valueGen = 0000000000000010,
BB04 valueGen = 0000000000000080 => BB04 valueGen = 0000000000000040,
BB05 valueGen = 0000000000000000AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000
AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000
AssertionPropCallback::Changed : BB01 before out -> 00000000000000FF; after out -> 0000000000000002;
jumpDest before out -> 00000000000000FF; jumpDest after out -> 0000000000000001;
AssertionPropCallback::StartMerge: BB02 in -> 00000000000000FF
AssertionPropCallback::Merge : BB02 in -> 00000000000000FF, predBlock BB01 out -> 0000000000000002
AssertionPropCallback::Merge : BB02 in -> 0000000000000002, predBlock BB02 out -> 00000000000000FF
AssertionPropCallback::EndMerge : BB02 in -> 0000000000000002
AssertionPropCallback::Changed : BB02 before out -> 00000000000000FF; after out -> 000000000000000A;
jumpDest before out -> 00000000000000FF; jumpDest after out -> 0000000000000006;
AssertionPropCallback::StartMerge: BB03 in -> 00000000000000FF
AssertionPropCallback::Merge : BB03 in -> 00000000000000FF, predBlock BB01 out -> 0000000000000002
AssertionPropCallback::Merge : BB03 in -> 0000000000000001, predBlock BB02 out -> 000000000000000A
AssertionPropCallback::EndMerge : BB03 in -> 0000000000000000
AssertionPropCallback::Changed : BB03 before out -> 00000000000000FF; after out -> 0000000000000020;
jumpDest before out -> 00000000000000FF; jumpDest after out -> 0000000000000010;
AssertionPropCallback::StartMerge: BB03 in -> 0000000000000000
AssertionPropCallback::Merge : BB03 in -> 0000000000000000, predBlock BB01 out -> 0000000000000002
AssertionPropCallback::Merge : BB03 in -> 0000000000000000, predBlock BB02 out -> 000000000000000A
AssertionPropCallback::EndMerge : BB03 in -> 0000000000000000
AssertionPropCallback::Unchanged : BB03 out -> 0000000000000020; jumpDest out -> 0000000000000010
AssertionPropCallback::StartMerge: BB02 in -> 0000000000000002
AssertionPropCallback::Merge : BB02 in -> 0000000000000002, predBlock BB01 out -> 0000000000000002
AssertionPropCallback::Merge : BB02 in -> 0000000000000002, predBlock BB02 out -> 000000000000000A
AssertionPropCallback::EndMerge : BB02 in -> 0000000000000002
AssertionPropCallback::Unchanged : BB02 out -> 000000000000000A; jumpDest out -> 0000000000000006
AssertionPropCallback::StartMerge: BB04 in -> 00000000000000FF
AssertionPropCallback::Merge : BB04 in -> 00000000000000FF, predBlock BB03 out -> 0000000000000020
AssertionPropCallback::Merge : BB04 in -> 0000000000000020, predBlock BB04 out -> 00000000000000FF
AssertionPropCallback::EndMerge : BB04 in -> 0000000000000020
AssertionPropCallback::Changed : BB04 before out -> 00000000000000FF; after out -> 00000000000000A0;
jumpDest before out -> 00000000000000FF; jumpDest after out -> 0000000000000060;
AssertionPropCallback::StartMerge: BB05 in -> 00000000000000FF
AssertionPropCallback::Merge : BB05 in -> 00000000000000FF, predBlock BB03 out -> 0000000000000020
AssertionPropCallback::Merge : BB05 in -> 0000000000000010, predBlock BB04 out -> 00000000000000A0
AssertionPropCallback::EndMerge : BB05 in -> 0000000000000000
AssertionPropCallback::Changed : BB05 before out -> 00000000000000FF; after out -> 0000000000000000;
jumpDest before out -> 00000000000000FF; jumpDest after out -> 0000000000000000;
AssertionPropCallback::StartMerge: BB05 in -> 0000000000000000
AssertionPropCallback::Merge : BB05 in -> 0000000000000000, predBlock BB03 out -> 0000000000000020
AssertionPropCallback::Merge : BB05 in -> 0000000000000000, predBlock BB04 out -> 00000000000000A0
AssertionPropCallback::EndMerge : BB05 in -> 0000000000000000
AssertionPropCallback::Unchanged : BB05 out -> 0000000000000000; jumpDest out -> 0000000000000000
AssertionPropCallback::StartMerge: BB04 in -> 0000000000000020
AssertionPropCallback::Merge : BB04 in -> 0000000000000020, predBlock BB03 out -> 0000000000000020
AssertionPropCallback::Merge : BB04 in -> 0000000000000020, predBlock BB04 out -> 00000000000000A0
AssertionPropCallback::EndMerge : BB04 in -> 0000000000000020
AssertionPropCallback::Unchanged : BB04 out -> 00000000000000A0; jumpDest out -> 0000000000000060
BB01 valueIn = 0000000000000000 valueOut = 0000000000000002 => BB03 valueOut= 0000000000000001
BB02 valueIn = 0000000000000002 valueOut = 000000000000000A => BB02 valueOut= 0000000000000006
BB03 valueIn = 0000000000000000 valueOut = 0000000000000020 => BB05 valueOut= 0000000000000010
BB04 valueIn = 0000000000000020 valueOut = 00000000000000A0 => BB04 valueOut= 0000000000000060
BB05 valueIn = 0000000000000000 valueOut = 0000000000000000
Propagating 0000000000000000 assertions for BB01, stmt [000142], tree [000159], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000142], tree [000001], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000142], tree [000140], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000142], tree [000141], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000145], tree [000003], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000145], tree [000143], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000145], tree [000144], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000016], tree [000013], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000016], tree [000014], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000016], tree [000015], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000172], tree [000169], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000172], tree [000170], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000172], tree [000168], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000025], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000026], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000027], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000164], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000028], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000030], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000031], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000032], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000033], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000165], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000034], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000035], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000040], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000041], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000042], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000043], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000163], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000044], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000045], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000050], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000051], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000052], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000053], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000161], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000054], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000024], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000056], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000058], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000060], tree [000059], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000070], tree [000061], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000070], tree [000066], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000070], tree [000067], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000070], tree [000068], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000070], tree [000069], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000022], tree [000018], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000022], tree [000019], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000022], tree [000020], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000075], tree [000072], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000075], tree [000073], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000075], tree [000074], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000177], tree [000174], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000177], tree [000175], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000177], tree [000173], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000086], tree [000083], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000086], tree [000084], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000086], tree [000085], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000096], tree [000087], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000096], tree [000088], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000096], tree [000089], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000096], tree [000090], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000096], tree [000091], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000096], tree [000092], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000096], tree [000094], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000096], tree [000095], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000103], tree [000097], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000103], tree [000099], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000103], tree [000100], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000103], tree [000101], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000103], tree [000102], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000081], tree [000077], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000081], tree [000078], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000081], tree [000079], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000111], tree [000105], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000111], tree [000107], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000111], tree [000108], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000111], tree [000109], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000111], tree [000110], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000114], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000115], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000116], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000117], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000118], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000113], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000119], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000120], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000121], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000122], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000123], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000124], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000125], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000127], tree [000126], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000011], tree [000128], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000011], tree [000129], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000011], tree [000130], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000011], tree [000132], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000011], tree [000133], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000011], tree [000166], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000011], tree [000135], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000011], tree [000136], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000011], tree [000138], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000011], tree [000139], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000011], tree [000010], tree -> 0
*************** In fgDebugCheckBBlist
*************** In OptimizeRangeChecks()
Blocks/trees before phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000142] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000159] ------------ | | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
N004 ( 5, 12) [000141] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000140] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000145] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000144] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000143] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
***** BB01, stmt 4
( 5, 8) [000172] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000171] ------------ \--* JTRUE void
N002 ( 1, 4) [000170] ------------ | /--* CNS_INT int 256 $43
N003 ( 3, 6) [000168] J------N---- \--* LT int $200
N001 ( 1, 1) [000169] ------------ \--* LCL_VAR int V04 tmp3 u:2 $80
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 5
( 2, 3) [000209] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000207] ------------ | * PHI long
N001 ( 0, 0) [000222] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000208] -A------R--- \--* ASG long
N006 ( 1, 1) [000206] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 6
( 2, 3) [000201] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000199] ------------ | * PHI int
N001 ( 0, 0) [000224] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000200] -A------R--- \--* ASG int
N006 ( 1, 1) [000198] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 7
( 28, 31) [000060] ------------ * STMT void (IL 0x000... ???)
N024 ( 6, 7) [000161] ---XG------- | /--* CAST int <- long $206
N023 ( 5, 5) [000053] ---XG------- | | \--* HWIntrinsic long PopCount $303
N022 ( 4, 4) [000052] *--XG------- | | \--* IND long <l:$145, c:$2c3>
N020 ( 1, 1) [000050] ------------ | | | /--* CNS_INT long 24 $343
N021 ( 2, 2) [000051] -------N---- | | \--* ADD long $243
N019 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N025 ( 26, 29) [000054] ---XG------- | /--* ADD int $207
N017 ( 6, 7) [000163] ---XG------- | | | /--* CAST int <- long $204
N016 ( 5, 5) [000043] ---XG------- | | | | \--* HWIntrinsic long PopCount $302
N015 ( 4, 4) [000042] *--XG------- | | | | \--* IND long <l:$144, c:$2c2>
N013 ( 1, 1) [000040] ------------ | | | | | /--* CNS_INT long 16 $342
N014 ( 2, 2) [000041] -------N---- | | | | \--* ADD long $242
N012 ( 1, 1) [000035] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:3 $141
N018 ( 19, 21) [000044] ---XG------- | | \--* ADD int $205
N010 ( 6, 7) [000165] ---XG------- | | | /--* CAST int <- long $202
N009 ( 5, 5) [000033] ---XG------- | | | | \--* HWIntrinsic long PopCount $301
N008 ( 4, 4) [000032] *--XG------- | | | | \--* IND long <l:$143, c:$2c1>
N006 ( 1, 1) [000030] ------------ | | | | | /--* CNS_INT long 8 $340
N007 ( 2, 2) [000031] -------N---- | | | | \--* ADD long $241
N005 ( 1, 1) [000028] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:3 $141
N011 ( 12, 13) [000034] ---XG------- | | \--* ADD int $203
N004 ( 5, 5) [000164] ---XG------- | | \--* CAST int <- long $201
N003 ( 4, 3) [000027] ---XG------- | | \--* HWIntrinsic long PopCount $300
N002 ( 3, 2) [000026] *--XG------- | | \--* IND long <l:$142, c:$2c0>
N001 ( 1, 1) [000025] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N027 ( 28, 31) [000056] ---XG---R--- | /--* SUB int $208
N026 ( 1, 1) [000024] ------------ | | \--* LCL_VAR int V04 tmp3 u:3 (last use) $280
N029 ( 28, 31) [000059] -A-XG---R--- \--* ASG int $208
N028 ( 1, 1) [000058] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $208
***** BB02, stmt 8
( 3, 3) [000070] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000066] ------------ | /--* CNS_INT long 32 $344
N003 ( 3, 3) [000067] ------------ | /--* ADD long $244
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000069] -A------R--- \--* ASG long $244
N004 ( 1, 1) [000068] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $244
***** BB02, stmt 9
( 5, 8) [000022] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000021] ------------ \--* JTRUE void
N002 ( 1, 4) [000019] ------------ | /--* CNS_INT int 256 $43
N003 ( 3, 6) [000020] J------N---- \--* GE int $209
N001 ( 1, 1) [000018] ------------ \--* LCL_VAR int V04 tmp3 u:4 $208
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 10
( 2, 3) [000205] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000203] ------------ | * PHI long
N001 ( 0, 0) [000218] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000204] -A------R--- \--* ASG long
N006 ( 1, 1) [000202] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 11
( 2, 3) [000197] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000195] ------------ | * PHI int
N001 ( 0, 0) [000220] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000196] -A------R--- \--* ASG int
N006 ( 1, 1) [000194] D------N---- \--* LCL_VAR int V04 tmp3 d:5
***** BB03, stmt 12
( 1, 3) [000075] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000072] ------------ | /--* LCL_VAR int V04 tmp3 u:5 $281
N003 ( 1, 3) [000074] -A------R--- \--* ASG int $281
N002 ( 1, 1) [000073] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $281
***** BB03, stmt 13
( 5, 5) [000177] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000176] ------------ \--* JTRUE void
N002 ( 1, 1) [000175] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000173] J------N---- \--* LE int $20a
N001 ( 1, 1) [000174] ------------ \--* LCL_VAR int V05 tmp4 u:2 $281
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
***** BB04, stmt 14
( 2, 3) [000189] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000187] ------------ | * PHI long
N001 ( 0, 0) [000238] ------------ | /--* PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ | \--* PHI_ARG long V03 tmp2 u:5 $146
N007 ( 2, 3) [000188] -A------R--- \--* ASG long
N006 ( 1, 1) [000186] D------N---- \--* LCL_VAR long V03 tmp2 d:6
***** BB04, stmt 15
( 2, 3) [000181] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000179] ------------ | * PHI int
N001 ( 0, 0) [000240] ------------ | /--* PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ | \--* PHI_ARG int V04 tmp3 u:5 $281
N007 ( 2, 3) [000180] -A------R--- \--* ASG int
N006 ( 1, 1) [000178] D------N---- \--* LCL_VAR int V04 tmp3 d:6
***** BB04, stmt 16
( 1, 3) [000086] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000083] ------------ | /--* LCL_VAR int V04 tmp3 u:6 $282
N003 ( 1, 3) [000085] -A------R--- \--* ASG int $282
N002 ( 1, 1) [000084] D------N---- \--* LCL_VAR int V05 tmp4 d:3 $282
***** BB04, stmt 17
( 7, 7) [000096] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000091] ---XG------- | /--* CAST int <- long $20b
N004 ( 4, 3) [000090] ---XG------- | | \--* HWIntrinsic long PopCount $440
N003 ( 3, 2) [000089] *--XG------- | | \--* IND long <l:$148, c:$400>
N002 ( 1, 1) [000088] ------------ | | \--* LCL_VAR long V03 tmp2 u:6 $147
N006 ( 7, 7) [000092] ---XG------- | /--* SUB int $20c
N001 ( 1, 1) [000087] ------------ | | \--* LCL_VAR int V05 tmp4 u:3 (last use) $282
N008 ( 7, 7) [000095] -A-XG---R--- \--* ASG int $20c
N007 ( 1, 1) [000094] D------N---- \--* LCL_VAR int V04 tmp3 d:7 $20c
***** BB04, stmt 18
( 3, 3) [000103] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000099] ------------ | /--* CNS_INT long 8 $340
N003 ( 3, 3) [000100] ------------ | /--* ADD long $246
N001 ( 1, 1) [000097] ------------ | | \--* LCL_VAR long V03 tmp2 u:6 (last use) $147
N005 ( 3, 3) [000102] -A------R--- \--* ASG long $246
N004 ( 1, 1) [000101] D------N---- \--* LCL_VAR long V03 tmp2 d:7 $246
***** BB04, stmt 19
( 5, 5) [000081] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000080] ------------ \--* JTRUE void
N002 ( 1, 1) [000078] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000079] J------N---- \--* GT int $20d
N001 ( 1, 1) [000077] ------------ \--* LCL_VAR int V04 tmp3 u:7 $20c
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 20
( 2, 3) [000193] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000191] ------------ | * PHI int
N001 ( 0, 0) [000234] ------------ | /--* PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ | \--* PHI_ARG int V05 tmp4 u:2 $281
N007 ( 2, 3) [000192] -A------R--- \--* ASG int
N006 ( 1, 1) [000190] D------N---- \--* LCL_VAR int V05 tmp4 d:4
***** BB05, stmt 21
( 2, 3) [000185] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000183] ------------ | * PHI long
N001 ( 0, 0) [000236] ------------ | /--* PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ | \--* PHI_ARG long V03 tmp2 u:5 $146
N007 ( 2, 3) [000184] -A------R--- \--* ASG long
N006 ( 1, 1) [000182] D------N---- \--* LCL_VAR long V03 tmp2 d:8
***** BB05, stmt 22
( 3, 3) [000111] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000107] ------------ | /--* CNS_INT long -8 $345
N003 ( 3, 3) [000108] ------------ | /--* ADD long $247
N001 ( 1, 1) [000105] ------------ | | \--* LCL_VAR long V03 tmp2 u:8 (last use) $149
N005 ( 3, 3) [000110] -A------R--- \--* ASG long $247
N004 ( 1, 1) [000109] D------N---- \--* LCL_VAR long V03 tmp2 d:9 $247
***** BB05, stmt 23
( 16, 13) [000127] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000124] ---XG------- | /--* CAST int <- long $211
N011 ( 15, 11) [000123] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount $481
N009 ( 3, 2) [000121] *--XG------- | | | /--* IND long <l:$14a, c:$184>
N008 ( 1, 1) [000120] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:9 $247
N010 ( 14, 10) [000122] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit $480
N004 ( 1, 1) [000117] ------------ | | | /--* CNS_INT int 63 $4a
N005 ( 5, 5) [000118] ------------ | | | /--* AND int $210
N002 ( 1, 1) [000115] ------------ | | | | | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000116] ------------ | | | | \--* ADD int $20f
N001 ( 1, 1) [000114] ------------ | | | | \--* LCL_VAR int V05 tmp4 u:4 (last use) $283
N007 ( 10, 7) [000119] --------R--- | | \--* LSH long $248
N006 ( 1, 1) [000113] ------------ | | \--* CNS_INT long 1 $346
N014 ( 16, 13) [000126] -A-XG---R--- \--* ASG int $211
N013 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V06 tmp5 d:2 $211
***** BB05, stmt 24
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int $1c3
N009 ( 1, 1) [000138] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use) $211
N010 ( 29, 13) [000139] ------------ \--* ADD int <l:$216, c:$217>
N007 ( 1, 1) [000135] ------------ | /--* CNS_INT int 6 $4b
N008 ( 27, 11) [000136] ------------ \--* LSH int <l:$214, c:$215>
N006 ( 25, 9) [000166] ------------ \--* CAST int <- long <l:$212, c:$213>
N004 ( 1, 1) [000132] ------------ | /--* CNS_INT long 8 $340
N005 ( 24, 7) [000133] ------------ \--* DIV long <l:$24b, c:$24c>
N002 ( 1, 1) [000129] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000130] ------------ \--* SUB long <l:$249, c:$24a>
N001 ( 1, 1) [000128] ------------ \--* LCL_VAR long V03 tmp2 u:9 (last use) $247
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000142] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000159] ------------ | | \--* CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
N004 ( 5, 12) [000141] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000140] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000145] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000144] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000143] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
***** BB01, stmt 4
( 5, 8) [000172] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000171] ------------ \--* JTRUE void
N002 ( 1, 4) [000170] ------------ | /--* CNS_INT int 256 $43
N003 ( 3, 6) [000168] J------N---- \--* LT int $200
N001 ( 1, 1) [000169] ------------ \--* LCL_VAR int V04 tmp3 u:2 $80
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 5
( 2, 3) [000209] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000207] ------------ | * PHI long
N001 ( 0, 0) [000222] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000208] -A------R--- \--* ASG long
N006 ( 1, 1) [000206] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 6
( 2, 3) [000201] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000199] ------------ | * PHI int
N001 ( 0, 0) [000224] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000200] -A------R--- \--* ASG int
N006 ( 1, 1) [000198] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 7
( 28, 31) [000060] ------------ * STMT void (IL 0x000... ???)
N024 ( 6, 7) [000161] ---XG------- | /--* CAST int <- long $206
N023 ( 5, 5) [000053] ---XG------- | | \--* HWIntrinsic long PopCount $303
N022 ( 4, 4) [000052] *--XG------- | | \--* IND long <l:$145, c:$2c3>
N020 ( 1, 1) [000050] ------------ | | | /--* CNS_INT long 24 $343
N021 ( 2, 2) [000051] -------N---- | | \--* ADD long $243
N019 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N025 ( 26, 29) [000054] ---XG------- | /--* ADD int $207
N017 ( 6, 7) [000163] ---XG------- | | | /--* CAST int <- long $204
N016 ( 5, 5) [000043] ---XG------- | | | | \--* HWIntrinsic long PopCount $302
N015 ( 4, 4) [000042] *--XG------- | | | | \--* IND long <l:$144, c:$2c2>
N013 ( 1, 1) [000040] ------------ | | | | | /--* CNS_INT long 16 $342
N014 ( 2, 2) [000041] -------N---- | | | | \--* ADD long $242
N012 ( 1, 1) [000035] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:3 $141
N018 ( 19, 21) [000044] ---XG------- | | \--* ADD int $205
N010 ( 6, 7) [000165] ---XG------- | | | /--* CAST int <- long $202
N009 ( 5, 5) [000033] ---XG------- | | | | \--* HWIntrinsic long PopCount $301
N008 ( 4, 4) [000032] *--XG------- | | | | \--* IND long <l:$143, c:$2c1>
N006 ( 1, 1) [000030] ------------ | | | | | /--* CNS_INT long 8 $340
N007 ( 2, 2) [000031] -------N---- | | | | \--* ADD long $241
N005 ( 1, 1) [000028] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:3 $141
N011 ( 12, 13) [000034] ---XG------- | | \--* ADD int $203
N004 ( 5, 5) [000164] ---XG------- | | \--* CAST int <- long $201
N003 ( 4, 3) [000027] ---XG------- | | \--* HWIntrinsic long PopCount $300
N002 ( 3, 2) [000026] *--XG------- | | \--* IND long <l:$142, c:$2c0>
N001 ( 1, 1) [000025] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N027 ( 28, 31) [000056] ---XG---R--- | /--* SUB int $208
N026 ( 1, 1) [000024] ------------ | | \--* LCL_VAR int V04 tmp3 u:3 (last use) $280
N029 ( 28, 31) [000059] -A-XG---R--- \--* ASG int $208
N028 ( 1, 1) [000058] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $208
***** BB02, stmt 8
( 3, 3) [000070] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000066] ------------ | /--* CNS_INT long 32 $344
N003 ( 3, 3) [000067] ------------ | /--* ADD long $244
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000069] -A------R--- \--* ASG long $244
N004 ( 1, 1) [000068] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $244
***** BB02, stmt 9
( 5, 8) [000022] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 8) [000021] ------------ \--* JTRUE void
N002 ( 1, 4) [000019] ------------ | /--* CNS_INT int 256 $43
N003 ( 3, 6) [000020] J------N---- \--* GE int $209
N001 ( 1, 1) [000018] ------------ \--* LCL_VAR int V04 tmp3 u:4 $208
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 10
( 2, 3) [000205] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000203] ------------ | * PHI long
N001 ( 0, 0) [000218] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000204] -A------R--- \--* ASG long
N006 ( 1, 1) [000202] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 11
( 2, 3) [000197] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000195] ------------ | * PHI int
N001 ( 0, 0) [000220] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000196] -A------R--- \--* ASG int
N006 ( 1, 1) [000194] D------N---- \--* LCL_VAR int V04 tmp3 d:5
***** BB03, stmt 12
( 1, 3) [000075] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000072] ------------ | /--* LCL_VAR int V04 tmp3 u:5 $281
N003 ( 1, 3) [000074] -A------R--- \--* ASG int $281
N002 ( 1, 1) [000073] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $281
***** BB03, stmt 13
( 5, 5) [000177] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000176] ------------ \--* JTRUE void
N002 ( 1, 1) [000175] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000173] J------N---- \--* LE int $20a
N001 ( 1, 1) [000174] ------------ \--* LCL_VAR int V05 tmp4 u:2 $281
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
***** BB04, stmt 14
( 2, 3) [000189] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000187] ------------ | * PHI long
N001 ( 0, 0) [000238] ------------ | /--* PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ | \--* PHI_ARG long V03 tmp2 u:5 $146
N007 ( 2, 3) [000188] -A------R--- \--* ASG long
N006 ( 1, 1) [000186] D------N---- \--* LCL_VAR long V03 tmp2 d:6
***** BB04, stmt 15
( 2, 3) [000181] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000179] ------------ | * PHI int
N001 ( 0, 0) [000240] ------------ | /--* PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ | \--* PHI_ARG int V04 tmp3 u:5 $281
N007 ( 2, 3) [000180] -A------R--- \--* ASG int
N006 ( 1, 1) [000178] D------N---- \--* LCL_VAR int V04 tmp3 d:6
***** BB04, stmt 16
( 1, 3) [000086] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000083] ------------ | /--* LCL_VAR int V04 tmp3 u:6 $282
N003 ( 1, 3) [000085] -A------R--- \--* ASG int $282
N002 ( 1, 1) [000084] D------N---- \--* LCL_VAR int V05 tmp4 d:3 $282
***** BB04, stmt 17
( 7, 7) [000096] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000091] ---XG------- | /--* CAST int <- long $20b
N004 ( 4, 3) [000090] ---XG------- | | \--* HWIntrinsic long PopCount $440
N003 ( 3, 2) [000089] *--XG------- | | \--* IND long <l:$148, c:$400>
N002 ( 1, 1) [000088] ------------ | | \--* LCL_VAR long V03 tmp2 u:6 $147
N006 ( 7, 7) [000092] ---XG------- | /--* SUB int $20c
N001 ( 1, 1) [000087] ------------ | | \--* LCL_VAR int V05 tmp4 u:3 (last use) $282
N008 ( 7, 7) [000095] -A-XG---R--- \--* ASG int $20c
N007 ( 1, 1) [000094] D------N---- \--* LCL_VAR int V04 tmp3 d:7 $20c
***** BB04, stmt 18
( 3, 3) [000103] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000099] ------------ | /--* CNS_INT long 8 $340
N003 ( 3, 3) [000100] ------------ | /--* ADD long $246
N001 ( 1, 1) [000097] ------------ | | \--* LCL_VAR long V03 tmp2 u:6 (last use) $147
N005 ( 3, 3) [000102] -A------R--- \--* ASG long $246
N004 ( 1, 1) [000101] D------N---- \--* LCL_VAR long V03 tmp2 d:7 $246
***** BB04, stmt 19
( 5, 5) [000081] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000080] ------------ \--* JTRUE void
N002 ( 1, 1) [000078] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000079] J------N---- \--* GT int $20d
N001 ( 1, 1) [000077] ------------ \--* LCL_VAR int V04 tmp3 u:7 $20c
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 20
( 2, 3) [000193] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000191] ------------ | * PHI int
N001 ( 0, 0) [000234] ------------ | /--* PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ | \--* PHI_ARG int V05 tmp4 u:2 $281
N007 ( 2, 3) [000192] -A------R--- \--* ASG int
N006 ( 1, 1) [000190] D------N---- \--* LCL_VAR int V05 tmp4 d:4
***** BB05, stmt 21
( 2, 3) [000185] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000183] ------------ | * PHI long
N001 ( 0, 0) [000236] ------------ | /--* PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ | \--* PHI_ARG long V03 tmp2 u:5 $146
N007 ( 2, 3) [000184] -A------R--- \--* ASG long
N006 ( 1, 1) [000182] D------N---- \--* LCL_VAR long V03 tmp2 d:8
***** BB05, stmt 22
( 3, 3) [000111] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000107] ------------ | /--* CNS_INT long -8 $345
N003 ( 3, 3) [000108] ------------ | /--* ADD long $247
N001 ( 1, 1) [000105] ------------ | | \--* LCL_VAR long V03 tmp2 u:8 (last use) $149
N005 ( 3, 3) [000110] -A------R--- \--* ASG long $247
N004 ( 1, 1) [000109] D------N---- \--* LCL_VAR long V03 tmp2 d:9 $247
***** BB05, stmt 23
( 16, 13) [000127] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000124] ---XG------- | /--* CAST int <- long $211
N011 ( 15, 11) [000123] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount $481
N009 ( 3, 2) [000121] *--XG------- | | | /--* IND long <l:$14a, c:$184>
N008 ( 1, 1) [000120] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:9 $247
N010 ( 14, 10) [000122] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit $480
N004 ( 1, 1) [000117] ------------ | | | /--* CNS_INT int 63 $4a
N005 ( 5, 5) [000118] ------------ | | | /--* AND int $210
N002 ( 1, 1) [000115] ------------ | | | | | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000116] ------------ | | | | \--* ADD int $20f
N001 ( 1, 1) [000114] ------------ | | | | \--* LCL_VAR int V05 tmp4 u:4 (last use) $283
N007 ( 10, 7) [000119] --------R--- | | \--* LSH long $248
N006 ( 1, 1) [000113] ------------ | | \--* CNS_INT long 1 $346
N014 ( 16, 13) [000126] -A-XG---R--- \--* ASG int $211
N013 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V06 tmp5 d:2 $211
***** BB05, stmt 24
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int $1c3
N009 ( 1, 1) [000138] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use) $211
N010 ( 29, 13) [000139] ------------ \--* ADD int <l:$216, c:$217>
N007 ( 1, 1) [000135] ------------ | /--* CNS_INT int 6 $4b
N008 ( 27, 11) [000136] ------------ \--* LSH int <l:$214, c:$215>
N006 ( 25, 9) [000166] ------------ \--* CAST int <- long <l:$212, c:$213>
N004 ( 1, 1) [000132] ------------ | /--* CNS_INT long 8 $340
N005 ( 24, 7) [000133] ------------ \--* DIV long <l:$24b, c:$24c>
N002 ( 1, 1) [000129] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000130] ------------ \--* SUB long <l:$249, c:$24a>
N001 ( 1, 1) [000128] ------------ \--* LCL_VAR long V03 tmp2 u:9 (last use) $247
-------------------------------------------------------------------------------------------------------------------
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 5, 12) [000141] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000144] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000208] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000200] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N029 ( 28, 31) [000059] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 3, 3) [000069] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000204] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000196] DA---------- * STORE_LCL_VAR int V04 tmp3 d:5
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000074] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000188] DA---------- * STORE_LCL_VAR long V03 tmp2 d:6
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000180] DA---------- * STORE_LCL_VAR int V04 tmp3 d:6
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000085] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N008 ( 7, 7) [000095] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:7
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 3, 3) [000102] DA---------- * STORE_LCL_VAR long V03 tmp2 d:7
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000192] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000184] DA---------- * STORE_LCL_VAR long V03 tmp2 d:8
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 3, 3) [000110] DA---------- * STORE_LCL_VAR long V03 tmp2 d:9
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N014 ( 16, 13) [000126] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2
*************** Exiting IR Rationalize
Trees after IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd LIR
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000142] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000159] ------------ t159 = CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
/--* t159 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000141] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000145] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000144] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 5, 8) [000172] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000169] ------------ t169 = LCL_VAR int V04 tmp3 u:2 $80
N002 ( 1, 4) [000170] ------------ t170 = CNS_INT int 256 $43
/--* t169 int
+--* t170 int
N003 ( 3, 6) [000168] J------N---- t168 = * LT int $200
/--* t168 int
N004 ( 5, 8) [000171] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000222] ------------ t222 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ t210 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t222 long
+--* t210 long
N005 ( 2, 2) [000207] ------------ t207 = * PHI long
/--* t207 long
N007 ( 2, 3) [000208] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000224] ------------ t224 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ t212 = PHI_ARG int V04 tmp3 u:2 $80
/--* t224 int
+--* t212 int
N005 ( 2, 2) [000199] ------------ t199 = * PHI int
/--* t199 int
N007 ( 2, 3) [000200] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 28, 31) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V03 tmp2 u:3 $141
/--* t25 long
N002 ( 3, 2) [000026] *--XG------- t26 = * IND long <l:$142, c:$2c0>
/--* t26 long
N003 ( 4, 3) [000027] ---XG------- t27 = * HWIntrinsic long PopCount $300
/--* t27 long
N004 ( 5, 5) [000164] ---XG------- t164 = * CAST int <- long $201
N005 ( 1, 1) [000028] ------------ t28 = LCL_VAR long V03 tmp2 u:3 $141
N006 ( 1, 1) [000030] ------------ t30 = CNS_INT long 8 $340
/--* t28 long
+--* t30 long
N007 ( 2, 2) [000031] -------N---- t31 = * ADD long $241
/--* t31 long
N008 ( 4, 4) [000032] *--XG------- t32 = * IND long <l:$143, c:$2c1>
/--* t32 long
N009 ( 5, 5) [000033] ---XG------- t33 = * HWIntrinsic long PopCount $301
/--* t33 long
N010 ( 6, 7) [000165] ---XG------- t165 = * CAST int <- long $202
/--* t164 int
+--* t165 int
N011 ( 12, 13) [000034] ---XG------- t34 = * ADD int $203
N012 ( 1, 1) [000035] ------------ t35 = LCL_VAR long V03 tmp2 u:3 $141
N013 ( 1, 1) [000040] ------------ t40 = CNS_INT long 16 $342
/--* t35 long
+--* t40 long
N014 ( 2, 2) [000041] -------N---- t41 = * ADD long $242
/--* t41 long
N015 ( 4, 4) [000042] *--XG------- t42 = * IND long <l:$144, c:$2c2>
/--* t42 long
N016 ( 5, 5) [000043] ---XG------- t43 = * HWIntrinsic long PopCount $302
/--* t43 long
N017 ( 6, 7) [000163] ---XG------- t163 = * CAST int <- long $204
/--* t34 int
+--* t163 int
N018 ( 19, 21) [000044] ---XG------- t44 = * ADD int $205
N019 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V03 tmp2 u:3 $141
N020 ( 1, 1) [000050] ------------ t50 = CNS_INT long 24 $343
/--* t45 long
+--* t50 long
N021 ( 2, 2) [000051] -------N---- t51 = * ADD long $243
/--* t51 long
N022 ( 4, 4) [000052] *--XG------- t52 = * IND long <l:$145, c:$2c3>
/--* t52 long
N023 ( 5, 5) [000053] ---XG------- t53 = * HWIntrinsic long PopCount $303
/--* t53 long
N024 ( 6, 7) [000161] ---XG------- t161 = * CAST int <- long $206
/--* t44 int
+--* t161 int
N025 ( 26, 29) [000054] ---XG------- t54 = * ADD int $207
N026 ( 1, 1) [000024] ------------ t24 = LCL_VAR int V04 tmp3 u:3 (last use) $280
/--* t24 int
+--* t54 int
N027 ( 28, 31) [000056] ---XG------- t56 = * SUB int $208
/--* t56 int
N029 ( 28, 31) [000059] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 3, 3) [000070] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR long V03 tmp2 u:3 (last use) $141
N002 ( 1, 1) [000066] ------------ t66 = CNS_INT long 32 $344
/--* t61 long
+--* t66 long
N003 ( 3, 3) [000067] ------------ t67 = * ADD long $244
/--* t67 long
N005 ( 3, 3) [000069] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 5, 8) [000022] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR int V04 tmp3 u:4 $208
N002 ( 1, 4) [000019] ------------ t19 = CNS_INT int 256 $43
/--* t18 int
+--* t19 int
N003 ( 3, 6) [000020] J------N---- t20 = * GE int $209
/--* t20 int
N004 ( 5, 8) [000021] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000218] ------------ t218 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ t214 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t218 long
+--* t214 long
N005 ( 2, 2) [000203] ------------ t203 = * PHI long
/--* t203 long
N007 ( 2, 3) [000204] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000220] ------------ t220 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ t216 = PHI_ARG int V04 tmp3 u:2 $80
/--* t220 int
+--* t216 int
N005 ( 2, 2) [000195] ------------ t195 = * PHI int
/--* t195 int
N007 ( 2, 3) [000196] DA---------- * STORE_LCL_VAR int V04 tmp3 d:5
( 1, 3) [000075] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR int V04 tmp3 u:5 $281
/--* t72 int
N003 ( 1, 3) [000074] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V05 tmp4 u:2 $281
N002 ( 1, 1) [000175] ------------ t175 = CNS_INT int 0 $40
/--* t174 int
+--* t175 int
N003 ( 3, 3) [000173] J------N---- t173 = * LE int $20a
/--* t173 int
N004 ( 5, 5) [000176] ------------ * JTRUE void
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
N001 ( 0, 0) [000238] ------------ t238 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ t226 = PHI_ARG long V03 tmp2 u:5 $146
/--* t238 long
+--* t226 long
N005 ( 2, 2) [000187] ------------ t187 = * PHI long
/--* t187 long
N007 ( 2, 3) [000188] DA---------- * STORE_LCL_VAR long V03 tmp2 d:6
N001 ( 0, 0) [000240] ------------ t240 = PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ t228 = PHI_ARG int V04 tmp3 u:5 $281
/--* t240 int
+--* t228 int
N005 ( 2, 2) [000179] ------------ t179 = * PHI int
/--* t179 int
N007 ( 2, 3) [000180] DA---------- * STORE_LCL_VAR int V04 tmp3 d:6
( 1, 3) [000086] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V04 tmp3 u:6 $282
/--* t83 int
N003 ( 1, 3) [000085] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 7, 7) [000096] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V05 tmp4 u:3 (last use) $282
N002 ( 1, 1) [000088] ------------ t88 = LCL_VAR long V03 tmp2 u:6 $147
/--* t88 long
N003 ( 3, 2) [000089] *--XG------- t89 = * IND long <l:$148, c:$400>
/--* t89 long
N004 ( 4, 3) [000090] ---XG------- t90 = * HWIntrinsic long PopCount $440
/--* t90 long
N005 ( 5, 5) [000091] ---XG------- t91 = * CAST int <- long $20b
/--* t87 int
+--* t91 int
N006 ( 7, 7) [000092] ---XG------- t92 = * SUB int $20c
/--* t92 int
N008 ( 7, 7) [000095] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:7
( 3, 3) [000103] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000097] ------------ t97 = LCL_VAR long V03 tmp2 u:6 (last use) $147
N002 ( 1, 1) [000099] ------------ t99 = CNS_INT long 8 $340
/--* t97 long
+--* t99 long
N003 ( 3, 3) [000100] ------------ t100 = * ADD long $246
/--* t100 long
N005 ( 3, 3) [000102] DA---------- * STORE_LCL_VAR long V03 tmp2 d:7
( 5, 5) [000081] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000077] ------------ t77 = LCL_VAR int V04 tmp3 u:7 $20c
N002 ( 1, 1) [000078] ------------ t78 = CNS_INT int 0 $40
/--* t77 int
+--* t78 int
N003 ( 3, 3) [000079] J------N---- t79 = * GT int $20d
/--* t79 int
N004 ( 5, 5) [000080] ------------ * JTRUE void
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
N001 ( 0, 0) [000234] ------------ t234 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ t230 = PHI_ARG int V05 tmp4 u:2 $281
/--* t234 int
+--* t230 int
N005 ( 2, 2) [000191] ------------ t191 = * PHI int
/--* t191 int
N007 ( 2, 3) [000192] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
N001 ( 0, 0) [000236] ------------ t236 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ t232 = PHI_ARG long V03 tmp2 u:5 $146
/--* t236 long
+--* t232 long
N005 ( 2, 2) [000183] ------------ t183 = * PHI long
/--* t183 long
N007 ( 2, 3) [000184] DA---------- * STORE_LCL_VAR long V03 tmp2 d:8
( 3, 3) [000111] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000105] ------------ t105 = LCL_VAR long V03 tmp2 u:8 (last use) $149
N002 ( 1, 1) [000107] ------------ t107 = CNS_INT long -8 $345
/--* t105 long
+--* t107 long
N003 ( 3, 3) [000108] ------------ t108 = * ADD long $247
/--* t108 long
N005 ( 3, 3) [000110] DA---------- * STORE_LCL_VAR long V03 tmp2 d:9
( 16, 13) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:4 (last use) $283
N002 ( 1, 1) [000115] ------------ t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20f
N004 ( 1, 1) [000117] ------------ t117 = CNS_INT int 63 $4a
/--* t116 int
+--* t117 int
N005 ( 5, 5) [000118] ------------ t118 = * AND int $210
N006 ( 1, 1) [000113] ------------ t113 = CNS_INT long 1 $346
/--* t113 long
+--* t118 int
N007 ( 10, 7) [000119] ------------ t119 = * LSH long $248
N008 ( 1, 1) [000120] ------------ t120 = LCL_VAR long V03 tmp2 u:9 $247
/--* t120 long
N009 ( 3, 2) [000121] *--XG------- t121 = * IND long <l:$14a, c:$184>
/--* t119 long
+--* t121 long
N010 ( 14, 10) [000122] ---XG------- t122 = * HWIntrinsic long ParallelBitDeposit $480
/--* t122 long
N011 ( 15, 11) [000123] ---XG------- t123 = * HWIntrinsic long TrailingZeroCount $481
/--* t123 long
N012 ( 16, 13) [000124] ---XG------- t124 = * CAST int <- long $211
/--* t124 int
N014 ( 16, 13) [000126] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2
N001 ( 1, 1) [000128] ------------ t128 = LCL_VAR long V03 tmp2 u:9 (last use) $247
N002 ( 1, 1) [000129] ------------ t129 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t128 long
+--* t129 long
N003 ( 3, 3) [000130] ------------ t130 = * SUB long <l:$249, c:$24a>
N004 ( 1, 1) [000132] ------------ t132 = CNS_INT long 8 $340
/--* t130 long
+--* t132 long
N005 ( 24, 7) [000133] ------------ t133 = * DIV long <l:$24b, c:$24c>
/--* t133 long
N006 ( 25, 9) [000166] ------------ t166 = * CAST int <- long <l:$212, c:$213>
N007 ( 1, 1) [000135] ------------ t135 = CNS_INT int 6 $4b
/--* t166 int
+--* t135 int
N008 ( 27, 11) [000136] ------------ t136 = * LSH int <l:$214, c:$215>
N009 ( 1, 1) [000138] ------------ t138 = LCL_VAR int V06 tmp5 u:2 (last use) $211
/--* t136 int
+--* t138 int
N010 ( 29, 13) [000139] ------------ t139 = * ADD int <l:$216, c:$217>
/--* t139 int
N011 ( 30, 14) [000010] ------------ * RETURN int $1c3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd LIR
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000142] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000159] ------------ t159 = CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
/--* t159 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000141] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000145] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000144] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 5, 8) [000172] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000169] ------------ t169 = LCL_VAR int V04 tmp3 u:2 $80
N002 ( 1, 4) [000170] ------------ t170 = CNS_INT int 256 $43
/--* t169 int
+--* t170 int
N003 ( 3, 6) [000168] J------N---- t168 = * LT int $200
/--* t168 int
N004 ( 5, 8) [000171] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000222] ------------ t222 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ t210 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t222 long
+--* t210 long
N005 ( 2, 2) [000207] ------------ t207 = * PHI long
/--* t207 long
N007 ( 2, 3) [000208] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000224] ------------ t224 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ t212 = PHI_ARG int V04 tmp3 u:2 $80
/--* t224 int
+--* t212 int
N005 ( 2, 2) [000199] ------------ t199 = * PHI int
/--* t199 int
N007 ( 2, 3) [000200] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 28, 31) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V03 tmp2 u:3 $141
/--* t25 long
N002 ( 3, 2) [000026] *--XG------- t26 = * IND long <l:$142, c:$2c0>
/--* t26 long
N003 ( 4, 3) [000027] ---XG------- t27 = * HWIntrinsic long PopCount $300
/--* t27 long
N004 ( 5, 5) [000164] ---XG------- t164 = * CAST int <- long $201
N005 ( 1, 1) [000028] ------------ t28 = LCL_VAR long V03 tmp2 u:3 $141
N006 ( 1, 1) [000030] ------------ t30 = CNS_INT long 8 $340
/--* t28 long
+--* t30 long
N007 ( 2, 2) [000031] -------N---- t31 = * ADD long $241
/--* t31 long
N008 ( 4, 4) [000032] *--XG------- t32 = * IND long <l:$143, c:$2c1>
/--* t32 long
N009 ( 5, 5) [000033] ---XG------- t33 = * HWIntrinsic long PopCount $301
/--* t33 long
N010 ( 6, 7) [000165] ---XG------- t165 = * CAST int <- long $202
/--* t164 int
+--* t165 int
N011 ( 12, 13) [000034] ---XG------- t34 = * ADD int $203
N012 ( 1, 1) [000035] ------------ t35 = LCL_VAR long V03 tmp2 u:3 $141
N013 ( 1, 1) [000040] ------------ t40 = CNS_INT long 16 $342
/--* t35 long
+--* t40 long
N014 ( 2, 2) [000041] -------N---- t41 = * ADD long $242
/--* t41 long
N015 ( 4, 4) [000042] *--XG------- t42 = * IND long <l:$144, c:$2c2>
/--* t42 long
N016 ( 5, 5) [000043] ---XG------- t43 = * HWIntrinsic long PopCount $302
/--* t43 long
N017 ( 6, 7) [000163] ---XG------- t163 = * CAST int <- long $204
/--* t34 int
+--* t163 int
N018 ( 19, 21) [000044] ---XG------- t44 = * ADD int $205
N019 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V03 tmp2 u:3 $141
N020 ( 1, 1) [000050] ------------ t50 = CNS_INT long 24 $343
/--* t45 long
+--* t50 long
N021 ( 2, 2) [000051] -------N---- t51 = * ADD long $243
/--* t51 long
N022 ( 4, 4) [000052] *--XG------- t52 = * IND long <l:$145, c:$2c3>
/--* t52 long
N023 ( 5, 5) [000053] ---XG------- t53 = * HWIntrinsic long PopCount $303
/--* t53 long
N024 ( 6, 7) [000161] ---XG------- t161 = * CAST int <- long $206
/--* t44 int
+--* t161 int
N025 ( 26, 29) [000054] ---XG------- t54 = * ADD int $207
N026 ( 1, 1) [000024] ------------ t24 = LCL_VAR int V04 tmp3 u:3 (last use) $280
/--* t24 int
+--* t54 int
N027 ( 28, 31) [000056] ---XG------- t56 = * SUB int $208
/--* t56 int
N029 ( 28, 31) [000059] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 3, 3) [000070] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR long V03 tmp2 u:3 (last use) $141
N002 ( 1, 1) [000066] ------------ t66 = CNS_INT long 32 $344
/--* t61 long
+--* t66 long
N003 ( 3, 3) [000067] ------------ t67 = * ADD long $244
/--* t67 long
N005 ( 3, 3) [000069] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 5, 8) [000022] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR int V04 tmp3 u:4 $208
N002 ( 1, 4) [000019] ------------ t19 = CNS_INT int 256 $43
/--* t18 int
+--* t19 int
N003 ( 3, 6) [000020] J------N---- t20 = * GE int $209
/--* t20 int
N004 ( 5, 8) [000021] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000218] ------------ t218 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ t214 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t218 long
+--* t214 long
N005 ( 2, 2) [000203] ------------ t203 = * PHI long
/--* t203 long
N007 ( 2, 3) [000204] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000220] ------------ t220 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ t216 = PHI_ARG int V04 tmp3 u:2 $80
/--* t220 int
+--* t216 int
N005 ( 2, 2) [000195] ------------ t195 = * PHI int
/--* t195 int
N007 ( 2, 3) [000196] DA---------- * STORE_LCL_VAR int V04 tmp3 d:5
( 1, 3) [000075] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR int V04 tmp3 u:5 $281
/--* t72 int
N003 ( 1, 3) [000074] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V05 tmp4 u:2 $281
N002 ( 1, 1) [000175] ------------ t175 = CNS_INT int 0 $40
/--* t174 int
+--* t175 int
N003 ( 3, 3) [000173] J------N---- t173 = * LE int $20a
/--* t173 int
N004 ( 5, 5) [000176] ------------ * JTRUE void
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
N001 ( 0, 0) [000238] ------------ t238 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ t226 = PHI_ARG long V03 tmp2 u:5 $146
/--* t238 long
+--* t226 long
N005 ( 2, 2) [000187] ------------ t187 = * PHI long
/--* t187 long
N007 ( 2, 3) [000188] DA---------- * STORE_LCL_VAR long V03 tmp2 d:6
N001 ( 0, 0) [000240] ------------ t240 = PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ t228 = PHI_ARG int V04 tmp3 u:5 $281
/--* t240 int
+--* t228 int
N005 ( 2, 2) [000179] ------------ t179 = * PHI int
/--* t179 int
N007 ( 2, 3) [000180] DA---------- * STORE_LCL_VAR int V04 tmp3 d:6
( 1, 3) [000086] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V04 tmp3 u:6 $282
/--* t83 int
N003 ( 1, 3) [000085] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 7, 7) [000096] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V05 tmp4 u:3 (last use) $282
N002 ( 1, 1) [000088] ------------ t88 = LCL_VAR long V03 tmp2 u:6 $147
/--* t88 long
N003 ( 3, 2) [000089] *--XG------- t89 = * IND long <l:$148, c:$400>
/--* t89 long
N004 ( 4, 3) [000090] ---XG------- t90 = * HWIntrinsic long PopCount $440
/--* t90 long
N005 ( 5, 5) [000091] ---XG------- t91 = * CAST int <- long $20b
/--* t87 int
+--* t91 int
N006 ( 7, 7) [000092] ---XG------- t92 = * SUB int $20c
/--* t92 int
N008 ( 7, 7) [000095] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:7
( 3, 3) [000103] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000097] ------------ t97 = LCL_VAR long V03 tmp2 u:6 (last use) $147
N002 ( 1, 1) [000099] ------------ t99 = CNS_INT long 8 $340
/--* t97 long
+--* t99 long
N003 ( 3, 3) [000100] ------------ t100 = * ADD long $246
/--* t100 long
N005 ( 3, 3) [000102] DA---------- * STORE_LCL_VAR long V03 tmp2 d:7
( 5, 5) [000081] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000077] ------------ t77 = LCL_VAR int V04 tmp3 u:7 $20c
N002 ( 1, 1) [000078] ------------ t78 = CNS_INT int 0 $40
/--* t77 int
+--* t78 int
N003 ( 3, 3) [000079] J------N---- t79 = * GT int $20d
/--* t79 int
N004 ( 5, 5) [000080] ------------ * JTRUE void
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
N001 ( 0, 0) [000234] ------------ t234 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ t230 = PHI_ARG int V05 tmp4 u:2 $281
/--* t234 int
+--* t230 int
N005 ( 2, 2) [000191] ------------ t191 = * PHI int
/--* t191 int
N007 ( 2, 3) [000192] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
N001 ( 0, 0) [000236] ------------ t236 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ t232 = PHI_ARG long V03 tmp2 u:5 $146
/--* t236 long
+--* t232 long
N005 ( 2, 2) [000183] ------------ t183 = * PHI long
/--* t183 long
N007 ( 2, 3) [000184] DA---------- * STORE_LCL_VAR long V03 tmp2 d:8
( 3, 3) [000111] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000105] ------------ t105 = LCL_VAR long V03 tmp2 u:8 (last use) $149
N002 ( 1, 1) [000107] ------------ t107 = CNS_INT long -8 $345
/--* t105 long
+--* t107 long
N003 ( 3, 3) [000108] ------------ t108 = * ADD long $247
/--* t108 long
N005 ( 3, 3) [000110] DA---------- * STORE_LCL_VAR long V03 tmp2 d:9
( 16, 13) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:4 (last use) $283
N002 ( 1, 1) [000115] ------------ t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20f
N004 ( 1, 1) [000117] ------------ t117 = CNS_INT int 63 $4a
/--* t116 int
+--* t117 int
N005 ( 5, 5) [000118] ------------ t118 = * AND int $210
N006 ( 1, 1) [000113] ------------ t113 = CNS_INT long 1 $346
/--* t113 long
+--* t118 int
N007 ( 10, 7) [000119] ------------ t119 = * LSH long $248
N008 ( 1, 1) [000120] ------------ t120 = LCL_VAR long V03 tmp2 u:9 $247
/--* t120 long
N009 ( 3, 2) [000121] *--XG------- t121 = * IND long <l:$14a, c:$184>
/--* t119 long
+--* t121 long
N010 ( 14, 10) [000122] ---XG------- t122 = * HWIntrinsic long ParallelBitDeposit $480
/--* t122 long
N011 ( 15, 11) [000123] ---XG------- t123 = * HWIntrinsic long TrailingZeroCount $481
/--* t123 long
N012 ( 16, 13) [000124] ---XG------- t124 = * CAST int <- long $211
/--* t124 int
N014 ( 16, 13) [000126] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2
N001 ( 1, 1) [000128] ------------ t128 = LCL_VAR long V03 tmp2 u:9 (last use) $247
N002 ( 1, 1) [000129] ------------ t129 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t128 long
+--* t129 long
N003 ( 3, 3) [000130] ------------ t130 = * SUB long <l:$249, c:$24a>
N004 ( 1, 1) [000132] ------------ t132 = CNS_INT long 8 $340
/--* t130 long
+--* t132 long
N005 ( 24, 7) [000133] ------------ t133 = * DIV long <l:$24b, c:$24c>
/--* t133 long
N006 ( 25, 9) [000166] ------------ t166 = * CAST int <- long <l:$212, c:$213>
N007 ( 1, 1) [000135] ------------ t135 = CNS_INT int 6 $4b
/--* t166 int
+--* t135 int
N008 ( 27, 11) [000136] ------------ t136 = * LSH int <l:$214, c:$215>
N009 ( 1, 1) [000138] ------------ t138 = LCL_VAR int V06 tmp5 u:2 (last use) $211
/--* t136 int
+--* t138 int
N010 ( 29, 13) [000139] ------------ t139 = * ADD int <l:$216, c:$217>
/--* t139 int
N011 ( 30, 14) [000010] ------------ * RETURN int $1c3
-------------------------------------------------------------------------------------------------------------------
No addressing mode:
N001 ( 3, 10) [000159] ------------ * CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
No addressing mode:
N001 ( 1, 1) [000025] ------------ * LCL_VAR long V03 tmp2 u:3 $141
Addressing mode:
Base
N005 ( 1, 1) [000028] ------------ * LCL_VAR long V03 tmp2 u:3 $141
+ 8
New addressing mode node:
[000242] ------------ * LEA(b+8) long
Addressing mode:
Base
N012 ( 1, 1) [000035] ------------ * LCL_VAR long V03 tmp2 u:3 $141
+ 16
New addressing mode node:
[000243] ------------ * LEA(b+16) long
Addressing mode:
Base
N019 ( 1, 1) [000045] ------------ * LCL_VAR long V03 tmp2 u:3 $141
+ 24
New addressing mode node:
[000244] ------------ * LEA(b+24) long
No addressing mode:
N002 ( 1, 1) [000088] ------------ * LCL_VAR long V03 tmp2 u:6 $147
No addressing mode:
N008 ( 1, 1) [000120] ------------ * LCL_VAR long V03 tmp2 u:9 $247
lvaGrabTemp returning 7 (V07 rat0) called for ReplaceWithLclVar is creating a new local variable.
New refCnts for V07: refCnt = 1, refCntWtd = 2
New refCnts for V07: refCnt = 2, refCntWtd = 4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
[000246] DA---------- * STORE_LCL_VAR long V07 rat0
ReplaceWithLclVar created store :
[000246] DA---------- * STORE_LCL_VAR long V07 rat0
New refCnts for V07: refCnt = 3, refCntWtd = 6
lowering GT_RETURN
N011 ( 30, 14) [000010] ------------ * RETURN int $1c3
============Lower has completed modifying nodes.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd LIR
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000142] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000159] ------------ t159 = CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
/--* t159 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000141] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000145] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000144] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 5, 8) [000172] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000169] ------------ t169 = LCL_VAR int V04 tmp3 u:2 $80
N002 ( 1, 4) [000170] -c---------- t170 = CNS_INT int 256 $43
/--* t169 int
+--* t170 int
N003 ( 3, 6) [000168] J------N---- * LT void $200
N004 ( 5, 8) [000171] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000222] ------------ t222 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ t210 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t222 long
+--* t210 long
N005 ( 2, 2) [000207] ------------ t207 = * PHI long
/--* t207 long
N007 ( 2, 3) [000208] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000224] ------------ t224 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ t212 = PHI_ARG int V04 tmp3 u:2 $80
/--* t224 int
+--* t212 int
N005 ( 2, 2) [000199] ------------ t199 = * PHI int
/--* t199 int
N007 ( 2, 3) [000200] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 28, 31) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V03 tmp2 u:3 $141
/--* t25 long
N002 ( 3, 2) [000026] *c-XG------- t26 = * IND long <l:$142, c:$2c0>
/--* t26 long
N003 ( 4, 3) [000027] ---XG------- t27 = * HWIntrinsic long PopCount $300
/--* t27 long
N004 ( 5, 5) [000164] ---XG------- t164 = * CAST int <- long $201
N005 ( 1, 1) [000028] ------------ t28 = LCL_VAR long V03 tmp2 u:3 $141
/--* t28 long
[000242] -c---------- t242 = * LEA(b+8) long
/--* t242 long
N008 ( 4, 4) [000032] *c-XG------- t32 = * IND long <l:$143, c:$2c1>
/--* t32 long
N009 ( 5, 5) [000033] ---XG------- t33 = * HWIntrinsic long PopCount $301
/--* t33 long
N010 ( 6, 7) [000165] ---XG------- t165 = * CAST int <- long $202
/--* t164 int
+--* t165 int
N011 ( 12, 13) [000034] ---XG------- t34 = * ADD int $203
N012 ( 1, 1) [000035] ------------ t35 = LCL_VAR long V03 tmp2 u:3 $141
/--* t35 long
[000243] -c---------- t243 = * LEA(b+16) long
/--* t243 long
N015 ( 4, 4) [000042] *c-XG------- t42 = * IND long <l:$144, c:$2c2>
/--* t42 long
N016 ( 5, 5) [000043] ---XG------- t43 = * HWIntrinsic long PopCount $302
/--* t43 long
N017 ( 6, 7) [000163] ---XG------- t163 = * CAST int <- long $204
/--* t34 int
+--* t163 int
N018 ( 19, 21) [000044] ---XG------- t44 = * ADD int $205
N019 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V03 tmp2 u:3 $141
/--* t45 long
[000244] -c---------- t244 = * LEA(b+24) long
/--* t244 long
N022 ( 4, 4) [000052] *c-XG------- t52 = * IND long <l:$145, c:$2c3>
/--* t52 long
N023 ( 5, 5) [000053] ---XG------- t53 = * HWIntrinsic long PopCount $303
/--* t53 long
N024 ( 6, 7) [000161] ---XG------- t161 = * CAST int <- long $206
/--* t44 int
+--* t161 int
N025 ( 26, 29) [000054] ---XG------- t54 = * ADD int $207
N026 ( 1, 1) [000024] ------------ t24 = LCL_VAR int V04 tmp3 u:3 (last use) $280
/--* t24 int
+--* t54 int
N027 ( 28, 31) [000056] ---XG------- t56 = * SUB int $208
/--* t56 int
N029 ( 28, 31) [000059] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 3, 3) [000070] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR long V03 tmp2 u:3 (last use) $141
N002 ( 1, 1) [000066] -c---------- t66 = CNS_INT long 32 $344
/--* t61 long
+--* t66 long
N003 ( 3, 3) [000067] ------------ t67 = * ADD long $244
/--* t67 long
N005 ( 3, 3) [000069] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 5, 8) [000022] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR int V04 tmp3 u:4 $208
N002 ( 1, 4) [000019] -c---------- t19 = CNS_INT int 256 $43
/--* t18 int
+--* t19 int
N003 ( 3, 6) [000020] J------N---- * GE void $209
N004 ( 5, 8) [000021] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000218] ------------ t218 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ t214 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t218 long
+--* t214 long
N005 ( 2, 2) [000203] ------------ t203 = * PHI long
/--* t203 long
N007 ( 2, 3) [000204] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000220] ------------ t220 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ t216 = PHI_ARG int V04 tmp3 u:2 $80
/--* t220 int
+--* t216 int
N005 ( 2, 2) [000195] ------------ t195 = * PHI int
/--* t195 int
N007 ( 2, 3) [000196] DA---------- * STORE_LCL_VAR int V04 tmp3 d:5
( 1, 3) [000075] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR int V04 tmp3 u:5 $281
/--* t72 int
N003 ( 1, 3) [000074] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V05 tmp4 u:2 $281
N002 ( 1, 1) [000175] -c---------- t175 = CNS_INT int 0 $40
/--* t174 int
+--* t175 int
N003 ( 3, 3) [000173] J------N---- * LE void $20a
N004 ( 5, 5) [000176] ------------ * JTRUE void
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
N001 ( 0, 0) [000238] ------------ t238 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ t226 = PHI_ARG long V03 tmp2 u:5 $146
/--* t238 long
+--* t226 long
N005 ( 2, 2) [000187] ------------ t187 = * PHI long
/--* t187 long
N007 ( 2, 3) [000188] DA---------- * STORE_LCL_VAR long V03 tmp2 d:6
N001 ( 0, 0) [000240] ------------ t240 = PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ t228 = PHI_ARG int V04 tmp3 u:5 $281
/--* t240 int
+--* t228 int
N005 ( 2, 2) [000179] ------------ t179 = * PHI int
/--* t179 int
N007 ( 2, 3) [000180] DA---------- * STORE_LCL_VAR int V04 tmp3 d:6
( 1, 3) [000086] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V04 tmp3 u:6 $282
/--* t83 int
N003 ( 1, 3) [000085] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 7, 7) [000096] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V05 tmp4 u:3 (last use) $282
N002 ( 1, 1) [000088] ------------ t88 = LCL_VAR long V03 tmp2 u:6 $147
/--* t88 long
N003 ( 3, 2) [000089] *c-XG------- t89 = * IND long <l:$148, c:$400>
/--* t89 long
N004 ( 4, 3) [000090] ---XG------- t90 = * HWIntrinsic long PopCount $440
/--* t90 long
N005 ( 5, 5) [000091] ---XG------- t91 = * CAST int <- long $20b
/--* t87 int
+--* t91 int
N006 ( 7, 7) [000092] ---XG------- t92 = * SUB int $20c
/--* t92 int
N008 ( 7, 7) [000095] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:7
( 3, 3) [000103] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000097] ------------ t97 = LCL_VAR long V03 tmp2 u:6 (last use) $147
N002 ( 1, 1) [000099] -c---------- t99 = CNS_INT long 8 $340
/--* t97 long
+--* t99 long
N003 ( 3, 3) [000100] ------------ t100 = * ADD long $246
/--* t100 long
N005 ( 3, 3) [000102] DA---------- * STORE_LCL_VAR long V03 tmp2 d:7
( 5, 5) [000081] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000077] ------------ t77 = LCL_VAR int V04 tmp3 u:7 $20c
N002 ( 1, 1) [000078] -c---------- t78 = CNS_INT int 0 $40
/--* t77 int
+--* t78 int
N003 ( 3, 3) [000079] J------N---- * GT void $20d
N004 ( 5, 5) [000080] ------------ * JTRUE void
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
N001 ( 0, 0) [000234] ------------ t234 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ t230 = PHI_ARG int V05 tmp4 u:2 $281
/--* t234 int
+--* t230 int
N005 ( 2, 2) [000191] ------------ t191 = * PHI int
/--* t191 int
N007 ( 2, 3) [000192] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
N001 ( 0, 0) [000236] ------------ t236 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ t232 = PHI_ARG long V03 tmp2 u:5 $146
/--* t236 long
+--* t232 long
N005 ( 2, 2) [000183] ------------ t183 = * PHI long
/--* t183 long
N007 ( 2, 3) [000184] DA---------- * STORE_LCL_VAR long V03 tmp2 d:8
( 3, 3) [000111] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000105] ------------ t105 = LCL_VAR long V03 tmp2 u:8 (last use) $149
N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT long -8 $345
/--* t105 long
+--* t107 long
N003 ( 3, 3) [000108] ------------ t108 = * ADD long $247
/--* t108 long
N005 ( 3, 3) [000110] DA---------- * STORE_LCL_VAR long V03 tmp2 d:9
( 16, 13) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:4 (last use) $283
N002 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20f
N006 ( 1, 1) [000113] ------------ t113 = CNS_INT long 1 $346
/--* t113 long
+--* t116 int
N007 ( 10, 7) [000119] ------------ t119 = * LSH long $248
N008 ( 1, 1) [000120] ------------ t120 = LCL_VAR long V03 tmp2 u:9 $247
/--* t120 long
N009 ( 3, 2) [000121] *c-XG------- t121 = * IND long <l:$14a, c:$184>
/--* t119 long
+--* t121 long
N010 ( 14, 10) [000122] ---XG------- t122 = * HWIntrinsic long ParallelBitDeposit $480
/--* t122 long
N011 ( 15, 11) [000123] ---XG------- t123 = * HWIntrinsic long TrailingZeroCount $481
/--* t123 long
N012 ( 16, 13) [000124] ---XG------- t124 = * CAST int <- long $211
/--* t124 int
N014 ( 16, 13) [000126] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2
N001 ( 1, 1) [000128] ------------ t128 = LCL_VAR long V03 tmp2 u:9 (last use) $247
N002 ( 1, 1) [000129] ------------ t129 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t128 long
+--* t129 long
N003 ( 3, 3) [000130] ------------ t130 = * SUB long <l:$249, c:$24a>
/--* t130 long
[000246] DA---------- * STORE_LCL_VAR long V07 rat0
N001 ( 1, 1) [000247] ------------ t247 = LCL_VAR long V07 rat0
N002 ( 1, 1) [000248] -c---------- t248 = CNS_INT int 63
/--* t247 long
+--* t248 int
N003 ( 3, 3) [000249] ------------ t249 = * RSH long
N004 ( 1, 1) [000250] -c---------- t250 = CNS_INT long 7
/--* t249 long
+--* t250 long
N005 ( 5, 5) [000251] ------------ t251 = * AND long
N006 ( 1, 1) [000252] ------------ t252 = LCL_VAR long V07 rat0
/--* t251 long
+--* t252 long
N007 ( 7, 7) [000253] ------------ t253 = * ADD long
N008 ( 1, 1) [000132] -c---------- t132 = CNS_INT long 3 $340
/--* t253 long
+--* t132 long
N009 ( 9, 9) [000254] ------------ t254 = * RSH long
/--* t254 long
N006 ( 25, 9) [000166] ------------ t166 = * CAST int <- long <l:$212, c:$213>
N007 ( 1, 1) [000135] -c---------- t135 = CNS_INT int 6 $4b
/--* t166 int
+--* t135 int
N008 ( 27, 11) [000136] ------------ t136 = * LSH int <l:$214, c:$215>
N009 ( 1, 1) [000138] ------------ t138 = LCL_VAR int V06 tmp5 u:2 (last use) $211
/--* t136 int
+--* t138 int
N010 ( 29, 13) [000139] ------------ t139 = * ADD int <l:$216, c:$217>
/--* t139 int
N011 ( 30, 14) [000010] ------------ * RETURN int $1c3
-------------------------------------------------------------------------------------------------------------------
New refCnts for V02: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V04: refCnt = 1, refCntWtd = 2
New refCnts for V02: refCnt = 2, refCntWtd = 4
New refCnts for V03: refCnt = 1, refCntWtd = 1
New refCnts for V04: refCnt = 2, refCntWtd = 4
New refCnts for V03: refCnt = 2, refCntWtd = 3
New refCnts for V03: refCnt = 3, refCntWtd = 5
New refCnts for V03: refCnt = 4, refCntWtd = 7
New refCnts for V03: refCnt = 5, refCntWtd = 9
New refCnts for V04: refCnt = 3, refCntWtd = 8
New refCnts for V04: refCnt = 4, refCntWtd = 12
New refCnts for V03: refCnt = 6, refCntWtd = 11
New refCnts for V03: refCnt = 7, refCntWtd = 13
New refCnts for V04: refCnt = 5, refCntWtd = 16
New refCnts for V04: refCnt = 6, refCntWtd = 17
New refCnts for V05: refCnt = 1, refCntWtd = 0.50
New refCnts for V05: refCnt = 2, refCntWtd = 1
New refCnts for V04: refCnt = 7, refCntWtd = 21
New refCnts for V05: refCnt = 3, refCntWtd = 3
New refCnts for V05: refCnt = 4, refCntWtd = 5
New refCnts for V03: refCnt = 8, refCntWtd = 15
New refCnts for V04: refCnt = 8, refCntWtd = 25
New refCnts for V03: refCnt = 9, refCntWtd = 17
New refCnts for V03: refCnt = 10, refCntWtd = 19
New refCnts for V04: refCnt = 9, refCntWtd = 29
New refCnts for V03: refCnt = 11, refCntWtd = 20
New refCnts for V03: refCnt = 12, refCntWtd = 21
New refCnts for V05: refCnt = 5, refCntWtd = 6
New refCnts for V03: refCnt = 13, refCntWtd = 22
New refCnts for V06: refCnt = 1, refCntWtd = 1
New refCnts for V03: refCnt = 14, refCntWtd = 23
New refCnts for V02: refCnt = 3, refCntWtd = 6
New refCnts for V07: refCnt = 1, refCntWtd = 2
New refCnts for V07: refCnt = 2, refCntWtd = 4
New refCnts for V07: refCnt = 3, refCntWtd = 6
New refCnts for V06: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk ( 0)
; V02 tmp1 long
; V03 tmp2 long
; V04 tmp3 int
; V05 tmp4 int
; V06 tmp5 int
; V07 rat0 long
In fgLocalVarLivenessInit, sorting locals
refCnt table for 'IntrinsicsUnrolled':
V04 tmp3 [ int]: refCnt = 9, refCntWtd = 29
V03 tmp2 [ long]: refCnt = 14, refCntWtd = 23
V05 tmp4 [ int]: refCnt = 5, refCntWtd = 6
V02 tmp1 [ long]: refCnt = 3, refCntWtd = 6
V07 rat0 [ long]: refCnt = 3, refCntWtd = 6
V00 arg0 [ int]: refCnt = 3, refCntWtd = 3
V06 tmp5 [ int]: refCnt = 2, refCntWtd = 2
V01 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={ V00} + ByrefExposed + GcHeap
DEF(3)={V04 V03 V02 }
BB02 USE(2)={V04 V03} + ByrefExposed + GcHeap
DEF(2)={V04 V03}
BB03 USE(1)={V04 }
DEF(1)={ V05}
BB04 USE(2)={V04 V03 } + ByrefExposed + GcHeap
DEF(3)={V04 V03 V05}
BB05 USE(3)={V03 V05 V02 } + ByrefExposed + GcHeap
DEF(3)={V03 V07 V06}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={ V00} + ByrefExposed + GcHeap
OUT(3)={V04 V03 V02 } + ByrefExposed + GcHeap
BB02 IN (3)={V04 V03 V02} + ByrefExposed + GcHeap
OUT(3)={V04 V03 V02} + ByrefExposed + GcHeap
BB03 IN (3)={V04 V03 V02} + ByrefExposed + GcHeap
OUT(4)={V04 V03 V05 V02} + ByrefExposed + GcHeap
BB04 IN (3)={V04 V03 V02} + ByrefExposed + GcHeap
OUT(4)={V04 V03 V05 V02} + ByrefExposed + GcHeap
BB05 IN (3)={V03 V05 V02} + ByrefExposed + GcHeap
OUT(0)={ }
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd LIR
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Liveness pass finished after lowering, IR:
lvasortagain = 0
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd LIR
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000142] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000159] ------------ t159 = CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
/--* t159 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000141] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000145] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000144] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 5, 8) [000172] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000169] ------------ t169 = LCL_VAR int V04 tmp3 u:2 $80
N002 ( 1, 4) [000170] -c---------- t170 = CNS_INT int 256 $43
/--* t169 int
+--* t170 int
N003 ( 3, 6) [000168] J------N---- * LT void $200
N004 ( 5, 8) [000171] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000222] ------------ t222 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ t210 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t222 long
+--* t210 long
N005 ( 2, 2) [000207] ------------ t207 = * PHI long
/--* t207 long
N007 ( 2, 3) [000208] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000224] ------------ t224 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ t212 = PHI_ARG int V04 tmp3 u:2 $80
/--* t224 int
+--* t212 int
N005 ( 2, 2) [000199] ------------ t199 = * PHI int
/--* t199 int
N007 ( 2, 3) [000200] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 28, 31) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V03 tmp2 u:3 $141
/--* t25 long
N002 ( 3, 2) [000026] *c-XG------- t26 = * IND long <l:$142, c:$2c0>
/--* t26 long
N003 ( 4, 3) [000027] ---XG------- t27 = * HWIntrinsic long PopCount $300
/--* t27 long
N004 ( 5, 5) [000164] ---XG------- t164 = * CAST int <- long $201
N005 ( 1, 1) [000028] ------------ t28 = LCL_VAR long V03 tmp2 u:3 $141
/--* t28 long
[000242] -c---------- t242 = * LEA(b+8) long
/--* t242 long
N008 ( 4, 4) [000032] *c-XG------- t32 = * IND long <l:$143, c:$2c1>
/--* t32 long
N009 ( 5, 5) [000033] ---XG------- t33 = * HWIntrinsic long PopCount $301
/--* t33 long
N010 ( 6, 7) [000165] ---XG------- t165 = * CAST int <- long $202
/--* t164 int
+--* t165 int
N011 ( 12, 13) [000034] ---XG------- t34 = * ADD int $203
N012 ( 1, 1) [000035] ------------ t35 = LCL_VAR long V03 tmp2 u:3 $141
/--* t35 long
[000243] -c---------- t243 = * LEA(b+16) long
/--* t243 long
N015 ( 4, 4) [000042] *c-XG------- t42 = * IND long <l:$144, c:$2c2>
/--* t42 long
N016 ( 5, 5) [000043] ---XG------- t43 = * HWIntrinsic long PopCount $302
/--* t43 long
N017 ( 6, 7) [000163] ---XG------- t163 = * CAST int <- long $204
/--* t34 int
+--* t163 int
N018 ( 19, 21) [000044] ---XG------- t44 = * ADD int $205
N019 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V03 tmp2 u:3 $141
/--* t45 long
[000244] -c---------- t244 = * LEA(b+24) long
/--* t244 long
N022 ( 4, 4) [000052] *c-XG------- t52 = * IND long <l:$145, c:$2c3>
/--* t52 long
N023 ( 5, 5) [000053] ---XG------- t53 = * HWIntrinsic long PopCount $303
/--* t53 long
N024 ( 6, 7) [000161] ---XG------- t161 = * CAST int <- long $206
/--* t44 int
+--* t161 int
N025 ( 26, 29) [000054] ---XG------- t54 = * ADD int $207
N026 ( 1, 1) [000024] ------------ t24 = LCL_VAR int V04 tmp3 u:3 (last use) $280
/--* t24 int
+--* t54 int
N027 ( 28, 31) [000056] ---XG------- t56 = * SUB int $208
/--* t56 int
N029 ( 28, 31) [000059] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 3, 3) [000070] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR long V03 tmp2 u:3 (last use) $141
N002 ( 1, 1) [000066] -c---------- t66 = CNS_INT long 32 $344
/--* t61 long
+--* t66 long
N003 ( 3, 3) [000067] ------------ t67 = * ADD long $244
/--* t67 long
N005 ( 3, 3) [000069] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 5, 8) [000022] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR int V04 tmp3 u:4 $208
N002 ( 1, 4) [000019] -c---------- t19 = CNS_INT int 256 $43
/--* t18 int
+--* t19 int
N003 ( 3, 6) [000020] J------N---- * GE void $209
N004 ( 5, 8) [000021] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000218] ------------ t218 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ t214 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t218 long
+--* t214 long
N005 ( 2, 2) [000203] ------------ t203 = * PHI long
/--* t203 long
N007 ( 2, 3) [000204] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000220] ------------ t220 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ t216 = PHI_ARG int V04 tmp3 u:2 $80
/--* t220 int
+--* t216 int
N005 ( 2, 2) [000195] ------------ t195 = * PHI int
/--* t195 int
N007 ( 2, 3) [000196] DA---------- * STORE_LCL_VAR int V04 tmp3 d:5
( 1, 3) [000075] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR int V04 tmp3 u:5 $281
/--* t72 int
N003 ( 1, 3) [000074] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V05 tmp4 u:2 $281
N002 ( 1, 1) [000175] -c---------- t175 = CNS_INT int 0 $40
/--* t174 int
+--* t175 int
N003 ( 3, 3) [000173] J------N---- * LE void $20a
N004 ( 5, 5) [000176] ------------ * JTRUE void
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
N001 ( 0, 0) [000238] ------------ t238 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ t226 = PHI_ARG long V03 tmp2 u:5 $146
/--* t238 long
+--* t226 long
N005 ( 2, 2) [000187] ------------ t187 = * PHI long
/--* t187 long
N007 ( 2, 3) [000188] DA---------- * STORE_LCL_VAR long V03 tmp2 d:6
N001 ( 0, 0) [000240] ------------ t240 = PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ t228 = PHI_ARG int V04 tmp3 u:5 $281
/--* t240 int
+--* t228 int
N005 ( 2, 2) [000179] ------------ t179 = * PHI int
/--* t179 int
N007 ( 2, 3) [000180] DA---------- * STORE_LCL_VAR int V04 tmp3 d:6
( 1, 3) [000086] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V04 tmp3 u:6 (last use) $282
/--* t83 int
N003 ( 1, 3) [000085] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 7, 7) [000096] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V05 tmp4 u:3 $282
N002 ( 1, 1) [000088] ------------ t88 = LCL_VAR long V03 tmp2 u:6 $147
/--* t88 long
N003 ( 3, 2) [000089] *c-XG------- t89 = * IND long <l:$148, c:$400>
/--* t89 long
N004 ( 4, 3) [000090] ---XG------- t90 = * HWIntrinsic long PopCount $440
/--* t90 long
N005 ( 5, 5) [000091] ---XG------- t91 = * CAST int <- long $20b
/--* t87 int
+--* t91 int
N006 ( 7, 7) [000092] ---XG------- t92 = * SUB int $20c
/--* t92 int
N008 ( 7, 7) [000095] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:7
( 3, 3) [000103] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000097] ------------ t97 = LCL_VAR long V03 tmp2 u:6 (last use) $147
N002 ( 1, 1) [000099] -c---------- t99 = CNS_INT long 8 $340
/--* t97 long
+--* t99 long
N003 ( 3, 3) [000100] ------------ t100 = * ADD long $246
/--* t100 long
N005 ( 3, 3) [000102] DA---------- * STORE_LCL_VAR long V03 tmp2 d:7
( 5, 5) [000081] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000077] ------------ t77 = LCL_VAR int V04 tmp3 u:7 $20c
N002 ( 1, 1) [000078] -c---------- t78 = CNS_INT int 0 $40
/--* t77 int
+--* t78 int
N003 ( 3, 3) [000079] J------N---- * GT void $20d
N004 ( 5, 5) [000080] ------------ * JTRUE void
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
N001 ( 0, 0) [000234] ------------ t234 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ t230 = PHI_ARG int V05 tmp4 u:2 $281
/--* t234 int
+--* t230 int
N005 ( 2, 2) [000191] ------------ t191 = * PHI int
/--* t191 int
N007 ( 2, 3) [000192] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
N001 ( 0, 0) [000236] ------------ t236 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ t232 = PHI_ARG long V03 tmp2 u:5 $146
/--* t236 long
+--* t232 long
N005 ( 2, 2) [000183] ------------ t183 = * PHI long
/--* t183 long
N007 ( 2, 3) [000184] DA---------- * STORE_LCL_VAR long V03 tmp2 d:8
( 3, 3) [000111] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000105] ------------ t105 = LCL_VAR long V03 tmp2 u:8 (last use) $149
N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT long -8 $345
/--* t105 long
+--* t107 long
N003 ( 3, 3) [000108] ------------ t108 = * ADD long $247
/--* t108 long
N005 ( 3, 3) [000110] DA---------- * STORE_LCL_VAR long V03 tmp2 d:9
( 16, 13) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:4 (last use) $283
N002 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20f
N006 ( 1, 1) [000113] ------------ t113 = CNS_INT long 1 $346
/--* t113 long
+--* t116 int
N007 ( 10, 7) [000119] ------------ t119 = * LSH long $248
N008 ( 1, 1) [000120] ------------ t120 = LCL_VAR long V03 tmp2 u:9 $247
/--* t120 long
N009 ( 3, 2) [000121] *c-XG------- t121 = * IND long <l:$14a, c:$184>
/--* t119 long
+--* t121 long
N010 ( 14, 10) [000122] ---XG------- t122 = * HWIntrinsic long ParallelBitDeposit $480
/--* t122 long
N011 ( 15, 11) [000123] ---XG------- t123 = * HWIntrinsic long TrailingZeroCount $481
/--* t123 long
N012 ( 16, 13) [000124] ---XG------- t124 = * CAST int <- long $211
/--* t124 int
N014 ( 16, 13) [000126] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2
N001 ( 1, 1) [000128] ------------ t128 = LCL_VAR long V03 tmp2 u:9 (last use) $247
N002 ( 1, 1) [000129] ------------ t129 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t128 long
+--* t129 long
N003 ( 3, 3) [000130] ------------ t130 = * SUB long <l:$249, c:$24a>
/--* t130 long
[000246] DA---------- * STORE_LCL_VAR long V07 rat0
N001 ( 1, 1) [000247] ------------ t247 = LCL_VAR long V07 rat0
N002 ( 1, 1) [000248] -c---------- t248 = CNS_INT int 63
/--* t247 long
+--* t248 int
N003 ( 3, 3) [000249] ------------ t249 = * RSH long
N004 ( 1, 1) [000250] -c---------- t250 = CNS_INT long 7
/--* t249 long
+--* t250 long
N005 ( 5, 5) [000251] ------------ t251 = * AND long
N006 ( 1, 1) [000252] ------------ t252 = LCL_VAR long V07 rat0 (last use)
/--* t251 long
+--* t252 long
N007 ( 7, 7) [000253] ------------ t253 = * ADD long
N008 ( 1, 1) [000132] -c---------- t132 = CNS_INT long 3 $340
/--* t253 long
+--* t132 long
N009 ( 9, 9) [000254] ------------ t254 = * RSH long
/--* t254 long
N006 ( 25, 9) [000166] ------------ t166 = * CAST int <- long <l:$212, c:$213>
N007 ( 1, 1) [000135] -c---------- t135 = CNS_INT int 6 $4b
/--* t166 int
+--* t135 int
N008 ( 27, 11) [000136] ------------ t136 = * LSH int <l:$214, c:$215>
N009 ( 1, 1) [000138] ------------ t138 = LCL_VAR int V06 tmp5 u:2 (last use) $211
/--* t136 int
+--* t138 int
N010 ( 29, 13) [000139] ------------ t139 = * ADD int <l:$216, c:$217>
/--* t139 int
N011 ( 30, 14) [000010] ------------ * RETURN int $1c3
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Lowering
Trees after Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd LIR
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000142] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000159] ------------ t159 = CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
/--* t159 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000141] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000145] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000144] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 5, 8) [000172] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000169] ------------ t169 = LCL_VAR int V04 tmp3 u:2 $80
N002 ( 1, 4) [000170] -c---------- t170 = CNS_INT int 256 $43
/--* t169 int
+--* t170 int
N003 ( 3, 6) [000168] J------N---- * LT void $200
N004 ( 5, 8) [000171] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000222] ------------ t222 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ t210 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t222 long
+--* t210 long
N005 ( 2, 2) [000207] ------------ t207 = * PHI long
/--* t207 long
N007 ( 2, 3) [000208] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000224] ------------ t224 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ t212 = PHI_ARG int V04 tmp3 u:2 $80
/--* t224 int
+--* t212 int
N005 ( 2, 2) [000199] ------------ t199 = * PHI int
/--* t199 int
N007 ( 2, 3) [000200] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 28, 31) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V03 tmp2 u:3 $141
/--* t25 long
N002 ( 3, 2) [000026] *c-XG------- t26 = * IND long <l:$142, c:$2c0>
/--* t26 long
N003 ( 4, 3) [000027] ---XG------- t27 = * HWIntrinsic long PopCount $300
/--* t27 long
N004 ( 5, 5) [000164] ---XG------- t164 = * CAST int <- long $201
N005 ( 1, 1) [000028] ------------ t28 = LCL_VAR long V03 tmp2 u:3 $141
/--* t28 long
[000242] -c---------- t242 = * LEA(b+8) long
/--* t242 long
N008 ( 4, 4) [000032] *c-XG------- t32 = * IND long <l:$143, c:$2c1>
/--* t32 long
N009 ( 5, 5) [000033] ---XG------- t33 = * HWIntrinsic long PopCount $301
/--* t33 long
N010 ( 6, 7) [000165] ---XG------- t165 = * CAST int <- long $202
/--* t164 int
+--* t165 int
N011 ( 12, 13) [000034] ---XG------- t34 = * ADD int $203
N012 ( 1, 1) [000035] ------------ t35 = LCL_VAR long V03 tmp2 u:3 $141
/--* t35 long
[000243] -c---------- t243 = * LEA(b+16) long
/--* t243 long
N015 ( 4, 4) [000042] *c-XG------- t42 = * IND long <l:$144, c:$2c2>
/--* t42 long
N016 ( 5, 5) [000043] ---XG------- t43 = * HWIntrinsic long PopCount $302
/--* t43 long
N017 ( 6, 7) [000163] ---XG------- t163 = * CAST int <- long $204
/--* t34 int
+--* t163 int
N018 ( 19, 21) [000044] ---XG------- t44 = * ADD int $205
N019 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V03 tmp2 u:3 $141
/--* t45 long
[000244] -c---------- t244 = * LEA(b+24) long
/--* t244 long
N022 ( 4, 4) [000052] *c-XG------- t52 = * IND long <l:$145, c:$2c3>
/--* t52 long
N023 ( 5, 5) [000053] ---XG------- t53 = * HWIntrinsic long PopCount $303
/--* t53 long
N024 ( 6, 7) [000161] ---XG------- t161 = * CAST int <- long $206
/--* t44 int
+--* t161 int
N025 ( 26, 29) [000054] ---XG------- t54 = * ADD int $207
N026 ( 1, 1) [000024] ------------ t24 = LCL_VAR int V04 tmp3 u:3 (last use) $280
/--* t24 int
+--* t54 int
N027 ( 28, 31) [000056] ---XG------- t56 = * SUB int $208
/--* t56 int
N029 ( 28, 31) [000059] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 3, 3) [000070] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR long V03 tmp2 u:3 (last use) $141
N002 ( 1, 1) [000066] -c---------- t66 = CNS_INT long 32 $344
/--* t61 long
+--* t66 long
N003 ( 3, 3) [000067] ------------ t67 = * ADD long $244
/--* t67 long
N005 ( 3, 3) [000069] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 5, 8) [000022] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR int V04 tmp3 u:4 $208
N002 ( 1, 4) [000019] -c---------- t19 = CNS_INT int 256 $43
/--* t18 int
+--* t19 int
N003 ( 3, 6) [000020] J------N---- * GE void $209
N004 ( 5, 8) [000021] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000218] ------------ t218 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ t214 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t218 long
+--* t214 long
N005 ( 2, 2) [000203] ------------ t203 = * PHI long
/--* t203 long
N007 ( 2, 3) [000204] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000220] ------------ t220 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ t216 = PHI_ARG int V04 tmp3 u:2 $80
/--* t220 int
+--* t216 int
N005 ( 2, 2) [000195] ------------ t195 = * PHI int
/--* t195 int
N007 ( 2, 3) [000196] DA---------- * STORE_LCL_VAR int V04 tmp3 d:5
( 1, 3) [000075] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR int V04 tmp3 u:5 $281
/--* t72 int
N003 ( 1, 3) [000074] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V05 tmp4 u:2 $281
N002 ( 1, 1) [000175] -c---------- t175 = CNS_INT int 0 $40
/--* t174 int
+--* t175 int
N003 ( 3, 3) [000173] J------N---- * LE void $20a
N004 ( 5, 5) [000176] ------------ * JTRUE void
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
N001 ( 0, 0) [000238] ------------ t238 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ t226 = PHI_ARG long V03 tmp2 u:5 $146
/--* t238 long
+--* t226 long
N005 ( 2, 2) [000187] ------------ t187 = * PHI long
/--* t187 long
N007 ( 2, 3) [000188] DA---------- * STORE_LCL_VAR long V03 tmp2 d:6
N001 ( 0, 0) [000240] ------------ t240 = PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ t228 = PHI_ARG int V04 tmp3 u:5 $281
/--* t240 int
+--* t228 int
N005 ( 2, 2) [000179] ------------ t179 = * PHI int
/--* t179 int
N007 ( 2, 3) [000180] DA---------- * STORE_LCL_VAR int V04 tmp3 d:6
( 1, 3) [000086] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V04 tmp3 u:6 (last use) $282
/--* t83 int
N003 ( 1, 3) [000085] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 7, 7) [000096] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V05 tmp4 u:3 $282
N002 ( 1, 1) [000088] ------------ t88 = LCL_VAR long V03 tmp2 u:6 $147
/--* t88 long
N003 ( 3, 2) [000089] *c-XG------- t89 = * IND long <l:$148, c:$400>
/--* t89 long
N004 ( 4, 3) [000090] ---XG------- t90 = * HWIntrinsic long PopCount $440
/--* t90 long
N005 ( 5, 5) [000091] ---XG------- t91 = * CAST int <- long $20b
/--* t87 int
+--* t91 int
N006 ( 7, 7) [000092] ---XG------- t92 = * SUB int $20c
/--* t92 int
N008 ( 7, 7) [000095] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:7
( 3, 3) [000103] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000097] ------------ t97 = LCL_VAR long V03 tmp2 u:6 (last use) $147
N002 ( 1, 1) [000099] -c---------- t99 = CNS_INT long 8 $340
/--* t97 long
+--* t99 long
N003 ( 3, 3) [000100] ------------ t100 = * ADD long $246
/--* t100 long
N005 ( 3, 3) [000102] DA---------- * STORE_LCL_VAR long V03 tmp2 d:7
( 5, 5) [000081] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000077] ------------ t77 = LCL_VAR int V04 tmp3 u:7 $20c
N002 ( 1, 1) [000078] -c---------- t78 = CNS_INT int 0 $40
/--* t77 int
+--* t78 int
N003 ( 3, 3) [000079] J------N---- * GT void $20d
N004 ( 5, 5) [000080] ------------ * JTRUE void
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
N001 ( 0, 0) [000234] ------------ t234 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ t230 = PHI_ARG int V05 tmp4 u:2 $281
/--* t234 int
+--* t230 int
N005 ( 2, 2) [000191] ------------ t191 = * PHI int
/--* t191 int
N007 ( 2, 3) [000192] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
N001 ( 0, 0) [000236] ------------ t236 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ t232 = PHI_ARG long V03 tmp2 u:5 $146
/--* t236 long
+--* t232 long
N005 ( 2, 2) [000183] ------------ t183 = * PHI long
/--* t183 long
N007 ( 2, 3) [000184] DA---------- * STORE_LCL_VAR long V03 tmp2 d:8
( 3, 3) [000111] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000105] ------------ t105 = LCL_VAR long V03 tmp2 u:8 (last use) $149
N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT long -8 $345
/--* t105 long
+--* t107 long
N003 ( 3, 3) [000108] ------------ t108 = * ADD long $247
/--* t108 long
N005 ( 3, 3) [000110] DA---------- * STORE_LCL_VAR long V03 tmp2 d:9
( 16, 13) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:4 (last use) $283
N002 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20f
N006 ( 1, 1) [000113] ------------ t113 = CNS_INT long 1 $346
/--* t113 long
+--* t116 int
N007 ( 10, 7) [000119] ------------ t119 = * LSH long $248
N008 ( 1, 1) [000120] ------------ t120 = LCL_VAR long V03 tmp2 u:9 $247
/--* t120 long
N009 ( 3, 2) [000121] *c-XG------- t121 = * IND long <l:$14a, c:$184>
/--* t119 long
+--* t121 long
N010 ( 14, 10) [000122] ---XG------- t122 = * HWIntrinsic long ParallelBitDeposit $480
/--* t122 long
N011 ( 15, 11) [000123] ---XG------- t123 = * HWIntrinsic long TrailingZeroCount $481
/--* t123 long
N012 ( 16, 13) [000124] ---XG------- t124 = * CAST int <- long $211
/--* t124 int
N014 ( 16, 13) [000126] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2
N001 ( 1, 1) [000128] ------------ t128 = LCL_VAR long V03 tmp2 u:9 (last use) $247
N002 ( 1, 1) [000129] ------------ t129 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t128 long
+--* t129 long
N003 ( 3, 3) [000130] ------------ t130 = * SUB long <l:$249, c:$24a>
/--* t130 long
[000246] DA---------- * STORE_LCL_VAR long V07 rat0
N001 ( 1, 1) [000247] ------------ t247 = LCL_VAR long V07 rat0
N002 ( 1, 1) [000248] -c---------- t248 = CNS_INT int 63
/--* t247 long
+--* t248 int
N003 ( 3, 3) [000249] ------------ t249 = * RSH long
N004 ( 1, 1) [000250] -c---------- t250 = CNS_INT long 7
/--* t249 long
+--* t250 long
N005 ( 5, 5) [000251] ------------ t251 = * AND long
N006 ( 1, 1) [000252] ------------ t252 = LCL_VAR long V07 rat0 (last use)
/--* t251 long
+--* t252 long
N007 ( 7, 7) [000253] ------------ t253 = * ADD long
N008 ( 1, 1) [000132] -c---------- t132 = CNS_INT long 3 $340
/--* t253 long
+--* t132 long
N009 ( 9, 9) [000254] ------------ t254 = * RSH long
/--* t254 long
N006 ( 25, 9) [000166] ------------ t166 = * CAST int <- long <l:$212, c:$213>
N007 ( 1, 1) [000135] -c---------- t135 = CNS_INT int 6 $4b
/--* t166 int
+--* t135 int
N008 ( 27, 11) [000136] ------------ t136 = * LSH int <l:$214, c:$215>
N009 ( 1, 1) [000138] ------------ t138 = LCL_VAR int V06 tmp5 u:2 (last use) $211
/--* t136 int
+--* t138 int
N010 ( 29, 13) [000139] ------------ t139 = * ADD int <l:$216, c:$217>
/--* t139 int
N011 ( 30, 14) [000010] ------------ * RETURN int $1c3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In StackLevelSetter
Trees before StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd LIR
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000142] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000159] ------------ t159 = CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
/--* t159 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000141] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000145] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000144] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 5, 8) [000172] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000169] ------------ t169 = LCL_VAR int V04 tmp3 u:2 $80
N002 ( 1, 4) [000170] -c---------- t170 = CNS_INT int 256 $43
/--* t169 int
+--* t170 int
N003 ( 3, 6) [000168] J------N---- * LT void $200
N004 ( 5, 8) [000171] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000222] ------------ t222 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ t210 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t222 long
+--* t210 long
N005 ( 2, 2) [000207] ------------ t207 = * PHI long
/--* t207 long
N007 ( 2, 3) [000208] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000224] ------------ t224 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ t212 = PHI_ARG int V04 tmp3 u:2 $80
/--* t224 int
+--* t212 int
N005 ( 2, 2) [000199] ------------ t199 = * PHI int
/--* t199 int
N007 ( 2, 3) [000200] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 28, 31) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V03 tmp2 u:3 $141
/--* t25 long
N002 ( 3, 2) [000026] *c-XG------- t26 = * IND long <l:$142, c:$2c0>
/--* t26 long
N003 ( 4, 3) [000027] ---XG------- t27 = * HWIntrinsic long PopCount $300
/--* t27 long
N004 ( 5, 5) [000164] ---XG------- t164 = * CAST int <- long $201
N005 ( 1, 1) [000028] ------------ t28 = LCL_VAR long V03 tmp2 u:3 $141
/--* t28 long
[000242] -c---------- t242 = * LEA(b+8) long
/--* t242 long
N008 ( 4, 4) [000032] *c-XG------- t32 = * IND long <l:$143, c:$2c1>
/--* t32 long
N009 ( 5, 5) [000033] ---XG------- t33 = * HWIntrinsic long PopCount $301
/--* t33 long
N010 ( 6, 7) [000165] ---XG------- t165 = * CAST int <- long $202
/--* t164 int
+--* t165 int
N011 ( 12, 13) [000034] ---XG------- t34 = * ADD int $203
N012 ( 1, 1) [000035] ------------ t35 = LCL_VAR long V03 tmp2 u:3 $141
/--* t35 long
[000243] -c---------- t243 = * LEA(b+16) long
/--* t243 long
N015 ( 4, 4) [000042] *c-XG------- t42 = * IND long <l:$144, c:$2c2>
/--* t42 long
N016 ( 5, 5) [000043] ---XG------- t43 = * HWIntrinsic long PopCount $302
/--* t43 long
N017 ( 6, 7) [000163] ---XG------- t163 = * CAST int <- long $204
/--* t34 int
+--* t163 int
N018 ( 19, 21) [000044] ---XG------- t44 = * ADD int $205
N019 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V03 tmp2 u:3 $141
/--* t45 long
[000244] -c---------- t244 = * LEA(b+24) long
/--* t244 long
N022 ( 4, 4) [000052] *c-XG------- t52 = * IND long <l:$145, c:$2c3>
/--* t52 long
N023 ( 5, 5) [000053] ---XG------- t53 = * HWIntrinsic long PopCount $303
/--* t53 long
N024 ( 6, 7) [000161] ---XG------- t161 = * CAST int <- long $206
/--* t44 int
+--* t161 int
N025 ( 26, 29) [000054] ---XG------- t54 = * ADD int $207
N026 ( 1, 1) [000024] ------------ t24 = LCL_VAR int V04 tmp3 u:3 (last use) $280
/--* t24 int
+--* t54 int
N027 ( 28, 31) [000056] ---XG------- t56 = * SUB int $208
/--* t56 int
N029 ( 28, 31) [000059] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 3, 3) [000070] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR long V03 tmp2 u:3 (last use) $141
N002 ( 1, 1) [000066] -c---------- t66 = CNS_INT long 32 $344
/--* t61 long
+--* t66 long
N003 ( 3, 3) [000067] ------------ t67 = * ADD long $244
/--* t67 long
N005 ( 3, 3) [000069] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 5, 8) [000022] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR int V04 tmp3 u:4 $208
N002 ( 1, 4) [000019] -c---------- t19 = CNS_INT int 256 $43
/--* t18 int
+--* t19 int
N003 ( 3, 6) [000020] J------N---- * GE void $209
N004 ( 5, 8) [000021] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000218] ------------ t218 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ t214 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t218 long
+--* t214 long
N005 ( 2, 2) [000203] ------------ t203 = * PHI long
/--* t203 long
N007 ( 2, 3) [000204] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000220] ------------ t220 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ t216 = PHI_ARG int V04 tmp3 u:2 $80
/--* t220 int
+--* t216 int
N005 ( 2, 2) [000195] ------------ t195 = * PHI int
/--* t195 int
N007 ( 2, 3) [000196] DA---------- * STORE_LCL_VAR int V04 tmp3 d:5
( 1, 3) [000075] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR int V04 tmp3 u:5 $281
/--* t72 int
N003 ( 1, 3) [000074] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V05 tmp4 u:2 $281
N002 ( 1, 1) [000175] -c---------- t175 = CNS_INT int 0 $40
/--* t174 int
+--* t175 int
N003 ( 3, 3) [000173] J------N---- * LE void $20a
N004 ( 5, 5) [000176] ------------ * JTRUE void
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
N001 ( 0, 0) [000238] ------------ t238 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ t226 = PHI_ARG long V03 tmp2 u:5 $146
/--* t238 long
+--* t226 long
N005 ( 2, 2) [000187] ------------ t187 = * PHI long
/--* t187 long
N007 ( 2, 3) [000188] DA---------- * STORE_LCL_VAR long V03 tmp2 d:6
N001 ( 0, 0) [000240] ------------ t240 = PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ t228 = PHI_ARG int V04 tmp3 u:5 $281
/--* t240 int
+--* t228 int
N005 ( 2, 2) [000179] ------------ t179 = * PHI int
/--* t179 int
N007 ( 2, 3) [000180] DA---------- * STORE_LCL_VAR int V04 tmp3 d:6
( 1, 3) [000086] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V04 tmp3 u:6 (last use) $282
/--* t83 int
N003 ( 1, 3) [000085] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 7, 7) [000096] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V05 tmp4 u:3 $282
N002 ( 1, 1) [000088] ------------ t88 = LCL_VAR long V03 tmp2 u:6 $147
/--* t88 long
N003 ( 3, 2) [000089] *c-XG------- t89 = * IND long <l:$148, c:$400>
/--* t89 long
N004 ( 4, 3) [000090] ---XG------- t90 = * HWIntrinsic long PopCount $440
/--* t90 long
N005 ( 5, 5) [000091] ---XG------- t91 = * CAST int <- long $20b
/--* t87 int
+--* t91 int
N006 ( 7, 7) [000092] ---XG------- t92 = * SUB int $20c
/--* t92 int
N008 ( 7, 7) [000095] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:7
( 3, 3) [000103] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000097] ------------ t97 = LCL_VAR long V03 tmp2 u:6 (last use) $147
N002 ( 1, 1) [000099] -c---------- t99 = CNS_INT long 8 $340
/--* t97 long
+--* t99 long
N003 ( 3, 3) [000100] ------------ t100 = * ADD long $246
/--* t100 long
N005 ( 3, 3) [000102] DA---------- * STORE_LCL_VAR long V03 tmp2 d:7
( 5, 5) [000081] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000077] ------------ t77 = LCL_VAR int V04 tmp3 u:7 $20c
N002 ( 1, 1) [000078] -c---------- t78 = CNS_INT int 0 $40
/--* t77 int
+--* t78 int
N003 ( 3, 3) [000079] J------N---- * GT void $20d
N004 ( 5, 5) [000080] ------------ * JTRUE void
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
N001 ( 0, 0) [000234] ------------ t234 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ t230 = PHI_ARG int V05 tmp4 u:2 $281
/--* t234 int
+--* t230 int
N005 ( 2, 2) [000191] ------------ t191 = * PHI int
/--* t191 int
N007 ( 2, 3) [000192] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
N001 ( 0, 0) [000236] ------------ t236 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ t232 = PHI_ARG long V03 tmp2 u:5 $146
/--* t236 long
+--* t232 long
N005 ( 2, 2) [000183] ------------ t183 = * PHI long
/--* t183 long
N007 ( 2, 3) [000184] DA---------- * STORE_LCL_VAR long V03 tmp2 d:8
( 3, 3) [000111] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000105] ------------ t105 = LCL_VAR long V03 tmp2 u:8 (last use) $149
N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT long -8 $345
/--* t105 long
+--* t107 long
N003 ( 3, 3) [000108] ------------ t108 = * ADD long $247
/--* t108 long
N005 ( 3, 3) [000110] DA---------- * STORE_LCL_VAR long V03 tmp2 d:9
( 16, 13) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:4 (last use) $283
N002 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20f
N006 ( 1, 1) [000113] ------------ t113 = CNS_INT long 1 $346
/--* t113 long
+--* t116 int
N007 ( 10, 7) [000119] ------------ t119 = * LSH long $248
N008 ( 1, 1) [000120] ------------ t120 = LCL_VAR long V03 tmp2 u:9 $247
/--* t120 long
N009 ( 3, 2) [000121] *c-XG------- t121 = * IND long <l:$14a, c:$184>
/--* t119 long
+--* t121 long
N010 ( 14, 10) [000122] ---XG------- t122 = * HWIntrinsic long ParallelBitDeposit $480
/--* t122 long
N011 ( 15, 11) [000123] ---XG------- t123 = * HWIntrinsic long TrailingZeroCount $481
/--* t123 long
N012 ( 16, 13) [000124] ---XG------- t124 = * CAST int <- long $211
/--* t124 int
N014 ( 16, 13) [000126] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2
N001 ( 1, 1) [000128] ------------ t128 = LCL_VAR long V03 tmp2 u:9 (last use) $247
N002 ( 1, 1) [000129] ------------ t129 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t128 long
+--* t129 long
N003 ( 3, 3) [000130] ------------ t130 = * SUB long <l:$249, c:$24a>
/--* t130 long
[000246] DA---------- * STORE_LCL_VAR long V07 rat0
N001 ( 1, 1) [000247] ------------ t247 = LCL_VAR long V07 rat0
N002 ( 1, 1) [000248] -c---------- t248 = CNS_INT int 63
/--* t247 long
+--* t248 int
N003 ( 3, 3) [000249] ------------ t249 = * RSH long
N004 ( 1, 1) [000250] -c---------- t250 = CNS_INT long 7
/--* t249 long
+--* t250 long
N005 ( 5, 5) [000251] ------------ t251 = * AND long
N006 ( 1, 1) [000252] ------------ t252 = LCL_VAR long V07 rat0 (last use)
/--* t251 long
+--* t252 long
N007 ( 7, 7) [000253] ------------ t253 = * ADD long
N008 ( 1, 1) [000132] -c---------- t132 = CNS_INT long 3 $340
/--* t253 long
+--* t132 long
N009 ( 9, 9) [000254] ------------ t254 = * RSH long
/--* t254 long
N006 ( 25, 9) [000166] ------------ t166 = * CAST int <- long <l:$212, c:$213>
N007 ( 1, 1) [000135] -c---------- t135 = CNS_INT int 6 $4b
/--* t166 int
+--* t135 int
N008 ( 27, 11) [000136] ------------ t136 = * LSH int <l:$214, c:$215>
N009 ( 1, 1) [000138] ------------ t138 = LCL_VAR int V06 tmp5 u:2 (last use) $211
/--* t136 int
+--* t138 int
N010 ( 29, 13) [000139] ------------ t139 = * ADD int <l:$216, c:$217>
/--* t139 int
N011 ( 30, 14) [000010] ------------ * RETURN int $1c3
-------------------------------------------------------------------------------------------------------------------
*************** Exiting StackLevelSetter
Trees after StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd LIR
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000142] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000159] ------------ t159 = CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] $100
/--* t159 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000141] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000145] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000144] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 5, 8) [000172] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000169] ------------ t169 = LCL_VAR int V04 tmp3 u:2 $80
N002 ( 1, 4) [000170] -c---------- t170 = CNS_INT int 256 $43
/--* t169 int
+--* t170 int
N003 ( 3, 6) [000168] J------N---- * LT void $200
N004 ( 5, 8) [000171] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000222] ------------ t222 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000210] ------------ t210 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t222 long
+--* t210 long
N005 ( 2, 2) [000207] ------------ t207 = * PHI long
/--* t207 long
N007 ( 2, 3) [000208] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000224] ------------ t224 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000212] ------------ t212 = PHI_ARG int V04 tmp3 u:2 $80
/--* t224 int
+--* t212 int
N005 ( 2, 2) [000199] ------------ t199 = * PHI int
/--* t199 int
N007 ( 2, 3) [000200] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 28, 31) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V03 tmp2 u:3 $141
/--* t25 long
N002 ( 3, 2) [000026] *c-XG------- t26 = * IND long <l:$142, c:$2c0>
/--* t26 long
N003 ( 4, 3) [000027] ---XG------- t27 = * HWIntrinsic long PopCount $300
/--* t27 long
N004 ( 5, 5) [000164] ---XG------- t164 = * CAST int <- long $201
N005 ( 1, 1) [000028] ------------ t28 = LCL_VAR long V03 tmp2 u:3 $141
/--* t28 long
[000242] -c---------- t242 = * LEA(b+8) long
/--* t242 long
N008 ( 4, 4) [000032] *c-XG------- t32 = * IND long <l:$143, c:$2c1>
/--* t32 long
N009 ( 5, 5) [000033] ---XG------- t33 = * HWIntrinsic long PopCount $301
/--* t33 long
N010 ( 6, 7) [000165] ---XG------- t165 = * CAST int <- long $202
/--* t164 int
+--* t165 int
N011 ( 12, 13) [000034] ---XG------- t34 = * ADD int $203
N012 ( 1, 1) [000035] ------------ t35 = LCL_VAR long V03 tmp2 u:3 $141
/--* t35 long
[000243] -c---------- t243 = * LEA(b+16) long
/--* t243 long
N015 ( 4, 4) [000042] *c-XG------- t42 = * IND long <l:$144, c:$2c2>
/--* t42 long
N016 ( 5, 5) [000043] ---XG------- t43 = * HWIntrinsic long PopCount $302
/--* t43 long
N017 ( 6, 7) [000163] ---XG------- t163 = * CAST int <- long $204
/--* t34 int
+--* t163 int
N018 ( 19, 21) [000044] ---XG------- t44 = * ADD int $205
N019 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V03 tmp2 u:3 $141
/--* t45 long
[000244] -c---------- t244 = * LEA(b+24) long
/--* t244 long
N022 ( 4, 4) [000052] *c-XG------- t52 = * IND long <l:$145, c:$2c3>
/--* t52 long
N023 ( 5, 5) [000053] ---XG------- t53 = * HWIntrinsic long PopCount $303
/--* t53 long
N024 ( 6, 7) [000161] ---XG------- t161 = * CAST int <- long $206
/--* t44 int
+--* t161 int
N025 ( 26, 29) [000054] ---XG------- t54 = * ADD int $207
N026 ( 1, 1) [000024] ------------ t24 = LCL_VAR int V04 tmp3 u:3 (last use) $280
/--* t24 int
+--* t54 int
N027 ( 28, 31) [000056] ---XG------- t56 = * SUB int $208
/--* t56 int
N029 ( 28, 31) [000059] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 3, 3) [000070] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR long V03 tmp2 u:3 (last use) $141
N002 ( 1, 1) [000066] -c---------- t66 = CNS_INT long 32 $344
/--* t61 long
+--* t66 long
N003 ( 3, 3) [000067] ------------ t67 = * ADD long $244
/--* t67 long
N005 ( 3, 3) [000069] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 5, 8) [000022] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR int V04 tmp3 u:4 $208
N002 ( 1, 4) [000019] -c---------- t19 = CNS_INT int 256 $43
/--* t18 int
+--* t19 int
N003 ( 3, 6) [000020] J------N---- * GE void $209
N004 ( 5, 8) [000021] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000218] ------------ t218 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000214] ------------ t214 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t218 long
+--* t214 long
N005 ( 2, 2) [000203] ------------ t203 = * PHI long
/--* t203 long
N007 ( 2, 3) [000204] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000220] ------------ t220 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000216] ------------ t216 = PHI_ARG int V04 tmp3 u:2 $80
/--* t220 int
+--* t216 int
N005 ( 2, 2) [000195] ------------ t195 = * PHI int
/--* t195 int
N007 ( 2, 3) [000196] DA---------- * STORE_LCL_VAR int V04 tmp3 d:5
( 1, 3) [000075] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR int V04 tmp3 u:5 $281
/--* t72 int
N003 ( 1, 3) [000074] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V05 tmp4 u:2 $281
N002 ( 1, 1) [000175] -c---------- t175 = CNS_INT int 0 $40
/--* t174 int
+--* t175 int
N003 ( 3, 3) [000173] J------N---- * LE void $20a
N004 ( 5, 5) [000176] ------------ * JTRUE void
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
N001 ( 0, 0) [000238] ------------ t238 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000226] ------------ t226 = PHI_ARG long V03 tmp2 u:5 $146
/--* t238 long
+--* t226 long
N005 ( 2, 2) [000187] ------------ t187 = * PHI long
/--* t187 long
N007 ( 2, 3) [000188] DA---------- * STORE_LCL_VAR long V03 tmp2 d:6
N001 ( 0, 0) [000240] ------------ t240 = PHI_ARG int V04 tmp3 u:7
N002 ( 0, 0) [000228] ------------ t228 = PHI_ARG int V04 tmp3 u:5 $281
/--* t240 int
+--* t228 int
N005 ( 2, 2) [000179] ------------ t179 = * PHI int
/--* t179 int
N007 ( 2, 3) [000180] DA---------- * STORE_LCL_VAR int V04 tmp3 d:6
( 1, 3) [000086] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V04 tmp3 u:6 (last use) $282
/--* t83 int
N003 ( 1, 3) [000085] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 7, 7) [000096] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V05 tmp4 u:3 $282
N002 ( 1, 1) [000088] ------------ t88 = LCL_VAR long V03 tmp2 u:6 $147
/--* t88 long
N003 ( 3, 2) [000089] *c-XG------- t89 = * IND long <l:$148, c:$400>
/--* t89 long
N004 ( 4, 3) [000090] ---XG------- t90 = * HWIntrinsic long PopCount $440
/--* t90 long
N005 ( 5, 5) [000091] ---XG------- t91 = * CAST int <- long $20b
/--* t87 int
+--* t91 int
N006 ( 7, 7) [000092] ---XG------- t92 = * SUB int $20c
/--* t92 int
N008 ( 7, 7) [000095] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:7
( 3, 3) [000103] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000097] ------------ t97 = LCL_VAR long V03 tmp2 u:6 (last use) $147
N002 ( 1, 1) [000099] -c---------- t99 = CNS_INT long 8 $340
/--* t97 long
+--* t99 long
N003 ( 3, 3) [000100] ------------ t100 = * ADD long $246
/--* t100 long
N005 ( 3, 3) [000102] DA---------- * STORE_LCL_VAR long V03 tmp2 d:7
( 5, 5) [000081] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000077] ------------ t77 = LCL_VAR int V04 tmp3 u:7 $20c
N002 ( 1, 1) [000078] -c---------- t78 = CNS_INT int 0 $40
/--* t77 int
+--* t78 int
N003 ( 3, 3) [000079] J------N---- * GT void $20d
N004 ( 5, 5) [000080] ------------ * JTRUE void
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
N001 ( 0, 0) [000234] ------------ t234 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000230] ------------ t230 = PHI_ARG int V05 tmp4 u:2 $281
/--* t234 int
+--* t230 int
N005 ( 2, 2) [000191] ------------ t191 = * PHI int
/--* t191 int
N007 ( 2, 3) [000192] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
N001 ( 0, 0) [000236] ------------ t236 = PHI_ARG long V03 tmp2 u:7
N002 ( 0, 0) [000232] ------------ t232 = PHI_ARG long V03 tmp2 u:5 $146
/--* t236 long
+--* t232 long
N005 ( 2, 2) [000183] ------------ t183 = * PHI long
/--* t183 long
N007 ( 2, 3) [000184] DA---------- * STORE_LCL_VAR long V03 tmp2 d:8
( 3, 3) [000111] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000105] ------------ t105 = LCL_VAR long V03 tmp2 u:8 (last use) $149
N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT long -8 $345
/--* t105 long
+--* t107 long
N003 ( 3, 3) [000108] ------------ t108 = * ADD long $247
/--* t108 long
N005 ( 3, 3) [000110] DA---------- * STORE_LCL_VAR long V03 tmp2 d:9
( 16, 13) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:4 (last use) $283
N002 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20f
N006 ( 1, 1) [000113] ------------ t113 = CNS_INT long 1 $346
/--* t113 long
+--* t116 int
N007 ( 10, 7) [000119] ------------ t119 = * LSH long $248
N008 ( 1, 1) [000120] ------------ t120 = LCL_VAR long V03 tmp2 u:9 $247
/--* t120 long
N009 ( 3, 2) [000121] *c-XG------- t121 = * IND long <l:$14a, c:$184>
/--* t119 long
+--* t121 long
N010 ( 14, 10) [000122] ---XG------- t122 = * HWIntrinsic long ParallelBitDeposit $480
/--* t122 long
N011 ( 15, 11) [000123] ---XG------- t123 = * HWIntrinsic long TrailingZeroCount $481
/--* t123 long
N012 ( 16, 13) [000124] ---XG------- t124 = * CAST int <- long $211
/--* t124 int
N014 ( 16, 13) [000126] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2
N001 ( 1, 1) [000128] ------------ t128 = LCL_VAR long V03 tmp2 u:9 (last use) $247
N002 ( 1, 1) [000129] ------------ t129 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t128 long
+--* t129 long
N003 ( 3, 3) [000130] ------------ t130 = * SUB long <l:$249, c:$24a>
/--* t130 long
[000246] DA---------- * STORE_LCL_VAR long V07 rat0
N001 ( 1, 1) [000247] ------------ t247 = LCL_VAR long V07 rat0
N002 ( 1, 1) [000248] -c---------- t248 = CNS_INT int 63
/--* t247 long
+--* t248 int
N003 ( 3, 3) [000249] ------------ t249 = * RSH long
N004 ( 1, 1) [000250] -c---------- t250 = CNS_INT long 7
/--* t249 long
+--* t250 long
N005 ( 5, 5) [000251] ------------ t251 = * AND long
N006 ( 1, 1) [000252] ------------ t252 = LCL_VAR long V07 rat0 (last use)
/--* t251 long
+--* t252 long
N007 ( 7, 7) [000253] ------------ t253 = * ADD long
N008 ( 1, 1) [000132] -c---------- t132 = CNS_INT long 3 $340
/--* t253 long
+--* t132 long
N009 ( 9, 9) [000254] ------------ t254 = * RSH long
/--* t254 long
N006 ( 25, 9) [000166] ------------ t166 = * CAST int <- long <l:$212, c:$213>
N007 ( 1, 1) [000135] -c---------- t135 = CNS_INT int 6 $4b
/--* t166 int
+--* t135 int
N008 ( 27, 11) [000136] ------------ t136 = * LSH int <l:$214, c:$215>
N009 ( 1, 1) [000138] ------------ t138 = LCL_VAR int V06 tmp5 u:2 (last use) $211
/--* t136 int
+--* t138 int
N010 ( 29, 13) [000139] ------------ t139 = * ADD int <l:$216, c:$217>
/--* t139 int
N011 ( 30, 14) [000010] ------------ * RETURN int $1c3
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{V00}
{V02 V03 V04}
{V00}
{V02 V03 V04}
BB02 use def in out
{V03 V04}
{V03 V04}
{V02 V03 V04}
{V02 V03 V04}
BB03 use def in out
{V04}
{V05}
{V02 V03 V04}
{V02 V03 V04 V05}
BB04 use def in out
{V03 V04}
{V03 V04 V05}
{V02 V03 V04}
{V02 V03 V04 V05}
BB05 use def in out
{V02 V03 V05}
{V03 V06 V07}
{V02 V03 V05}
{}
Interval 0: RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {} physReg:NA Preferences=[allInt]
Interval 4: RefPositions {} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {} physReg:NA Preferences=[allInt]
Interval 6: RefPositions {} physReg:NA Preferences=[allInt]
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 1, singleExit = 1
; Decided to create an EBP based frame for ETW stackwalking (BasicBlock Count)
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 ) BB02( 2 ) BB03( 0.50) BB04( 2 ) BB05( 1 )
BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N000. IL_OFFSET IL offset: 0x0
N001. t159* = CNS_INT(h) 0x7f08ab884498 static Fseq[_bits]
N002. t1 = IND ; t159*
N004. V02(t141); t1
N000. IL_OFFSET IL offset: 0x0
N001. V00(t3*)
N003. V04(t144); t3*
N000. IL_OFFSET IL offset: 0x0
N001. V02(t13)
N003. V03(t15); t13
N000. IL_OFFSET IL offset: 0x0
N001. V04(t169)
N002. CNS_INT 256
N003. LT ; t169
N004. JTRUE
BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V03(t25)
N002. t26 = IND ; t25
N003. t27 = HWIntrinsic; t26
N004. t164 = CAST ; t27
N005. V03(t28)
N000. t242 = LEA(b+8) ; t28
N008. t32 = IND ; t242
N009. t33 = HWIntrinsic; t32
N010. t165 = CAST ; t33
N011. t34 = ADD ; t164,t165
N012. V03(t35)
N000. t243 = LEA(b+16); t35
N015. t42 = IND ; t243
N016. t43 = HWIntrinsic; t42
N017. t163 = CAST ; t43
N018. t44 = ADD ; t34,t163
N019. V03(t45)
N000. t244 = LEA(b+24); t45
N022. t52 = IND ; t244
N023. t53 = HWIntrinsic; t52
N024. t161 = CAST ; t53
N025. t54 = ADD ; t44,t161
N026. V04(t24*)
N027. t56 = SUB ; t24*,t54
N029. V04(t59); t56
N000. IL_OFFSET IL offset: 0x0
N001. V03(t61*)
N002. CNS_INT 32
N003. t67 = ADD ; t61*
N005. V03(t69); t67
N000. IL_OFFSET IL offset: 0x0
N001. V04(t18)
N002. CNS_INT 256
N003. GE ; t18
N004. JTRUE
BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V04(t72)
N003. V05(t74); t72
N000. IL_OFFSET IL offset: 0x0
N001. V05(t174)
N002. CNS_INT 0
N003. LE ; t174
N004. JTRUE
BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V04(t83*)
N003. V05(t85); t83*
N000. IL_OFFSET IL offset: 0x0
N001. V05(t87)
N002. V03(t88)
N003. t89 = IND ; t88
N004. t90 = HWIntrinsic; t89
N005. t91 = CAST ; t90
N006. t92 = SUB ; t87,t91
N008. V04(t95); t92
N000. IL_OFFSET IL offset: 0x0
N001. V03(t97*)
N002. CNS_INT 8
N003. t100 = ADD ; t97*
N005. V03(t102); t100
N000. IL_OFFSET IL offset: 0x0
N001. V04(t77)
N002. CNS_INT 0
N003. GT ; t77
N004. JTRUE
BB05 [000..001) (return), preds={BB03,BB04} succs={}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V03(t105*)
N002. CNS_INT -8
N003. t108 = ADD ; t105*
N005. V03(t110); t108
N000. IL_OFFSET IL offset: 0x0
N001. V05(t114*)
N002. CNS_INT -1
N003. t116 = ADD ; t114*
N006. t113 = CNS_INT 1
N007. t119 = LSH ; t113,t116
N008. V03(t120)
N009. t121 = IND ; t120
N010. t122 = HWIntrinsic; t119,t121
N011. t123 = HWIntrinsic; t122
N012. t124 = CAST ; t123
N014. V06(t126); t124
N001. V03(t128*)
N002. V02(t129*)
N003. t130 = SUB ; t128*,t129*
N000. V07(t246); t130
N001. V07(t247)
N002. CNS_INT 63
N003. t249 = RSH ; t247
N004. CNS_INT 7
N005. t251 = AND ; t249
N006. V07(t252*)
N007. t253 = ADD ; t251,t252*
N008. CNS_INT 3
N009. t254 = RSH ; t253
N006. t166 = CAST ; t254
N007. CNS_INT 6
N008. t136 = LSH ; t166
N009. V06(t138*)
N010. t139 = ADD ; t136,t138*
N011. RETURN ; t139
buildIntervals second part ========
Int arg V00 in reg rdi
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
NEW BLOCK BB01
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N003 ( 5, 12) [000142] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N005 ( 3, 10) [000159] ------------ * CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] REG NA $100
Interval 7: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #2 @6 RefTypeDef <Ivl:7> CNS_INT BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N005.t159. CNS_INT }
N007 ( 5, 12) [000001] x---G------- * IND long REG NA <l:$140, c:$180>
<RefPosition #3 @7 RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last>
Interval 8: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #4 @8 RefTypeDef <Ivl:8> IND BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N007.t1. IND }
N009 ( 5, 12) [000141] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2 NA REG NA
<RefPosition #5 @9 RefTypeUse <Ivl:8> BB01 regmask=[allInt] minReg=1 last>
Assigning related <L1> to <I8>
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N011 ( 1, 3) [000145] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N013 ( 1, 1) [000003] ------------ * LCL_VAR int V00 arg0 u:2 NA (last use) REG NA $80
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N015 ( 1, 3) [000144] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2 NA REG NA
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Assigning related <L3> to <L0>
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N017 ( 1, 3) [000016] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N019 ( 1, 1) [000013] ------------ * LCL_VAR long V02 tmp1 u:2 NA REG NA <l:$140, c:$180>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N021 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2 NA REG NA
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N023 ( 5, 8) [000172] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N025 ( 1, 1) [000169] ------------ * LCL_VAR int V04 tmp3 u:2 NA REG NA $80
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N027 ( 1, 4) [000170] -c---------- * CNS_INT int 256 REG NA $43
Contained
DefList: { }
N029 ( 3, 6) [000168] J------N---- * LT void REG NA $200
<RefPosition #11 @29 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N031 ( 5, 8) [000171] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
CHECKING LAST USES for block 1, liveout={V02 V03 V04}
==============================
use: {V00}
def: {V02 V03 V04}
NEW BLOCK BB02
Setting BB02 as the predecessor for determining incoming variable registers of BB01
<RefPosition #12 @33 RefTypeBB BB02 regmask=[] minReg=1>
DefList: { }
N035 ( 28, 31) [000060] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N037 ( 1, 1) [000025] ------------ * LCL_VAR long V03 tmp2 u:3 NA REG NA $141
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N039 ( 3, 2) [000026] *c-XG------- * IND long REG NA <l:$142, c:$2c0>
Contained
DefList: { }
N041 ( 4, 3) [000027] ---XG------- * HWIntrinsic long PopCount REG NA $300
<RefPosition #13 @41 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 9: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #14 @42 RefTypeDef <Ivl:9> HWIntrinsic BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N041.t27. HWIntrinsic }
N043 ( 5, 5) [000164] ---XG------- * CAST int <- long REG NA $201
<RefPosition #15 @43 RefTypeUse <Ivl:9> BB02 regmask=[allInt] minReg=1 last>
Interval 10: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #16 @44 RefTypeDef <Ivl:10> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N043.t164. CAST }
N045 ( 1, 1) [000028] ------------ * LCL_VAR long V03 tmp2 u:3 NA REG NA $141
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N043.t164. CAST }
N047 (???,???) [000242] -c---------- * LEA(b+8) long REG NA
Contained
DefList: { N043.t164. CAST }
N049 ( 4, 4) [000032] *c-XG------- * IND long REG NA <l:$143, c:$2c1>
Contained
DefList: { N043.t164. CAST }
N051 ( 5, 5) [000033] ---XG------- * HWIntrinsic long PopCount REG NA $301
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 11: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #18 @52 RefTypeDef <Ivl:11> HWIntrinsic BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N043.t164. CAST; N051.t33. HWIntrinsic }
N053 ( 6, 7) [000165] ---XG------- * CAST int <- long REG NA $202
<RefPosition #19 @53 RefTypeUse <Ivl:11> BB02 regmask=[allInt] minReg=1 last>
Interval 12: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #20 @54 RefTypeDef <Ivl:12> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N043.t164. CAST; N053.t165. CAST }
N055 ( 12, 13) [000034] ---XG------- * ADD int REG NA $203
<RefPosition #21 @55 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #22 @55 RefTypeUse <Ivl:12> BB02 regmask=[allInt] minReg=1 last>
Interval 13: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #23 @56 RefTypeDef <Ivl:13> ADD BB02 regmask=[allInt] minReg=1>
Assigning related <I10> to <I13>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 2 produce=1
DefList: { N055.t34. ADD }
N057 ( 1, 1) [000035] ------------ * LCL_VAR long V03 tmp2 u:3 NA REG NA $141
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N055.t34. ADD }
N059 (???,???) [000243] -c---------- * LEA(b+16) long REG NA
Contained
DefList: { N055.t34. ADD }
N061 ( 4, 4) [000042] *c-XG------- * IND long REG NA <l:$144, c:$2c2>
Contained
DefList: { N055.t34. ADD }
N063 ( 5, 5) [000043] ---XG------- * HWIntrinsic long PopCount REG NA $302
<RefPosition #24 @63 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 14: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #25 @64 RefTypeDef <Ivl:14> HWIntrinsic BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N055.t34. ADD; N063.t43. HWIntrinsic }
N065 ( 6, 7) [000163] ---XG------- * CAST int <- long REG NA $204
<RefPosition #26 @65 RefTypeUse <Ivl:14> BB02 regmask=[allInt] minReg=1 last>
Interval 15: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #27 @66 RefTypeDef <Ivl:15> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N055.t34. ADD; N065.t163. CAST }
N067 ( 19, 21) [000044] ---XG------- * ADD int REG NA $205
<RefPosition #28 @67 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #29 @67 RefTypeUse <Ivl:15> BB02 regmask=[allInt] minReg=1 last>
Interval 16: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #30 @68 RefTypeDef <Ivl:16> ADD BB02 regmask=[allInt] minReg=1>
Assigning related <I13> to <I16>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 2 produce=1
DefList: { N067.t44. ADD }
N069 ( 1, 1) [000045] ------------ * LCL_VAR long V03 tmp2 u:3 NA REG NA $141
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N067.t44. ADD }
N071 (???,???) [000244] -c---------- * LEA(b+24) long REG NA
Contained
DefList: { N067.t44. ADD }
N073 ( 4, 4) [000052] *c-XG------- * IND long REG NA <l:$145, c:$2c3>
Contained
DefList: { N067.t44. ADD }
N075 ( 5, 5) [000053] ---XG------- * HWIntrinsic long PopCount REG NA $303
<RefPosition #31 @75 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 17: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #32 @76 RefTypeDef <Ivl:17> HWIntrinsic BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N067.t44. ADD; N075.t53. HWIntrinsic }
N077 ( 6, 7) [000161] ---XG------- * CAST int <- long REG NA $206
<RefPosition #33 @77 RefTypeUse <Ivl:17> BB02 regmask=[allInt] minReg=1 last>
Interval 18: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #34 @78 RefTypeDef <Ivl:18> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N067.t44. ADD; N077.t161. CAST }
N079 ( 26, 29) [000054] ---XG------- * ADD int REG NA $207
<RefPosition #35 @79 RefTypeUse <Ivl:16> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #36 @79 RefTypeUse <Ivl:18> BB02 regmask=[allInt] minReg=1 last>
Interval 19: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #37 @80 RefTypeDef <Ivl:19> ADD BB02 regmask=[allInt] minReg=1>
Assigning related <I16> to <I19>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 2 produce=1
DefList: { N079.t54. ADD }
N081 ( 1, 1) [000024] ------------ * LCL_VAR int V04 tmp3 u:3 NA (last use) REG NA $280
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N079.t54. ADD }
N083 ( 28, 31) [000056] ---XG------- * SUB int REG NA $208
<RefPosition #38 @83 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #39 @83 RefTypeUse <Ivl:19> BB02 regmask=[allInt] minReg=1 last>
Interval 20: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #40 @84 RefTypeDef <Ivl:20> SUB BB02 regmask=[allInt] minReg=1>
Assigning related <L3> to <I20>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N083.t56. SUB }
N085 ( 28, 31) [000059] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4 NA REG NA
<RefPosition #41 @85 RefTypeUse <Ivl:20> BB02 regmask=[allInt] minReg=1 last>
Assigning related <L3> to <I20>
<RefPosition #42 @86 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N087 ( 3, 3) [000070] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N089 ( 1, 1) [000061] ------------ * LCL_VAR long V03 tmp2 u:3 NA (last use) REG NA $141
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N091 ( 1, 1) [000066] -c---------- * CNS_INT long 32 REG NA $344
Contained
DefList: { }
N093 ( 3, 3) [000067] ------------ * ADD long REG NA $244
<RefPosition #43 @93 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 21: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #44 @94 RefTypeDef <Ivl:21> ADD BB02 regmask=[allInt] minReg=1>
Assigning related <L2> to <I21>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N093.t67. ADD }
N095 ( 3, 3) [000069] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4 NA REG NA
<RefPosition #45 @95 RefTypeUse <Ivl:21> BB02 regmask=[allInt] minReg=1 last>
Assigning related <L2> to <I21>
<RefPosition #46 @96 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N097 ( 5, 8) [000022] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N099 ( 1, 1) [000018] ------------ * LCL_VAR int V04 tmp3 u:4 NA REG NA $208
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N101 ( 1, 4) [000019] -c---------- * CNS_INT int 256 REG NA $43
Contained
DefList: { }
N103 ( 3, 6) [000020] J------N---- * GE void REG NA $209
<RefPosition #47 @103 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N105 ( 5, 8) [000021] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
CHECKING LAST USES for block 2, liveout={V02 V03 V04}
==============================
use: {V03 V04}
def: {V03 V04}
NEW BLOCK BB03
Setting BB03 as the predecessor for determining incoming variable registers of BB02
<RefPosition #48 @107 RefTypeBB BB03 regmask=[] minReg=1>
DefList: { }
N109 ( 1, 3) [000075] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N111 ( 1, 1) [000072] ------------ * LCL_VAR int V04 tmp3 u:5 NA REG NA $281
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N113 ( 1, 3) [000074] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2 NA REG NA
<RefPosition #49 @113 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
<RefPosition #50 @114 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N115 ( 5, 5) [000177] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N117 ( 1, 1) [000174] ------------ * LCL_VAR int V05 tmp4 u:2 NA REG NA $281
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N119 ( 1, 1) [000175] -c---------- * CNS_INT int 0 REG NA $40
Contained
DefList: { }
N121 ( 3, 3) [000173] J------N---- * LE void REG NA $20a
<RefPosition #51 @121 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N123 ( 5, 5) [000176] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
CHECKING LAST USES for block 3, liveout={V02 V03 V04 V05}
==============================
use: {V04}
def: {V05}
NEW BLOCK BB04
Setting BB04 as the predecessor for determining incoming variable registers of BB03
<RefPosition #52 @125 RefTypeBB BB04 regmask=[] minReg=1>
DefList: { }
N127 ( 1, 3) [000086] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N129 ( 1, 1) [000083] ------------ * LCL_VAR int V04 tmp3 u:6 NA (last use) REG NA $282
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N131 ( 1, 3) [000085] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3 NA REG NA
<RefPosition #53 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
Assigning related <L4> to <L3>
<RefPosition #54 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N133 ( 7, 7) [000096] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N135 ( 1, 1) [000087] ------------ * LCL_VAR int V05 tmp4 u:3 NA REG NA $282
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N137 ( 1, 1) [000088] ------------ * LCL_VAR long V03 tmp2 u:6 NA REG NA $147
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N139 ( 3, 2) [000089] *c-XG------- * IND long REG NA <l:$148, c:$400>
Contained
DefList: { }
N141 ( 4, 3) [000090] ---XG------- * HWIntrinsic long PopCount REG NA $440
<RefPosition #55 @141 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
Interval 22: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #56 @142 RefTypeDef <Ivl:22> HWIntrinsic BB04 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N141.t90. HWIntrinsic }
N143 ( 5, 5) [000091] ---XG------- * CAST int <- long REG NA $20b
<RefPosition #57 @143 RefTypeUse <Ivl:22> BB04 regmask=[allInt] minReg=1 last>
Interval 23: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #58 @144 RefTypeDef <Ivl:23> CAST BB04 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N143.t91. CAST }
N145 ( 7, 7) [000092] ---XG------- * SUB int REG NA $20c
<RefPosition #59 @145 RefTypeUse <Ivl:4 V05> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #60 @145 RefTypeUse <Ivl:23> BB04 regmask=[allInt] minReg=1 last>
Interval 24: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #61 @146 RefTypeDef <Ivl:24> SUB BB04 regmask=[allInt] minReg=1>
Assigning related <L4> to <I24>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N145.t92. SUB }
N147 ( 7, 7) [000095] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:7 NA REG NA
<RefPosition #62 @147 RefTypeUse <Ivl:24> BB04 regmask=[allInt] minReg=1 last>
Assigning related <L3> to <I24>
<RefPosition #63 @148 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N149 ( 3, 3) [000103] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N151 ( 1, 1) [000097] ------------ * LCL_VAR long V03 tmp2 u:6 NA (last use) REG NA $147
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N153 ( 1, 1) [000099] -c---------- * CNS_INT long 8 REG NA $340
Contained
DefList: { }
N155 ( 3, 3) [000100] ------------ * ADD long REG NA $246
<RefPosition #64 @155 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
Interval 25: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #65 @156 RefTypeDef <Ivl:25> ADD BB04 regmask=[allInt] minReg=1>
Assigning related <L2> to <I25>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N155.t100. ADD }
N157 ( 3, 3) [000102] DA---------- * STORE_LCL_VAR long V03 tmp2 d:7 NA REG NA
<RefPosition #66 @157 RefTypeUse <Ivl:25> BB04 regmask=[allInt] minReg=1 last>
Assigning related <L2> to <I25>
<RefPosition #67 @158 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N159 ( 5, 5) [000081] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N161 ( 1, 1) [000077] ------------ * LCL_VAR int V04 tmp3 u:7 NA REG NA $20c
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N163 ( 1, 1) [000078] -c---------- * CNS_INT int 0 REG NA $40
Contained
DefList: { }
N165 ( 3, 3) [000079] J------N---- * GT void REG NA $20d
<RefPosition #68 @165 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N167 ( 5, 5) [000080] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
Exposed uses:<RefPosition #69 @169 RefTypeExpUse <Ivl:3 V04> BB04 regmask=[allInt] minReg=1>
V04
CHECKING LAST USES for block 4, liveout={V02 V03 V04 V05}
==============================
use: {V03 V04}
def: {V03 V04 V05}
NEW BLOCK BB05
Setting BB05 as the predecessor for determining incoming variable registers of BB04
<RefPosition #70 @169 RefTypeBB BB05 regmask=[] minReg=1>
DefList: { }
N171 ( 3, 3) [000111] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N173 ( 1, 1) [000105] ------------ * LCL_VAR long V03 tmp2 u:8 NA (last use) REG NA $149
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N175 ( 1, 1) [000107] -c---------- * CNS_INT long -8 REG NA $345
Contained
DefList: { }
N177 ( 3, 3) [000108] ------------ * ADD long REG NA $247
<RefPosition #71 @177 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 26: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #72 @178 RefTypeDef <Ivl:26> ADD BB05 regmask=[allInt] minReg=1>
Assigning related <L2> to <I26>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N177.t108. ADD }
N179 ( 3, 3) [000110] DA---------- * STORE_LCL_VAR long V03 tmp2 d:9 NA REG NA
<RefPosition #73 @179 RefTypeUse <Ivl:26> BB05 regmask=[allInt] minReg=1 last>
Assigning related <L2> to <I26>
<RefPosition #74 @180 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N181 ( 16, 13) [000127] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N183 ( 1, 1) [000114] ------------ * LCL_VAR int V05 tmp4 u:4 NA (last use) REG NA $283
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N185 ( 1, 1) [000115] -c---------- * CNS_INT int -1 REG NA $41
Contained
DefList: { }
N187 ( 3, 3) [000116] ------------ * ADD int REG NA $20f
<RefPosition #75 @187 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 27: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #76 @188 RefTypeDef <Ivl:27> ADD BB05 regmask=[allInt] minReg=1>
Assigning related <L4> to <I27>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N187.t116. ADD }
N189 ( 1, 1) [000113] ------------ * CNS_INT long 1 REG NA $346
Interval 28: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #77 @190 RefTypeDef <Ivl:28> CNS_INT BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N187.t116. ADD; N189.t113. CNS_INT }
N191 ( 10, 7) [000119] ------------ * LSH long REG NA $248
<RefPosition #78 @191 RefTypeUse <Ivl:28> BB05 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1 last>
<RefPosition #79 @191 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #80 @191 RefTypeUse <Ivl:27> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #81 @192 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1>
Interval 29: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #82 @192 RefTypeDef <Ivl:29> LSH BB05 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
Assigning related <I28> to <I29>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N191.t119. LSH }
N193 ( 1, 1) [000120] ------------ * LCL_VAR long V03 tmp2 u:9 NA REG NA $247
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N191.t119. LSH }
N195 ( 3, 2) [000121] *c-XG------- * IND long REG NA <l:$14a, c:$184>
Contained
DefList: { N191.t119. LSH }
N197 ( 14, 10) [000122] ---XG------- * HWIntrinsic long ParallelBitDeposit REG NA $480
<RefPosition #83 @197 RefTypeUse <Ivl:29> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #84 @197 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 30: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #85 @198 RefTypeDef <Ivl:30> HWIntrinsic BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 2 produce=1
DefList: { N197.t122. HWIntrinsic }
N199 ( 15, 11) [000123] ---XG------- * HWIntrinsic long TrailingZeroCount REG NA $481
<RefPosition #86 @199 RefTypeUse <Ivl:30> BB05 regmask=[allInt] minReg=1 last>
Interval 31: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #87 @200 RefTypeDef <Ivl:31> HWIntrinsic BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N199.t123. HWIntrinsic }
N201 ( 16, 13) [000124] ---XG------- * CAST int <- long REG NA $211
<RefPosition #88 @201 RefTypeUse <Ivl:31> BB05 regmask=[allInt] minReg=1 last>
Interval 32: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #89 @202 RefTypeDef <Ivl:32> CAST BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N201.t124. CAST }
N203 ( 16, 13) [000126] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2 NA REG NA
<RefPosition #90 @203 RefTypeUse <Ivl:32> BB05 regmask=[allInt] minReg=1 last>
Assigning related <L5> to <I32>
<RefPosition #91 @204 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N205 ( 1, 1) [000128] ------------ * LCL_VAR long V03 tmp2 u:9 NA (last use) REG NA $247
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N207 ( 1, 1) [000129] ------------ * LCL_VAR long V02 tmp1 u:2 NA (last use) REG NA <l:$140, c:$180>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N209 ( 3, 3) [000130] ------------ * SUB long REG NA <l:$249, c:$24a>
<RefPosition #92 @209 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #93 @209 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 33: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #94 @210 RefTypeDef <Ivl:33> SUB BB05 regmask=[allInt] minReg=1>
Assigning related <L2> to <I33>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N209.t130. SUB }
N211 (???,???) [000246] DA---------- * STORE_LCL_VAR long V07 rat0 NA REG NA
<RefPosition #95 @211 RefTypeUse <Ivl:33> BB05 regmask=[allInt] minReg=1 last>
Assigning related <L6> to <I33>
<RefPosition #96 @212 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N213 ( 1, 1) [000247] ------------ * LCL_VAR long V07 rat0 NA REG NA
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N215 ( 1, 1) [000248] -c---------- * CNS_INT int 63 REG NA
Contained
DefList: { }
N217 ( 3, 3) [000249] ------------ * RSH long REG NA
<RefPosition #97 @217 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 34: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #98 @218 RefTypeDef <Ivl:34> RSH BB05 regmask=[allInt] minReg=1>
Assigning related <L6> to <I34>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N217.t249. RSH }
N219 ( 1, 1) [000250] -c---------- * CNS_INT long 7 REG NA
Contained
DefList: { N217.t249. RSH }
N221 ( 5, 5) [000251] ------------ * AND long REG NA
<RefPosition #99 @221 RefTypeUse <Ivl:34> BB05 regmask=[allInt] minReg=1 last>
Interval 35: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #100 @222 RefTypeDef <Ivl:35> AND BB05 regmask=[allInt] minReg=1>
Assigning related <I34> to <I35>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N221.t251. AND }
N223 ( 1, 1) [000252] ------------ * LCL_VAR long V07 rat0 NA (last use) REG NA
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { N221.t251. AND }
N225 ( 7, 7) [000253] ------------ * ADD long REG NA
<RefPosition #101 @225 RefTypeUse <Ivl:35> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #102 @225 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 36: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #103 @226 RefTypeDef <Ivl:36> ADD BB05 regmask=[allInt] minReg=1>
Assigning related <I35> to <I36>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N225.t253. ADD }
N227 ( 1, 1) [000132] -c---------- * CNS_INT long 3 REG NA $340
Contained
DefList: { N225.t253. ADD }
N229 ( 9, 9) [000254] ------------ * RSH long REG NA
<RefPosition #104 @229 RefTypeUse <Ivl:36> BB05 regmask=[allInt] minReg=1 last>
Interval 37: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #105 @230 RefTypeDef <Ivl:37> RSH BB05 regmask=[allInt] minReg=1>
Assigning related <I36> to <I37>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N229.t254. RSH }
N231 ( 25, 9) [000166] ------------ * CAST int <- long REG NA <l:$212, c:$213>
<RefPosition #106 @231 RefTypeUse <Ivl:37> BB05 regmask=[allInt] minReg=1 last>
Interval 38: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #107 @232 RefTypeDef <Ivl:38> CAST BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N231.t166. CAST }
N233 ( 1, 1) [000135] -c---------- * CNS_INT int 6 REG NA $4b
Contained
DefList: { N231.t166. CAST }
N235 ( 27, 11) [000136] ------------ * LSH int REG NA <l:$214, c:$215>
<RefPosition #108 @235 RefTypeUse <Ivl:38> BB05 regmask=[allInt] minReg=1 last>
Interval 39: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #109 @236 RefTypeDef <Ivl:39> LSH BB05 regmask=[allInt] minReg=1>
Assigning related <I38> to <I39>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N235.t136. LSH }
N237 ( 1, 1) [000138] ------------ * LCL_VAR int V06 tmp5 u:2 NA (last use) REG NA $211
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { N235.t136. LSH }
N239 ( 29, 13) [000139] ------------ * ADD int REG NA <l:$216, c:$217>
<RefPosition #110 @239 RefTypeUse <Ivl:39> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #111 @239 RefTypeUse <Ivl:5 V06> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 40: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #112 @240 RefTypeDef <Ivl:40> ADD BB05 regmask=[allInt] minReg=1>
Assigning related <I39> to <I40>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N239.t139. ADD }
N241 ( 30, 14) [000010] ------------ * RETURN int REG NA $1c3
<RefPosition #113 @241 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #114 @241 RefTypeUse <Ivl:40> BB05 regmask=[rax] minReg=1 last fixed>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
CHECKING LAST USES for block 5, liveout={}
==============================
use: {V02 V03 V05}
def: {V03 V06 V07}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) RefPositions {#0@0 #7@15} physReg:rdi Preferences=[rdi] RelatedInterval <L3>[00000000024ECF58]
Interval 1: (V02) RefPositions {#6@10 #9@21 #93@209} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 2: (V03) RefPositions {#10@22 #13@41 #17@51 #24@63 #31@75 #43@93 #46@96 #55@141 #64@155 #67@158 #71@177 #74@180 #84@197 #92@209} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 3: (V04) RefPositions {#8@16 #11@29 #38@83 #42@86 #47@103 #49@113 #53@131 #63@148 #68@165 #69@169} physReg:NA Preferences=[allInt] RelatedInterval <L4>[00000000024ECFA8]
Interval 4: (V05) RefPositions {#50@114 #51@121 #54@132 #59@145 #75@187} physReg:NA Preferences=[allInt]
Interval 5: (V06) RefPositions {#91@204 #111@239} physReg:NA Preferences=[allInt]
Interval 6: (V07) RefPositions {#96@212 #97@217 #102@225} physReg:NA Preferences=[allInt]
Interval 7: (constant) RefPositions {#2@6 #3@7} physReg:NA Preferences=[allInt]
Interval 8: RefPositions {#4@8 #5@9} physReg:NA Preferences=[allInt] RelatedInterval <L1>[00000000024ECEB8]
Interval 9: RefPositions {#14@42 #15@43} physReg:NA Preferences=[allInt]
Interval 10: RefPositions {#16@44 #21@55} physReg:NA Preferences=[allInt]
Interval 11: RefPositions {#18@52 #19@53} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {#20@54 #22@55} physReg:NA Preferences=[allInt]
Interval 13: RefPositions {#23@56 #28@67} physReg:NA Preferences=[allInt] RelatedInterval <I10>[00000000024EDB98]
Interval 14: RefPositions {#25@64 #26@65} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#27@66 #29@67} physReg:NA Preferences=[allInt]
Interval 16: RefPositions {#30@68 #35@79} physReg:NA Preferences=[allInt] RelatedInterval <I13>[00000000024EDFC8]
Interval 17: RefPositions {#32@76 #33@77} physReg:NA Preferences=[allInt]
Interval 18: RefPositions {#34@78 #36@79} physReg:NA Preferences=[allInt]
Interval 19: RefPositions {#37@80 #39@83} physReg:NA Preferences=[allInt] RelatedInterval <I16>[00000000024EE3F8]
Interval 20: (interfering uses) RefPositions {#40@84 #41@85} physReg:NA Preferences=[allInt] RelatedInterval <L3>[00000000024ECF58]
Interval 21: RefPositions {#44@94 #45@95} physReg:NA Preferences=[allInt] RelatedInterval <L2>[00000000024ECF08]
Interval 22: RefPositions {#56@142 #57@143} physReg:NA Preferences=[allInt]
Interval 23: RefPositions {#58@144 #60@145} physReg:NA Preferences=[allInt]
Interval 24: (interfering uses) RefPositions {#61@146 #62@147} physReg:NA Preferences=[allInt] RelatedInterval <L3>[00000000024ECF58]
Interval 25: RefPositions {#65@156 #66@157} physReg:NA Preferences=[allInt] RelatedInterval <L2>[00000000024ECF08]
Interval 26: RefPositions {#72@178 #73@179} physReg:NA Preferences=[allInt] RelatedInterval <L2>[00000000024ECF08]
Interval 27: RefPositions {#76@188 #80@191} physReg:NA Preferences=[rcx] RelatedInterval <L4>[00000000024ECFA8]
Interval 28: (constant) RefPositions {#77@190 #78@191} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 29: (interfering uses) RefPositions {#82@192 #83@197} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15] RelatedInterval <I28>[00000000024F6198]
Interval 30: RefPositions {#85@198 #86@199} physReg:NA Preferences=[allInt]
Interval 31: RefPositions {#87@200 #88@201} physReg:NA Preferences=[allInt]
Interval 32: RefPositions {#89@202 #90@203} physReg:NA Preferences=[allInt] RelatedInterval <L5>[00000000024ECFF8]
Interval 33: (interfering uses) RefPositions {#94@210 #95@211} physReg:NA Preferences=[allInt] RelatedInterval <L6>[00000000024ED048]
Interval 34: RefPositions {#98@218 #99@221} physReg:NA Preferences=[allInt] RelatedInterval <L6>[00000000024ED048]
Interval 35: RefPositions {#100@222 #101@225} physReg:NA Preferences=[allInt] RelatedInterval <I34>[00000000024F6C38]
Interval 36: RefPositions {#103@226 #104@229} physReg:NA Preferences=[allInt] RelatedInterval <I35>[00000000024F6D88]
Interval 37: RefPositions {#105@230 #106@231} physReg:NA Preferences=[allInt] RelatedInterval <I36>[00000000024F6F18]
Interval 38: RefPositions {#107@232 #108@235} physReg:NA Preferences=[allInt]
Interval 39: RefPositions {#109@236 #110@239} physReg:NA Preferences=[allInt] RelatedInterval <I38>[00000000024F7178]
Interval 40: RefPositions {#112@240 #114@241} physReg:NA Preferences=[rax] RelatedInterval <I39>[00000000024F72C8]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @6 RefTypeDef <Ivl:7> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #3 @7 RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #4 @8 RefTypeDef <Ivl:8> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #5 @9 RefTypeUse <Ivl:8> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @29 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional>
<RefPosition #12 @33 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #13 @41 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #14 @42 RefTypeDef <Ivl:9> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #15 @43 RefTypeUse <Ivl:9> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #16 @44 RefTypeDef <Ivl:10> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #18 @52 RefTypeDef <Ivl:11> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #19 @53 RefTypeUse <Ivl:11> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #20 @54 RefTypeDef <Ivl:12> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #21 @55 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #22 @55 RefTypeUse <Ivl:12> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #23 @56 RefTypeDef <Ivl:13> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #24 @63 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #25 @64 RefTypeDef <Ivl:14> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #26 @65 RefTypeUse <Ivl:14> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #27 @66 RefTypeDef <Ivl:15> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #28 @67 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #29 @67 RefTypeUse <Ivl:15> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #30 @68 RefTypeDef <Ivl:16> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #31 @75 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @76 RefTypeDef <Ivl:17> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #33 @77 RefTypeUse <Ivl:17> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #34 @78 RefTypeDef <Ivl:18> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #35 @79 RefTypeUse <Ivl:16> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #36 @79 RefTypeUse <Ivl:18> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #37 @80 RefTypeDef <Ivl:19> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #38 @83 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #39 @83 RefTypeUse <Ivl:19> BB02 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #40 @84 RefTypeDef <Ivl:20> SUB BB02 regmask=[allInt] minReg=1>
<RefPosition #41 @85 RefTypeUse <Ivl:20> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #42 @86 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #43 @93 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #44 @94 RefTypeDef <Ivl:21> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #45 @95 RefTypeUse <Ivl:21> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #46 @96 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #47 @103 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 regOptional>
<RefPosition #48 @107 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #49 @113 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #50 @114 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #51 @121 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[allInt] minReg=1 regOptional>
<RefPosition #52 @125 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #53 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #54 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #55 @141 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #56 @142 RefTypeDef <Ivl:22> HWIntrinsic BB04 regmask=[allInt] minReg=1>
<RefPosition #57 @143 RefTypeUse <Ivl:22> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #58 @144 RefTypeDef <Ivl:23> CAST BB04 regmask=[allInt] minReg=1>
<RefPosition #59 @145 RefTypeUse <Ivl:4 V05> LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #60 @145 RefTypeUse <Ivl:23> BB04 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #61 @146 RefTypeDef <Ivl:24> SUB BB04 regmask=[allInt] minReg=1>
<RefPosition #62 @147 RefTypeUse <Ivl:24> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #63 @148 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #64 @155 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #65 @156 RefTypeDef <Ivl:25> ADD BB04 regmask=[allInt] minReg=1>
<RefPosition #66 @157 RefTypeUse <Ivl:25> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #67 @158 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #68 @165 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 regOptional>
<RefPosition #69 @169 RefTypeExpUse <Ivl:3 V04> BB04 regmask=[allInt] minReg=1>
<RefPosition #70 @169 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #71 @177 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #72 @178 RefTypeDef <Ivl:26> ADD BB05 regmask=[allInt] minReg=1>
<RefPosition #73 @179 RefTypeUse <Ivl:26> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #74 @180 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #75 @187 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #76 @188 RefTypeDef <Ivl:27> ADD BB05 regmask=[rcx] minReg=1>
<RefPosition #77 @190 RefTypeDef <Ivl:28> CNS_INT BB05 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
<RefPosition #78 @191 RefTypeUse <Ivl:28> BB05 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1 last>
<RefPosition #79 @191 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #80 @191 RefTypeUse <Ivl:27> BB05 regmask=[rcx] minReg=1 last fixed delay>
<RefPosition #81 @192 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #82 @192 RefTypeDef <Ivl:29> LSH BB05 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
<RefPosition #83 @197 RefTypeUse <Ivl:29> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #84 @197 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #85 @198 RefTypeDef <Ivl:30> HWIntrinsic BB05 regmask=[allInt] minReg=1>
<RefPosition #86 @199 RefTypeUse <Ivl:30> BB05 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #87 @200 RefTypeDef <Ivl:31> HWIntrinsic BB05 regmask=[allInt] minReg=1>
<RefPosition #88 @201 RefTypeUse <Ivl:31> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #89 @202 RefTypeDef <Ivl:32> CAST BB05 regmask=[allInt] minReg=1>
<RefPosition #90 @203 RefTypeUse <Ivl:32> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #91 @204 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #92 @209 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #93 @209 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #94 @210 RefTypeDef <Ivl:33> SUB BB05 regmask=[allInt] minReg=1>
<RefPosition #95 @211 RefTypeUse <Ivl:33> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #96 @212 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #97 @217 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #98 @218 RefTypeDef <Ivl:34> RSH BB05 regmask=[allInt] minReg=1>
<RefPosition #99 @221 RefTypeUse <Ivl:34> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #100 @222 RefTypeDef <Ivl:35> AND BB05 regmask=[allInt] minReg=1>
<RefPosition #101 @225 RefTypeUse <Ivl:35> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #102 @225 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #103 @226 RefTypeDef <Ivl:36> ADD BB05 regmask=[allInt] minReg=1>
<RefPosition #104 @229 RefTypeUse <Ivl:36> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #105 @230 RefTypeDef <Ivl:37> RSH BB05 regmask=[allInt] minReg=1>
<RefPosition #106 @231 RefTypeUse <Ivl:37> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #107 @232 RefTypeDef <Ivl:38> CAST BB05 regmask=[allInt] minReg=1>
<RefPosition #108 @235 RefTypeUse <Ivl:38> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #109 @236 RefTypeDef <Ivl:39> LSH BB05 regmask=[allInt] minReg=1>
<RefPosition #110 @239 RefTypeUse <Ivl:39> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #111 @239 RefTypeUse <Ivl:5 V06> LCL_VAR BB05 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #112 @240 RefTypeDef <Ivl:40> ADD BB05 regmask=[rax] minReg=1>
<RefPosition #113 @241 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #114 @241 RefTypeUse <Ivl:40> BB05 regmask=[rax] minReg=1 last fixed>
-----------------
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @29 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional>
<RefPosition #38 @83 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #42 @86 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #47 @103 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 regOptional>
<RefPosition #49 @113 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #53 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #63 @148 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #68 @165 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 regOptional>
<RefPosition #69 @169 RefTypeExpUse <Ivl:3 V04> BB04 regmask=[allInt] minReg=1>
-----------------
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #13 @41 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #24 @63 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #31 @75 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #43 @93 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #46 @96 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #55 @141 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #64 @155 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #67 @158 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #71 @177 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #74 @180 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #84 @197 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #92 @209 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #50 @114 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #51 @121 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[allInt] minReg=1 regOptional>
<RefPosition #54 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #59 @145 RefTypeUse <Ivl:4 V05> LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #75 @187 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #93 @209 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[allInt] minReg=1 last delay regOptional>
-----------------
<RefPosition #96 @212 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #97 @217 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #102 @225 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1 last regOptional>
-----------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #91 @204 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #111 @239 RefTypeUse <Ivl:5 V06> LCL_VAR BB05 regmask=[allInt] minReg=1 last regOptional>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V00
BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N003. IL_OFFSET IL offset: 0x0 REG NA
N005. CNS_INT(h) 0x7f08ab884498 static Fseq[_bits] REG NA
Def:<I7>(#2)
N007. IND
Use:<I7>(#3) *
Def:<I8>(#4) Pref:<L1>
N009. V02(L1)
Use:<I8>(#5) *
Def:<L1>(#6)
N011. IL_OFFSET IL offset: 0x0 REG NA
N013. V00(L0)
N015. V04(L3)
Use:<L0>(#7) *
Def:<L3>(#8) Pref:<L4>
N017. IL_OFFSET IL offset: 0x0 REG NA
N019. V02(L1)
N021. V03(L2)
Use:<L1>(#9)
Def:<L2>(#10)
N023. IL_OFFSET IL offset: 0x0 REG NA
N025. V04(L3)
N027. CNS_INT 256 REG NA
N029. LT
Use:<L3>(#11)
N031. JTRUE
BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
=====
N035. IL_OFFSET IL offset: 0x0 REG NA
N037. V03(L2)
N039. IND
N041. HWIntrinsic
Use:<L2>(#13)
Def:<I9>(#14)
N043. CAST
Use:<I9>(#15) *
Def:<I10>(#16)
N045. V03(L2)
N047. LEA(b+8)
N049. IND
N051. HWIntrinsic
Use:<L2>(#17)
Def:<I11>(#18)
N053. CAST
Use:<I11>(#19) *
Def:<I12>(#20)
N055. ADD
Use:<I10>(#21) *
Use:<I12>(#22) *
Def:<I13>(#23) Pref:<I10>
N057. V03(L2)
N059. LEA(b+16)
N061. IND
N063. HWIntrinsic
Use:<L2>(#24)
Def:<I14>(#25)
N065. CAST
Use:<I14>(#26) *
Def:<I15>(#27)
N067. ADD
Use:<I13>(#28) *
Use:<I15>(#29) *
Def:<I16>(#30) Pref:<I13>
N069. V03(L2)
N071. LEA(b+24)
N073. IND
N075. HWIntrinsic
Use:<L2>(#31)
Def:<I17>(#32)
N077. CAST
Use:<I17>(#33) *
Def:<I18>(#34)
N079. ADD
Use:<I16>(#35) *
Use:<I18>(#36) *
Def:<I19>(#37) Pref:<I16>
N081. V04(L3)
N083. SUB
Use:<L3>(#38) *
Use:<I19>(#39) *
Def:<I20>(#40) Pref:<L3>
N085. V04(L3)
Use:<I20>(#41) *
Def:<L3>(#42) Pref:<L4>
N087. IL_OFFSET IL offset: 0x0 REG NA
N089. V03(L2)
N091. CNS_INT 32 REG NA
N093. ADD
Use:<L2>(#43) *
Def:<I21>(#44) Pref:<L2>
N095. V03(L2)
Use:<I21>(#45) *
Def:<L2>(#46)
N097. IL_OFFSET IL offset: 0x0 REG NA
N099. V04(L3)
N101. CNS_INT 256 REG NA
N103. GE
Use:<L3>(#47)
N105. JTRUE
BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
=====
N109. IL_OFFSET IL offset: 0x0 REG NA
N111. V04(L3)
N113. V05(L4)
Use:<L3>(#49)
Def:<L4>(#50)
N115. IL_OFFSET IL offset: 0x0 REG NA
N117. V05(L4)
N119. CNS_INT 0 REG NA
N121. LE
Use:<L4>(#51)
N123. JTRUE
BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
=====
N127. IL_OFFSET IL offset: 0x0 REG NA
N129. V04(L3)
N131. V05(L4)
Use:<L3>(#53) *
Def:<L4>(#54)
N133. IL_OFFSET IL offset: 0x0 REG NA
N135. V05(L4)
N137. V03(L2)
N139. IND
N141. HWIntrinsic
Use:<L2>(#55)
Def:<I22>(#56)
N143. CAST
Use:<I22>(#57) *
Def:<I23>(#58)
N145. SUB
Use:<L4>(#59)
Use:<I23>(#60) *
Def:<I24>(#61) Pref:<L3>
N147. V04(L3)
Use:<I24>(#62) *
Def:<L3>(#63) Pref:<L4>
N149. IL_OFFSET IL offset: 0x0 REG NA
N151. V03(L2)
N153. CNS_INT 8 REG NA
N155. ADD
Use:<L2>(#64) *
Def:<I25>(#65) Pref:<L2>
N157. V03(L2)
Use:<I25>(#66) *
Def:<L2>(#67)
N159. IL_OFFSET IL offset: 0x0 REG NA
N161. V04(L3)
N163. CNS_INT 0 REG NA
N165. GT
Use:<L3>(#68)
N167. JTRUE
Exposed use of V04 at #69
BB05 [000..001) (return), preds={BB03,BB04} succs={}
=====
N171. IL_OFFSET IL offset: 0x0 REG NA
N173. V03(L2)
N175. CNS_INT -8 REG NA
N177. ADD
Use:<L2>(#71) *
Def:<I26>(#72) Pref:<L2>
N179. V03(L2)
Use:<I26>(#73) *
Def:<L2>(#74)
N181. IL_OFFSET IL offset: 0x0 REG NA
N183. V05(L4)
N185. CNS_INT -1 REG NA
N187. ADD
Use:<L4>(#75) *
Def:<I27>(#76) Pref:<L4>
N189. CNS_INT 1 REG NA
Def:<I28>(#77)
N191. LSH
Use:<I28>(#78) *
Use:<I27>(#80) Fixed:rcx(#79) *
Kill: rcx
Def:<I29>(#82) Pref:<I28>
N193. V03(L2)
N195. IND
N197. HWIntrinsic
Use:<I29>(#83) *
Use:<L2>(#84)
Def:<I30>(#85)
N199. HWIntrinsic
Use:<I30>(#86) *
Def:<I31>(#87)
N201. CAST
Use:<I31>(#88) *
Def:<I32>(#89) Pref:<L5>
N203. V06(L5)
Use:<I32>(#90) *
Def:<L5>(#91)
N205. V03(L2)
N207. V02(L1)
N209. SUB
Use:<L2>(#92) *
Use:<L1>(#93) *
Def:<I33>(#94) Pref:<L6>
N211. V07(L6)
Use:<I33>(#95) *
Def:<L6>(#96)
N213. V07(L6)
N215. CNS_INT 63 REG NA
N217. RSH
Use:<L6>(#97)
Def:<I34>(#98) Pref:<L6>
N219. CNS_INT 7 REG NA
N221. AND
Use:<I34>(#99) *
Def:<I35>(#100) Pref:<I34>
N223. V07(L6)
N225. ADD
Use:<I35>(#101) *
Use:<L6>(#102) *
Def:<I36>(#103) Pref:<I35>
N227. CNS_INT 3 REG NA
N229. RSH
Use:<I36>(#104) *
Def:<I37>(#105) Pref:<I36>
N231. CAST
Use:<I37>(#106) *
Def:<I38>(#107)
N233. CNS_INT 6 REG NA
N235. LSH
Use:<I38>(#108) *
Def:<I39>(#109) Pref:<I38>
N237. V06(L5)
N239. ADD
Use:<I39>(#110) *
Use:<L5>(#111) *
Def:<I40>(#112) Pref:<I39>
N241. RETURN
Use:<I40>(#114) Fixed:rax(#113) *
Linear scan intervals after buildIntervals:
Interval 0: (V00) RefPositions {#0@0 #7@15} physReg:rdi Preferences=[rdi] RelatedInterval <L3>[00000000024ECF58]
Interval 1: (V02) RefPositions {#6@10 #9@21 #93@209} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 2: (V03) RefPositions {#10@22 #13@41 #17@51 #24@63 #31@75 #43@93 #46@96 #55@141 #64@155 #67@158 #71@177 #74@180 #84@197 #92@209} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 3: (V04) RefPositions {#8@16 #11@29 #38@83 #42@86 #47@103 #49@113 #53@131 #63@148 #68@165 #69@169} physReg:NA Preferences=[allInt] RelatedInterval <L4>[00000000024ECFA8]
Interval 4: (V05) RefPositions {#50@114 #51@121 #54@132 #59@145 #75@187} physReg:NA Preferences=[allInt]
Interval 5: (V06) RefPositions {#91@204 #111@239} physReg:NA Preferences=[allInt]
Interval 6: (V07) RefPositions {#96@212 #97@217 #102@225} physReg:NA Preferences=[allInt]
Interval 7: (constant) RefPositions {#2@6 #3@7} physReg:NA Preferences=[allInt]
Interval 8: RefPositions {#4@8 #5@9} physReg:NA Preferences=[allInt] RelatedInterval <L1>[00000000024ECEB8]
Interval 9: RefPositions {#14@42 #15@43} physReg:NA Preferences=[allInt]
Interval 10: RefPositions {#16@44 #21@55} physReg:NA Preferences=[allInt]
Interval 11: RefPositions {#18@52 #19@53} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {#20@54 #22@55} physReg:NA Preferences=[allInt]
Interval 13: RefPositions {#23@56 #28@67} physReg:NA Preferences=[allInt] RelatedInterval <I10>[00000000024EDB98]
Interval 14: RefPositions {#25@64 #26@65} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#27@66 #29@67} physReg:NA Preferences=[allInt]
Interval 16: RefPositions {#30@68 #35@79} physReg:NA Preferences=[allInt] RelatedInterval <I13>[00000000024EDFC8]
Interval 17: RefPositions {#32@76 #33@77} physReg:NA Preferences=[allInt]
Interval 18: RefPositions {#34@78 #36@79} physReg:NA Preferences=[allInt]
Interval 19: RefPositions {#37@80 #39@83} physReg:NA Preferences=[allInt] RelatedInterval <I16>[00000000024EE3F8]
Interval 20: (interfering uses) RefPositions {#40@84 #41@85} physReg:NA Preferences=[allInt] RelatedInterval <L3>[00000000024ECF58]
Interval 21: RefPositions {#44@94 #45@95} physReg:NA Preferences=[allInt] RelatedInterval <L2>[00000000024ECF08]
Interval 22: RefPositions {#56@142 #57@143} physReg:NA Preferences=[allInt]
Interval 23: RefPositions {#58@144 #60@145} physReg:NA Preferences=[allInt]
Interval 24: (interfering uses) RefPositions {#61@146 #62@147} physReg:NA Preferences=[allInt] RelatedInterval <L3>[00000000024ECF58]
Interval 25: RefPositions {#65@156 #66@157} physReg:NA Preferences=[allInt] RelatedInterval <L2>[00000000024ECF08]
Interval 26: RefPositions {#72@178 #73@179} physReg:NA Preferences=[allInt] RelatedInterval <L2>[00000000024ECF08]
Interval 27: RefPositions {#76@188 #80@191} physReg:NA Preferences=[rcx] RelatedInterval <L4>[00000000024ECFA8]
Interval 28: (constant) RefPositions {#77@190 #78@191} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 29: (interfering uses) RefPositions {#82@192 #83@197} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15] RelatedInterval <I28>[00000000024F6198]
Interval 30: RefPositions {#85@198 #86@199} physReg:NA Preferences=[allInt]
Interval 31: RefPositions {#87@200 #88@201} physReg:NA Preferences=[allInt]
Interval 32: RefPositions {#89@202 #90@203} physReg:NA Preferences=[allInt] RelatedInterval <L5>[00000000024ECFF8]
Interval 33: (interfering uses) RefPositions {#94@210 #95@211} physReg:NA Preferences=[allInt] RelatedInterval <L6>[00000000024ED048]
Interval 34: RefPositions {#98@218 #99@221} physReg:NA Preferences=[allInt] RelatedInterval <L6>[00000000024ED048]
Interval 35: RefPositions {#100@222 #101@225} physReg:NA Preferences=[allInt] RelatedInterval <I34>[00000000024F6C38]
Interval 36: RefPositions {#103@226 #104@229} physReg:NA Preferences=[allInt] RelatedInterval <I35>[00000000024F6D88]
Interval 37: RefPositions {#105@230 #106@231} physReg:NA Preferences=[allInt] RelatedInterval <I36>[00000000024F6F18]
Interval 38: RefPositions {#107@232 #108@235} physReg:NA Preferences=[allInt]
Interval 39: RefPositions {#109@236 #110@239} physReg:NA Preferences=[allInt] RelatedInterval <I38>[00000000024F7178]
Interval 40: RefPositions {#112@240 #114@241} physReg:NA Preferences=[rax] RelatedInterval <I39>[00000000024F72C8]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) RefPositions {#0@0 #7@15} physReg:rdi Preferences=[rdi] RelatedInterval <L3>[00000000024ECF58]
Interval 1: (V02) RefPositions {#6@10 #9@21 #93@209} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 2: (V03) RefPositions {#10@22 #13@41 #17@51 #24@63 #31@75 #43@93 #46@96 #55@141 #64@155 #67@158 #71@177 #74@180 #84@197 #92@209} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 3: (V04) RefPositions {#8@16 #11@29 #38@83 #42@86 #47@103 #49@113 #53@131 #63@148 #68@165 #69@169} physReg:NA Preferences=[allInt] RelatedInterval <L4>[00000000024ECFA8]
Interval 4: (V05) RefPositions {#50@114 #51@121 #54@132 #59@145 #75@187} physReg:NA Preferences=[allInt]
Interval 5: (V06) RefPositions {#91@204 #111@239} physReg:NA Preferences=[allInt]
Interval 6: (V07) RefPositions {#96@212 #97@217 #102@225} physReg:NA Preferences=[allInt]
Interval 7: (constant) RefPositions {#2@6 #3@7} physReg:NA Preferences=[allInt]
Interval 8: RefPositions {#4@8 #5@9} physReg:NA Preferences=[allInt] RelatedInterval <L1>[00000000024ECEB8]
Interval 9: RefPositions {#14@42 #15@43} physReg:NA Preferences=[allInt]
Interval 10: RefPositions {#16@44 #21@55} physReg:NA Preferences=[allInt]
Interval 11: RefPositions {#18@52 #19@53} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {#20@54 #22@55} physReg:NA Preferences=[allInt]
Interval 13: RefPositions {#23@56 #28@67} physReg:NA Preferences=[allInt] RelatedInterval <I10>[00000000024EDB98]
Interval 14: RefPositions {#25@64 #26@65} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#27@66 #29@67} physReg:NA Preferences=[allInt]
Interval 16: RefPositions {#30@68 #35@79} physReg:NA Preferences=[allInt] RelatedInterval <I13>[00000000024EDFC8]
Interval 17: RefPositions {#32@76 #33@77} physReg:NA Preferences=[allInt]
Interval 18: RefPositions {#34@78 #36@79} physReg:NA Preferences=[allInt]
Interval 19: RefPositions {#37@80 #39@83} physReg:NA Preferences=[allInt] RelatedInterval <I16>[00000000024EE3F8]
Interval 20: (interfering uses) RefPositions {#40@84 #41@85} physReg:NA Preferences=[allInt] RelatedInterval <L3>[00000000024ECF58]
Interval 21: RefPositions {#44@94 #45@95} physReg:NA Preferences=[allInt] RelatedInterval <L2>[00000000024ECF08]
Interval 22: RefPositions {#56@142 #57@143} physReg:NA Preferences=[allInt]
Interval 23: RefPositions {#58@144 #60@145} physReg:NA Preferences=[allInt]
Interval 24: (interfering uses) RefPositions {#61@146 #62@147} physReg:NA Preferences=[allInt] RelatedInterval <L3>[00000000024ECF58]
Interval 25: RefPositions {#65@156 #66@157} physReg:NA Preferences=[allInt] RelatedInterval <L2>[00000000024ECF08]
Interval 26: RefPositions {#72@178 #73@179} physReg:NA Preferences=[allInt] RelatedInterval <L2>[00000000024ECF08]
Interval 27: RefPositions {#76@188 #80@191} physReg:NA Preferences=[rcx] RelatedInterval <L4>[00000000024ECFA8]
Interval 28: (constant) RefPositions {#77@190 #78@191} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 29: (interfering uses) RefPositions {#82@192 #83@197} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15] RelatedInterval <I28>[00000000024F6198]
Interval 30: RefPositions {#85@198 #86@199} physReg:NA Preferences=[allInt]
Interval 31: RefPositions {#87@200 #88@201} physReg:NA Preferences=[allInt]
Interval 32: RefPositions {#89@202 #90@203} physReg:NA Preferences=[allInt] RelatedInterval <L5>[00000000024ECFF8]
Interval 33: (interfering uses) RefPositions {#94@210 #95@211} physReg:NA Preferences=[allInt] RelatedInterval <L6>[00000000024ED048]
Interval 34: RefPositions {#98@218 #99@221} physReg:NA Preferences=[allInt] RelatedInterval <L6>[00000000024ED048]
Interval 35: RefPositions {#100@222 #101@225} physReg:NA Preferences=[allInt] RelatedInterval <I34>[00000000024F6C38]
Interval 36: RefPositions {#103@226 #104@229} physReg:NA Preferences=[allInt] RelatedInterval <I35>[00000000024F6D88]
Interval 37: RefPositions {#105@230 #106@231} physReg:NA Preferences=[allInt] RelatedInterval <I36>[00000000024F6F18]
Interval 38: RefPositions {#107@232 #108@235} physReg:NA Preferences=[allInt]
Interval 39: RefPositions {#109@236 #110@239} physReg:NA Preferences=[allInt] RelatedInterval <I38>[00000000024F7178]
Interval 40: RefPositions {#112@240 #114@241} physReg:NA Preferences=[rax] RelatedInterval <I39>[00000000024F72C8]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @6 RefTypeDef <Ivl:7> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #3 @7 RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #4 @8 RefTypeDef <Ivl:8> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #5 @9 RefTypeUse <Ivl:8> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @29 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional>
<RefPosition #12 @33 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #13 @41 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #14 @42 RefTypeDef <Ivl:9> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #15 @43 RefTypeUse <Ivl:9> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #16 @44 RefTypeDef <Ivl:10> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #18 @52 RefTypeDef <Ivl:11> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #19 @53 RefTypeUse <Ivl:11> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #20 @54 RefTypeDef <Ivl:12> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #21 @55 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #22 @55 RefTypeUse <Ivl:12> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #23 @56 RefTypeDef <Ivl:13> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #24 @63 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #25 @64 RefTypeDef <Ivl:14> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #26 @65 RefTypeUse <Ivl:14> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #27 @66 RefTypeDef <Ivl:15> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #28 @67 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #29 @67 RefTypeUse <Ivl:15> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #30 @68 RefTypeDef <Ivl:16> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #31 @75 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @76 RefTypeDef <Ivl:17> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #33 @77 RefTypeUse <Ivl:17> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #34 @78 RefTypeDef <Ivl:18> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #35 @79 RefTypeUse <Ivl:16> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #36 @79 RefTypeUse <Ivl:18> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #37 @80 RefTypeDef <Ivl:19> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #38 @83 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #39 @83 RefTypeUse <Ivl:19> BB02 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #40 @84 RefTypeDef <Ivl:20> SUB BB02 regmask=[allInt] minReg=1>
<RefPosition #41 @85 RefTypeUse <Ivl:20> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #42 @86 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #43 @93 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #44 @94 RefTypeDef <Ivl:21> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #45 @95 RefTypeUse <Ivl:21> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #46 @96 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #47 @103 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 regOptional>
<RefPosition #48 @107 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #49 @113 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #50 @114 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #51 @121 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[allInt] minReg=1 regOptional>
<RefPosition #52 @125 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #53 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #54 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #55 @141 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #56 @142 RefTypeDef <Ivl:22> HWIntrinsic BB04 regmask=[allInt] minReg=1>
<RefPosition #57 @143 RefTypeUse <Ivl:22> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #58 @144 RefTypeDef <Ivl:23> CAST BB04 regmask=[allInt] minReg=1>
<RefPosition #59 @145 RefTypeUse <Ivl:4 V05> LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #60 @145 RefTypeUse <Ivl:23> BB04 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #61 @146 RefTypeDef <Ivl:24> SUB BB04 regmask=[allInt] minReg=1>
<RefPosition #62 @147 RefTypeUse <Ivl:24> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #63 @148 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #64 @155 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #65 @156 RefTypeDef <Ivl:25> ADD BB04 regmask=[allInt] minReg=1>
<RefPosition #66 @157 RefTypeUse <Ivl:25> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #67 @158 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #68 @165 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 regOptional>
<RefPosition #69 @169 RefTypeExpUse <Ivl:3 V04> BB04 regmask=[allInt] minReg=1>
<RefPosition #70 @169 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #71 @177 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #72 @178 RefTypeDef <Ivl:26> ADD BB05 regmask=[allInt] minReg=1>
<RefPosition #73 @179 RefTypeUse <Ivl:26> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #74 @180 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #75 @187 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #76 @188 RefTypeDef <Ivl:27> ADD BB05 regmask=[rcx] minReg=1>
<RefPosition #77 @190 RefTypeDef <Ivl:28> CNS_INT BB05 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
<RefPosition #78 @191 RefTypeUse <Ivl:28> BB05 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1 last>
<RefPosition #79 @191 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #80 @191 RefTypeUse <Ivl:27> BB05 regmask=[rcx] minReg=1 last fixed delay>
<RefPosition #81 @192 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #82 @192 RefTypeDef <Ivl:29> LSH BB05 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
<RefPosition #83 @197 RefTypeUse <Ivl:29> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #84 @197 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #85 @198 RefTypeDef <Ivl:30> HWIntrinsic BB05 regmask=[allInt] minReg=1>
<RefPosition #86 @199 RefTypeUse <Ivl:30> BB05 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #87 @200 RefTypeDef <Ivl:31> HWIntrinsic BB05 regmask=[allInt] minReg=1>
<RefPosition #88 @201 RefTypeUse <Ivl:31> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #89 @202 RefTypeDef <Ivl:32> CAST BB05 regmask=[allInt] minReg=1>
<RefPosition #90 @203 RefTypeUse <Ivl:32> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #91 @204 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #92 @209 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #93 @209 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #94 @210 RefTypeDef <Ivl:33> SUB BB05 regmask=[allInt] minReg=1>
<RefPosition #95 @211 RefTypeUse <Ivl:33> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #96 @212 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #97 @217 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #98 @218 RefTypeDef <Ivl:34> RSH BB05 regmask=[allInt] minReg=1>
<RefPosition #99 @221 RefTypeUse <Ivl:34> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #100 @222 RefTypeDef <Ivl:35> AND BB05 regmask=[allInt] minReg=1>
<RefPosition #101 @225 RefTypeUse <Ivl:35> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #102 @225 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #103 @226 RefTypeDef <Ivl:36> ADD BB05 regmask=[allInt] minReg=1>
<RefPosition #104 @229 RefTypeUse <Ivl:36> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #105 @230 RefTypeDef <Ivl:37> RSH BB05 regmask=[allInt] minReg=1>
<RefPosition #106 @231 RefTypeUse <Ivl:37> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #107 @232 RefTypeDef <Ivl:38> CAST BB05 regmask=[allInt] minReg=1>
<RefPosition #108 @235 RefTypeUse <Ivl:38> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #109 @236 RefTypeDef <Ivl:39> LSH BB05 regmask=[allInt] minReg=1>
<RefPosition #110 @239 RefTypeUse <Ivl:39> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #111 @239 RefTypeUse <Ivl:5 V06> LCL_VAR BB05 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #112 @240 RefTypeDef <Ivl:40> ADD BB05 regmask=[rax] minReg=1>
<RefPosition #113 @241 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #114 @241 RefTypeUse <Ivl:40> BB05 regmask=[rax] minReg=1 last fixed>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
--- V01
--- V02
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #93 @209 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[allInt] minReg=1 last delay regOptional>
--- V03
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #13 @41 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #24 @63 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #31 @75 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #43 @93 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #46 @96 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #55 @141 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #64 @155 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #67 @158 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #71 @177 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #74 @180 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #84 @197 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #92 @209 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
--- V04
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @29 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional>
<RefPosition #38 @83 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #42 @86 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #47 @103 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 regOptional>
<RefPosition #49 @113 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #53 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #63 @148 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #68 @165 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 regOptional>
<RefPosition #69 @169 RefTypeExpUse <Ivl:3 V04> BB04 regmask=[allInt] minReg=1>
--- V05
<RefPosition #50 @114 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #51 @121 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[allInt] minReg=1 regOptional>
<RefPosition #54 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #59 @145 RefTypeUse <Ivl:4 V05> LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #75 @187 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
--- V06
<RefPosition #91 @204 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #111 @239 RefTypeUse <Ivl:5 V06> LCL_VAR BB05 regmask=[allInt] minReg=1 last regOptional>
--- V07
<RefPosition #96 @212 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #97 @217 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #102 @225 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1 last regOptional>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which
may increase during allocation, in which case additional columns will appear. Registers which are
not marked modified have ---- in their column.
--------------------------------+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |r12 |r13 |
--------------------------------+----+----+----+----+----+
| | | | | |
--------------------------------+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+
0.#0 V0 Parm Keep rdi | | | |V0 a| | |
1.#1 BB1 PredBB0 | | | |V0 a| | |
6.#2 C7 Def Alloc rcx | |C7 a| |V0 a| | |
7.#3 C7 Use * Keep rcx | |C7 a| |V0 a| | |
8.#4 I8 Def Alloc rax |I8 a|C7 i| |V0 a| | |
9.#5 I8 Use * Keep rax |I8 a|C7 i| |V0 a| | |
10.#6 V2 Def Alloc rax |V2 a|C7 i| |V0 a| | |
15.#7 V0 Use * Keep rdi |V2 a|C7 i| |V0 a| | |
16.#8 V4 Def Alloc rcx |V2 a|V4 a| | | | |
21.#9 V2 Use Keep rax |V2 a|V4 a| | | | |
22.#10 V3 Def Alloc rdi |V2 a|V4 a| |V3 a| | |
29.#11 V4 Use Keep rcx |V2 a|V4 a| |V3 a| | |
--------------------------------+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+
33.#12 BB2 PredBB1 |V2 a|V4 a| |V3 a| | |
41.#13 V3 Use Keep rdi |V2 a|V4 a| |V3 a| | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
42.#14 I9 Def Alloc rsi |V2 a|V4 a| |I9 a|V3 a| | |
43.#15 I9 Use * Keep rsi |V2 a|V4 a| |I9 a|V3 a| | |
44.#16 I10 Def Alloc rsi |V2 a|V4 a| |I10a|V3 a| | |
51.#17 V3 Use Keep rdi |V2 a|V4 a| |I10a|V3 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
52.#18 I11 Def Alloc rdx |V2 a|V4 a|I11a| |I10a|V3 a| | |
53.#19 I11 Use * Keep rdx |V2 a|V4 a|I11a| |I10a|V3 a| | |
54.#20 I12 Def Alloc rdx |V2 a|V4 a|I12a| |I10a|V3 a| | |
55.#21 I10 Use * Keep rsi |V2 a|V4 a|I12a| |I10a|V3 a| | |
55.#22 I12 Use * Keep rdx |V2 a|V4 a|I12a| |I10a|V3 a| | |
56.#23 I13 Def Alloc rsi |V2 a|V4 a| | |I13a|V3 a| | |
63.#24 V3 Use Keep rdi |V2 a|V4 a| | |I13a|V3 a| | |
64.#25 I14 Def Alloc rdx |V2 a|V4 a|I14a| |I13a|V3 a| | |
65.#26 I14 Use * Keep rdx |V2 a|V4 a|I14a| |I13a|V3 a| | |
66.#27 I15 Def Alloc rdx |V2 a|V4 a|I15a| |I13a|V3 a| | |
67.#28 I13 Use * Keep rsi |V2 a|V4 a|I15a| |I13a|V3 a| | |
67.#29 I15 Use * Keep rdx |V2 a|V4 a|I15a| |I13a|V3 a| | |
68.#30 I16 Def Alloc rsi |V2 a|V4 a| | |I16a|V3 a| | |
75.#31 V3 Use Keep rdi |V2 a|V4 a| | |I16a|V3 a| | |
76.#32 I17 Def Alloc rdx |V2 a|V4 a|I17a| |I16a|V3 a| | |
77.#33 I17 Use * Keep rdx |V2 a|V4 a|I17a| |I16a|V3 a| | |
78.#34 I18 Def Alloc rdx |V2 a|V4 a|I18a| |I16a|V3 a| | |
79.#35 I16 Use * Keep rsi |V2 a|V4 a|I18a| |I16a|V3 a| | |
79.#36 I18 Use * Keep rdx |V2 a|V4 a|I18a| |I16a|V3 a| | |
80.#37 I19 Def Alloc rsi |V2 a|V4 a| | |I19a|V3 a| | |
83.#38 V4 Use * Keep rcx |V2 a|V4 i| | |I19a|V3 a| | |
83.#39 I19 Use *D Keep rsi |V2 a|V4 i| | |I19a|V3 a| | |
84.#40 I20 Def Alloc rcx |V2 a|I20a| | |I19a|V3 a| | |
85.#41 I20 Use * Keep rcx |V2 a|I20a| | | |V3 a| | |
Restr rcx |V2 a|V4 i| | | |V3 a| | |
86.#42 V4 Def Alloc rcx |V2 a|V4 a| | | |V3 a| | |
93.#43 V3 Use * Keep rdi |V2 a|V4 a| | | |V3 i| | |
94.#44 I21 Def Alloc rdi |V2 a|V4 a| | | |I21a| | |
95.#45 I21 Use * Keep rdi |V2 a|V4 a| | | |I21a| | |
Restr rdi |V2 a|V4 a| | | |V3 i| | |
96.#46 V3 Def Alloc rdi |V2 a|V4 a| | | |V3 a| | |
103.#47 V4 Use Keep rcx |V2 a|V4 a| | | |V3 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
107.#48 BB3 PredBB2 |V2 a|V4 a| | | |V3 a| | |
113.#49 V4 Use Keep rcx |V2 a|V4 a| | | |V3 a| | |
114.#50 V5 Def Alloc rsi |V2 a|V4 a| | |V5 a|V3 a| | |
121.#51 V5 Use Keep rsi |V2 a|V4 a| | |V5 a|V3 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
125.#52 BB4 PredBB3 |V2 a|V4 a| | |V5 i|V3 a| | |
131.#53 V4 Use * Keep rcx |V2 a|V4 i| | |V5 i|V3 a| | |
132.#54 V5 Def Keep rsi |V2 a|V4 i| | |V5 a|V3 a| | |
141.#55 V3 Use Keep rdi |V2 a|V4 i| | |V5 a|V3 a| | |
142.#56 I22 Def Alloc rcx |V2 a|I22a| | |V5 a|V3 a| | |
143.#57 I22 Use * Keep rcx |V2 a|I22a| | |V5 a|V3 a| | |
Restr rcx |V2 a|V4 i| | |V5 a|V3 a| | |
144.#58 I23 Def Alloc rcx |V2 a|I23a| | |V5 a|V3 a| | |
145.#59 V5 Use Keep rsi |V2 a|I23a| | |V5 a|V3 a| | |
145.#60 I23 Use *D Keep rcx |V2 a|I23a| | |V5 a|V3 a| | |
146.#61 I24 Def Alloc rdx |V2 a|I23a|I24a| |V5 a|V3 a| | |
Restr rcx |V2 a|V4 i|I24a| |V5 a|V3 a| | |
147.#62 I24 Use * Keep rdx |V2 a|V4 i|I24a| |V5 a|V3 a| | |
148.#63 V4 Def Alloc rcx |V2 a|V4 a| | |V5 a|V3 a| | |
155.#64 V3 Use * Keep rdi |V2 a|V4 a| | |V5 a|V3 i| | |
156.#65 I25 Def Alloc rdi |V2 a|V4 a| | |V5 a|I25a| | |
157.#66 I25 Use * Keep rdi |V2 a|V4 a| | |V5 a|I25a| | |
Restr rdi |V2 a|V4 a| | |V5 a|V3 i| | |
158.#67 V3 Def Alloc rdi |V2 a|V4 a| | |V5 a|V3 a| | |
165.#68 V4 Use Keep rcx |V2 a|V4 a| | |V5 a|V3 a| | |
169.#69 V4 ExpU Keep NA |V2 a|V4 a| | |V5 a|V3 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
169.#70 BB5 PredBB4 |V2 a| | | |V5 a|V3 a| | |
177.#71 V3 Use * Keep rdi |V2 a| | | |V5 a|V3 i| | |
178.#72 I26 Def Alloc rdi |V2 a| | | |V5 a|I26a| | |
179.#73 I26 Use * Keep rdi |V2 a| | | |V5 a|I26a| | |
Restr rdi |V2 a| | | |V5 a|V3 i| | |
180.#74 V3 Def Alloc rdi |V2 a| | | |V5 a|V3 a| | |
187.#75 V5 Use * Keep rsi |V2 a| | | |V5 a|V3 a| | |
188.#76 I27 Def Alloc rcx |V2 a|I27a| | | |V3 a| | |
190.#77 C28 Def Alloc rsi |V2 a|I27a| | |C28a|V3 a| | |
191.#78 C28 Use * Keep rsi |V2 a|I27a| | |C28a|V3 a| | |
191.#79 rcx Fixd Keep rcx |V2 a|I27a| | |C28a|V3 a| | |
191.#80 I27 Use *D Keep rcx |V2 a|I27a| | |C28a|V3 a| | |
192.#81 rcx Kill Keep rcx |V2 a| | | |C28i|V3 a| | |
192.#82 I29 Def Alloc rsi |V2 a| | | |I29a|V3 a| | |
197.#83 I29 Use * Keep rsi |V2 a| | | |I29a|V3 a| | |
197.#84 V3 Use Keep rdi |V2 a| | | |I29a|V3 a| | |
198.#85 I30 Def Alloc rsi |V2 a| | | |I30a|V3 a| | |
199.#86 I30 Use * Keep rsi |V2 a| | | |I30a|V3 a| | |
200.#87 I31 Def Alloc rsi |V2 a| | | |I31a|V3 a| | |
201.#88 I31 Use * Keep rsi |V2 a| | | |I31a|V3 a| | |
202.#89 I32 Def Alloc rsi |V2 a| | | |I32a|V3 a| | |
203.#90 I32 Use * Keep rsi |V2 a| | | |I32a|V3 a| | |
204.#91 V6 Def Alloc rsi |V2 a| | | |V6 a|V3 a| | |
209.#92 V3 Use * Keep rdi |V2 a| | | |V6 a|V3 a| | |
209.#93 V2 Use *D Keep rax |V2 a| | | |V6 a|V3 a| | |
210.#94 I33 Def Alloc rdi |V2 a| | | |V6 a|I33a| | |
211.#95 I33 Use * Keep rdi | | | | |V6 a|I33a| | |
212.#96 V7 Def Alloc rdi | | | | |V6 a|V7 a| | |
217.#97 V7 Use Keep rdi | | | | |V6 a|V7 a| | |
218.#98 I34 Def Alloc rax |I34a| | | |V6 a|V7 a| | |
221.#99 I34 Use * Keep rax |I34a| | | |V6 a|V7 a| | |
222.#100 I35 Def Alloc rax |I35a| | | |V6 a|V7 a| | |
225.#101 I35 Use * Keep rax |I35a| | | |V6 a|V7 a| | |
225.#102 V7 Use * Keep rdi |I35a| | | |V6 a|V7 a| | |
226.#103 I36 Def Alloc rax |I36a| | | |V6 a| | | |
229.#104 I36 Use * Keep rax |I36a| | | |V6 a| | | |
230.#105 I37 Def Alloc rax |I37a| | | |V6 a| | | |
231.#106 I37 Use * Keep rax |I37a| | | |V6 a| | | |
232.#107 I38 Def Alloc rax |I38a| | | |V6 a| | | |
235.#108 I38 Use * Keep rax |I38a| | | |V6 a| | | |
236.#109 I39 Def Alloc rax |I39a| | | |V6 a| | | |
239.#110 I39 Use * Keep rax |I39a| | | |V6 a| | | |
239.#111 V6 Use * Keep rsi |I39a| | | |V6 a| | | |
240.#112 I40 Def Alloc rax |I40a| | | | | | | |
241.#113 rax Fixd Keep rax |I40a| | | | | | | |
241.#114 I40 Use * Keep rax | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @6 RefTypeDef <Ivl:7> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #3 @7 RefTypeUse <Ivl:7> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #4 @8 RefTypeDef <Ivl:8> IND BB01 regmask=[rax] minReg=1>
<RefPosition #5 @9 RefTypeUse <Ivl:8> BB01 regmask=[rax] minReg=1 last>
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdi] minReg=1 last>
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[rdi] minReg=1>
<RefPosition #11 @29 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[rcx] minReg=1 regOptional>
<RefPosition #12 @33 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #13 @41 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #14 @42 RefTypeDef <Ivl:9> HWIntrinsic BB02 regmask=[rsi] minReg=1>
<RefPosition #15 @43 RefTypeUse <Ivl:9> BB02 regmask=[rsi] minReg=1 last>
<RefPosition #16 @44 RefTypeDef <Ivl:10> CAST BB02 regmask=[rsi] minReg=1>
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #18 @52 RefTypeDef <Ivl:11> HWIntrinsic BB02 regmask=[rdx] minReg=1>
<RefPosition #19 @53 RefTypeUse <Ivl:11> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #20 @54 RefTypeDef <Ivl:12> CAST BB02 regmask=[rdx] minReg=1>
<RefPosition #21 @55 RefTypeUse <Ivl:10> BB02 regmask=[rsi] minReg=1 last regOptional>
<RefPosition #22 @55 RefTypeUse <Ivl:12> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #23 @56 RefTypeDef <Ivl:13> ADD BB02 regmask=[rsi] minReg=1>
<RefPosition #24 @63 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #25 @64 RefTypeDef <Ivl:14> HWIntrinsic BB02 regmask=[rdx] minReg=1>
<RefPosition #26 @65 RefTypeUse <Ivl:14> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #27 @66 RefTypeDef <Ivl:15> CAST BB02 regmask=[rdx] minReg=1>
<RefPosition #28 @67 RefTypeUse <Ivl:13> BB02 regmask=[rsi] minReg=1 last regOptional>
<RefPosition #29 @67 RefTypeUse <Ivl:15> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #30 @68 RefTypeDef <Ivl:16> ADD BB02 regmask=[rsi] minReg=1>
<RefPosition #31 @75 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #32 @76 RefTypeDef <Ivl:17> HWIntrinsic BB02 regmask=[rdx] minReg=1>
<RefPosition #33 @77 RefTypeUse <Ivl:17> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #34 @78 RefTypeDef <Ivl:18> CAST BB02 regmask=[rdx] minReg=1>
<RefPosition #35 @79 RefTypeUse <Ivl:16> BB02 regmask=[rsi] minReg=1 last regOptional>
<RefPosition #36 @79 RefTypeUse <Ivl:18> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #37 @80 RefTypeDef <Ivl:19> ADD BB02 regmask=[rsi] minReg=1>
<RefPosition #38 @83 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[rcx] minReg=1 last>
<RefPosition #39 @83 RefTypeUse <Ivl:19> BB02 regmask=[rsi] minReg=1 last delay regOptional>
<RefPosition #40 @84 RefTypeDef <Ivl:20> SUB BB02 regmask=[rcx] minReg=1>
<RefPosition #41 @85 RefTypeUse <Ivl:20> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #42 @86 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #43 @93 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rdi] minReg=1 last>
<RefPosition #44 @94 RefTypeDef <Ivl:21> ADD BB02 regmask=[rdi] minReg=1>
<RefPosition #45 @95 RefTypeUse <Ivl:21> BB02 regmask=[rdi] minReg=1 last>
<RefPosition #46 @96 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #47 @103 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[rcx] minReg=1 regOptional>
<RefPosition #48 @107 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #49 @113 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[rcx] minReg=1>
<RefPosition #50 @114 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB03 regmask=[rsi] minReg=1>
<RefPosition #51 @121 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[rsi] minReg=1 regOptional>
<RefPosition #52 @125 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #53 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[rcx] minReg=1 last>
<RefPosition #54 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[rsi] minReg=1>
<RefPosition #55 @141 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[rdi] minReg=1>
<RefPosition #56 @142 RefTypeDef <Ivl:22> HWIntrinsic BB04 regmask=[rcx] minReg=1>
<RefPosition #57 @143 RefTypeUse <Ivl:22> BB04 regmask=[rcx] minReg=1 last>
<RefPosition #58 @144 RefTypeDef <Ivl:23> CAST BB04 regmask=[rcx] minReg=1>
<RefPosition #59 @145 RefTypeUse <Ivl:4 V05> LCL_VAR BB04 regmask=[rsi] minReg=1>
<RefPosition #60 @145 RefTypeUse <Ivl:23> BB04 regmask=[rcx] minReg=1 last delay regOptional>
<RefPosition #61 @146 RefTypeDef <Ivl:24> SUB BB04 regmask=[rdx] minReg=1>
<RefPosition #62 @147 RefTypeUse <Ivl:24> BB04 regmask=[rdx] minReg=1 last>
<RefPosition #63 @148 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB04 regmask=[rcx] minReg=1>
<RefPosition #64 @155 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[rdi] minReg=1 last>
<RefPosition #65 @156 RefTypeDef <Ivl:25> ADD BB04 regmask=[rdi] minReg=1>
<RefPosition #66 @157 RefTypeUse <Ivl:25> BB04 regmask=[rdi] minReg=1 last>
<RefPosition #67 @158 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB04 regmask=[rdi] minReg=1>
<RefPosition #68 @165 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[rcx] minReg=1 regOptional>
<RefPosition #69 @169 RefTypeExpUse <Ivl:3 V04> BB04 regmask=[allInt] minReg=1>
<RefPosition #70 @169 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #71 @177 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[rdi] minReg=1 last>
<RefPosition #72 @178 RefTypeDef <Ivl:26> ADD BB05 regmask=[rdi] minReg=1>
<RefPosition #73 @179 RefTypeUse <Ivl:26> BB05 regmask=[rdi] minReg=1 last>
<RefPosition #74 @180 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB05 regmask=[rdi] minReg=1>
<RefPosition #75 @187 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[rsi] minReg=1 last>
<RefPosition #76 @188 RefTypeDef <Ivl:27> ADD BB05 regmask=[rcx] minReg=1>
<RefPosition #77 @190 RefTypeDef <Ivl:28> CNS_INT BB05 regmask=[rsi] minReg=1>
<RefPosition #78 @191 RefTypeUse <Ivl:28> BB05 regmask=[rsi] minReg=1 last>
<RefPosition #79 @191 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #80 @191 RefTypeUse <Ivl:27> BB05 regmask=[rcx] minReg=1 last fixed delay>
<RefPosition #81 @192 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #82 @192 RefTypeDef <Ivl:29> LSH BB05 regmask=[rsi] minReg=1>
<RefPosition #83 @197 RefTypeUse <Ivl:29> BB05 regmask=[rsi] minReg=1 last>
<RefPosition #84 @197 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[rdi] minReg=1>
<RefPosition #85 @198 RefTypeDef <Ivl:30> HWIntrinsic BB05 regmask=[rsi] minReg=1>
<RefPosition #86 @199 RefTypeUse <Ivl:30> BB05 regmask=[rsi] minReg=1 last regOptional>
<RefPosition #87 @200 RefTypeDef <Ivl:31> HWIntrinsic BB05 regmask=[rsi] minReg=1>
<RefPosition #88 @201 RefTypeUse <Ivl:31> BB05 regmask=[rsi] minReg=1 last>
<RefPosition #89 @202 RefTypeDef <Ivl:32> CAST BB05 regmask=[rsi] minReg=1>
<RefPosition #90 @203 RefTypeUse <Ivl:32> BB05 regmask=[rsi] minReg=1 last>
<RefPosition #91 @204 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB05 regmask=[rsi] minReg=1>
<RefPosition #92 @209 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[rdi] minReg=1 last>
<RefPosition #93 @209 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[rax] minReg=1 last delay regOptional>
<RefPosition #94 @210 RefTypeDef <Ivl:33> SUB BB05 regmask=[rdi] minReg=1>
<RefPosition #95 @211 RefTypeUse <Ivl:33> BB05 regmask=[rdi] minReg=1 last>
<RefPosition #96 @212 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB05 regmask=[rdi] minReg=1>
<RefPosition #97 @217 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[rdi] minReg=1>
<RefPosition #98 @218 RefTypeDef <Ivl:34> RSH BB05 regmask=[rax] minReg=1>
<RefPosition #99 @221 RefTypeUse <Ivl:34> BB05 regmask=[rax] minReg=1 last>
<RefPosition #100 @222 RefTypeDef <Ivl:35> AND BB05 regmask=[rax] minReg=1>
<RefPosition #101 @225 RefTypeUse <Ivl:35> BB05 regmask=[rax] minReg=1 last>
<RefPosition #102 @225 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[rdi] minReg=1 last regOptional>
<RefPosition #103 @226 RefTypeDef <Ivl:36> ADD BB05 regmask=[rax] minReg=1>
<RefPosition #104 @229 RefTypeUse <Ivl:36> BB05 regmask=[rax] minReg=1 last>
<RefPosition #105 @230 RefTypeDef <Ivl:37> RSH BB05 regmask=[rax] minReg=1>
<RefPosition #106 @231 RefTypeUse <Ivl:37> BB05 regmask=[rax] minReg=1 last>
<RefPosition #107 @232 RefTypeDef <Ivl:38> CAST BB05 regmask=[rax] minReg=1>
<RefPosition #108 @235 RefTypeUse <Ivl:38> BB05 regmask=[rax] minReg=1 last>
<RefPosition #109 @236 RefTypeDef <Ivl:39> LSH BB05 regmask=[rax] minReg=1>
<RefPosition #110 @239 RefTypeUse <Ivl:39> BB05 regmask=[rax] minReg=1 last>
<RefPosition #111 @239 RefTypeUse <Ivl:5 V06> LCL_VAR BB05 regmask=[rsi] minReg=1 last regOptional>
<RefPosition #112 @240 RefTypeDef <Ivl:40> ADD BB05 regmask=[rax] minReg=1>
<RefPosition #113 @241 RefTypeFixedReg <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #114 @241 RefTypeUse <Ivl:40> BB05 regmask=[rax] minReg=1 last fixed>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdi] minReg=1 last>
--- V01
--- V02
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #93 @209 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[rax] minReg=1 last delay regOptional>
--- V03
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[rdi] minReg=1>
<RefPosition #13 @41 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #24 @63 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #31 @75 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #43 @93 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rdi] minReg=1 last>
<RefPosition #46 @96 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #55 @141 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[rdi] minReg=1>
<RefPosition #64 @155 RefTypeUse <Ivl:2 V03> LCL_VAR BB04 regmask=[rdi] minReg=1 last>
<RefPosition #67 @158 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB04 regmask=[rdi] minReg=1>
<RefPosition #71 @177 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[rdi] minReg=1 last>
<RefPosition #74 @180 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB05 regmask=[rdi] minReg=1>
<RefPosition #84 @197 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[rdi] minReg=1>
<RefPosition #92 @209 RefTypeUse <Ivl:2 V03> LCL_VAR BB05 regmask=[rdi] minReg=1 last>
--- V04
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #11 @29 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[rcx] minReg=1 regOptional>
<RefPosition #38 @83 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[rcx] minReg=1 last>
<RefPosition #42 @86 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #47 @103 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[rcx] minReg=1 regOptional>
<RefPosition #49 @113 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[rcx] minReg=1>
<RefPosition #53 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[rcx] minReg=1 last>
<RefPosition #63 @148 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB04 regmask=[rcx] minReg=1>
<RefPosition #68 @165 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[rcx] minReg=1 regOptional>
<RefPosition #69 @169 RefTypeExpUse <Ivl:3 V04> BB04 regmask=[allInt] minReg=1>
--- V05
<RefPosition #50 @114 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB03 regmask=[rsi] minReg=1>
<RefPosition #51 @121 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[rsi] minReg=1 regOptional>
<RefPosition #54 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[rsi] minReg=1>
<RefPosition #59 @145 RefTypeUse <Ivl:4 V05> LCL_VAR BB04 regmask=[rsi] minReg=1>
<RefPosition #75 @187 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[rsi] minReg=1 last>
--- V06
<RefPosition #91 @204 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB05 regmask=[rsi] minReg=1>
<RefPosition #111 @239 RefTypeUse <Ivl:5 V06> LCL_VAR BB05 regmask=[rsi] minReg=1 last regOptional>
--- V07
<RefPosition #96 @212 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB05 regmask=[rdi] minReg=1>
<RefPosition #97 @217 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[rdi] minReg=1>
<RefPosition #102 @225 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[rdi] minReg=1 last regOptional>
Active intervals at end of allocation:
Active Interval 27: RefPositions {#76@188 #80@191} physReg:NA Preferences=[rcx] RelatedInterval <L4>[00000000024ECFA8]
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V02 V03 V04 V05}
Has Critical Edges
Prior to Resolution
BB01 use def in out
{V00}
{V02 V03 V04}
{V00}
{V02 V03 V04}
Var=Reg beg of BB01: V00=rdi
Var=Reg end of BB01: V04=rcx V03=rdi V02=rax
BB02 use def in out
{V03 V04}
{V03 V04}
{V02 V03 V04}
{V02 V03 V04}
Var=Reg beg of BB02: V04=rcx V03=rdi V02=rax
Var=Reg end of BB02: V04=rcx V03=rdi V02=rax
BB03 use def in out
{V04}
{V05}
{V02 V03 V04}
{V02 V03 V04 V05}
Var=Reg beg of BB03: V04=rcx V03=rdi V02=rax
Var=Reg end of BB03: V04=rcx V03=rdi V05=rsi V02=rax
BB04 use def in out
{V03 V04}
{V03 V04 V05}
{V02 V03 V04}
{V02 V03 V04 V05}
Var=Reg beg of BB04: V04=rcx V03=rdi V02=rax
Var=Reg end of BB04: V04=rcx V03=rdi V05=rsi V02=rax
BB05 use def in out
{V02 V03 V05}
{V03 V06 V07}
{V02 V03 V05}
{}
Var=Reg beg of BB05: V03=rdi V05=rsi V02=rax
Var=Reg end of BB05: none
RESOLVING EDGES
Set V00 argument initial register to rdi
Trees after linear scan register allocator (LSRA)
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd LIR
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
N003 ( 5, 12) [000142] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N005 ( 3, 10) [000159] ------------ t159 = CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] REG rcx $100
/--* t159 long
N007 ( 5, 12) [000001] x---G------- t1 = * IND long REG rax <l:$140, c:$180>
/--* t1 long
N009 ( 5, 12) [000141] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2 rax REG rax
N011 ( 1, 3) [000145] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N013 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 rdi (last use) REG rdi $80
/--* t3 int
N015 ( 1, 3) [000144] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2 rcx REG rcx
N017 ( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N019 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 rax REG rax <l:$140, c:$180>
/--* t13 long
N021 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2 rdi REG rdi
N023 ( 5, 8) [000172] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N025 ( 1, 1) [000169] ------------ t169 = LCL_VAR int V04 tmp3 u:2 rcx REG rcx $80
N027 ( 1, 4) [000170] -c---------- t170 = CNS_INT int 256 REG NA $43
/--* t169 int
+--* t170 int
N029 ( 3, 6) [000168] J------N---- * LT void REG NA $200
N031 ( 5, 8) [000171] ------------ * JTRUE void REG NA
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000222] ------------ t222 = PHI_ARG long V03 tmp2 u:4 rdi
N002 ( 0, 0) [000210] ------------ t210 = PHI_ARG long V03 tmp2 u:2 rdi <l:$140, c:$180>
/--* t222 long
+--* t210 long
N005 ( 2, 2) [000207] ------------ t207 = * PHI long
/--* t207 long
N007 ( 2, 3) [000208] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3 rdi
N001 ( 0, 0) [000224] ------------ t224 = PHI_ARG int V04 tmp3 u:4 rcx
N002 ( 0, 0) [000212] ------------ t212 = PHI_ARG int V04 tmp3 u:2 rcx $80
/--* t224 int
+--* t212 int
N005 ( 2, 2) [000199] ------------ t199 = * PHI int
/--* t199 int
N007 ( 2, 3) [000200] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3 rcx
N035 ( 28, 31) [000060] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N037 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V03 tmp2 u:3 rdi REG rdi $141
/--* t25 long
N039 ( 3, 2) [000026] *c-XG------- t26 = * IND long REG NA <l:$142, c:$2c0>
/--* t26 long
N041 ( 4, 3) [000027] ---XG------- t27 = * HWIntrinsic long PopCount REG rsi $300
/--* t27 long
N043 ( 5, 5) [000164] ---XG------- t164 = * CAST int <- long REG rsi $201
N045 ( 1, 1) [000028] ------------ t28 = LCL_VAR long V03 tmp2 u:3 rdi REG rdi $141
/--* t28 long
N047 (???,???) [000242] -c---------- t242 = * LEA(b+8) long REG NA
/--* t242 long
N049 ( 4, 4) [000032] *c-XG------- t32 = * IND long REG NA <l:$143, c:$2c1>
/--* t32 long
N051 ( 5, 5) [000033] ---XG------- t33 = * HWIntrinsic long PopCount REG rdx $301
/--* t33 long
N053 ( 6, 7) [000165] ---XG------- t165 = * CAST int <- long REG rdx $202
/--* t164 int
+--* t165 int
N055 ( 12, 13) [000034] ---XG------- t34 = * ADD int REG rsi $203
N057 ( 1, 1) [000035] ------------ t35 = LCL_VAR long V03 tmp2 u:3 rdi REG rdi $141
/--* t35 long
N059 (???,???) [000243] -c---------- t243 = * LEA(b+16) long REG NA
/--* t243 long
N061 ( 4, 4) [000042] *c-XG------- t42 = * IND long REG NA <l:$144, c:$2c2>
/--* t42 long
N063 ( 5, 5) [000043] ---XG------- t43 = * HWIntrinsic long PopCount REG rdx $302
/--* t43 long
N065 ( 6, 7) [000163] ---XG------- t163 = * CAST int <- long REG rdx $204
/--* t34 int
+--* t163 int
N067 ( 19, 21) [000044] ---XG------- t44 = * ADD int REG rsi $205
N069 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V03 tmp2 u:3 rdi REG rdi $141
/--* t45 long
N071 (???,???) [000244] -c---------- t244 = * LEA(b+24) long REG NA
/--* t244 long
N073 ( 4, 4) [000052] *c-XG------- t52 = * IND long REG NA <l:$145, c:$2c3>
/--* t52 long
N075 ( 5, 5) [000053] ---XG------- t53 = * HWIntrinsic long PopCount REG rdx $303
/--* t53 long
N077 ( 6, 7) [000161] ---XG------- t161 = * CAST int <- long REG rdx $206
/--* t44 int
+--* t161 int
N079 ( 26, 29) [000054] ---XG------- t54 = * ADD int REG rsi $207
N081 ( 1, 1) [000024] ------------ t24 = LCL_VAR int V04 tmp3 u:3 rcx (last use) REG rcx $280
/--* t24 int
+--* t54 int
N083 ( 28, 31) [000056] ---XG------- t56 = * SUB int REG rcx $208
/--* t56 int
N085 ( 28, 31) [000059] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4 rcx REG rcx
N087 ( 3, 3) [000070] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N089 ( 1, 1) [000061] ------------ t61 = LCL_VAR long V03 tmp2 u:3 rdi (last use) REG rdi $141
N091 ( 1, 1) [000066] -c---------- t66 = CNS_INT long 32 REG NA $344
/--* t61 long
+--* t66 long
N093 ( 3, 3) [000067] ------------ t67 = * ADD long REG rdi $244
/--* t67 long
N095 ( 3, 3) [000069] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4 rdi REG rdi
N097 ( 5, 8) [000022] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N099 ( 1, 1) [000018] ------------ t18 = LCL_VAR int V04 tmp3 u:4 rcx REG rcx $208
N101 ( 1, 4) [000019] -c---------- t19 = CNS_INT int 256 REG NA $43
/--* t18 int
+--* t19 int
N103 ( 3, 6) [000020] J------N---- * GE void REG NA $209
N105 ( 5, 8) [000021] ------------ * JTRUE void REG NA
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000218] ------------ t218 = PHI_ARG long V03 tmp2 u:4 rdi
N002 ( 0, 0) [000214] ------------ t214 = PHI_ARG long V03 tmp2 u:2 rdi <l:$140, c:$180>
/--* t218 long
+--* t214 long
N005 ( 2, 2) [000203] ------------ t203 = * PHI long
/--* t203 long
N007 ( 2, 3) [000204] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5 rdi
N001 ( 0, 0) [000220] ------------ t220 = PHI_ARG int V04 tmp3 u:4 rcx
N002 ( 0, 0) [000216] ------------ t216 = PHI_ARG int V04 tmp3 u:2 rcx $80
/--* t220 int
+--* t216 int
N005 ( 2, 2) [000195] ------------ t195 = * PHI int
/--* t195 int
N007 ( 2, 3) [000196] DA---------- * STORE_LCL_VAR int V04 tmp3 d:5 rcx
N109 ( 1, 3) [000075] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N111 ( 1, 1) [000072] ------------ t72 = LCL_VAR int V04 tmp3 u:5 rcx REG rcx $281
/--* t72 int
N113 ( 1, 3) [000074] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2 rsi REG rsi
N115 ( 5, 5) [000177] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N117 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V05 tmp4 u:2 rsi REG rsi $281
N119 ( 1, 1) [000175] -c---------- t175 = CNS_INT int 0 REG NA $40
/--* t174 int
+--* t175 int
N121 ( 3, 3) [000173] J------N---- * LE void REG NA $20a
N123 ( 5, 5) [000176] ------------ * JTRUE void REG NA
------------ BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
N001 ( 0, 0) [000238] ------------ t238 = PHI_ARG long V03 tmp2 u:7 rdi
N002 ( 0, 0) [000226] ------------ t226 = PHI_ARG long V03 tmp2 u:5 rdi $146
/--* t238 long
+--* t226 long
N005 ( 2, 2) [000187] ------------ t187 = * PHI long
/--* t187 long
N007 ( 2, 3) [000188] DA---------- * STORE_LCL_VAR long V03 tmp2 d:6 rdi
N001 ( 0, 0) [000240] ------------ t240 = PHI_ARG int V04 tmp3 u:7 rcx
N002 ( 0, 0) [000228] ------------ t228 = PHI_ARG int V04 tmp3 u:5 rcx $281
/--* t240 int
+--* t228 int
N005 ( 2, 2) [000179] ------------ t179 = * PHI int
/--* t179 int
N007 ( 2, 3) [000180] DA---------- * STORE_LCL_VAR int V04 tmp3 d:6 rcx
N127 ( 1, 3) [000086] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N129 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V04 tmp3 u:6 rcx (last use) REG rcx $282
/--* t83 int
N131 ( 1, 3) [000085] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3 rsi REG rsi
N133 ( 7, 7) [000096] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N135 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V05 tmp4 u:3 rsi REG rsi $282
N137 ( 1, 1) [000088] ------------ t88 = LCL_VAR long V03 tmp2 u:6 rdi REG rdi $147
/--* t88 long
N139 ( 3, 2) [000089] *c-XG------- t89 = * IND long REG NA <l:$148, c:$400>
/--* t89 long
N141 ( 4, 3) [000090] ---XG------- t90 = * HWIntrinsic long PopCount REG rcx $440
/--* t90 long
N143 ( 5, 5) [000091] ---XG------- t91 = * CAST int <- long REG rcx $20b
/--* t87 int
+--* t91 int
N145 ( 7, 7) [000092] ---XG------- t92 = * SUB int REG rdx $20c
/--* t92 int
N147 ( 7, 7) [000095] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:7 rcx REG rcx
N149 ( 3, 3) [000103] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N151 ( 1, 1) [000097] ------------ t97 = LCL_VAR long V03 tmp2 u:6 rdi (last use) REG rdi $147
N153 ( 1, 1) [000099] -c---------- t99 = CNS_INT long 8 REG NA $340
/--* t97 long
+--* t99 long
N155 ( 3, 3) [000100] ------------ t100 = * ADD long REG rdi $246
/--* t100 long
N157 ( 3, 3) [000102] DA---------- * STORE_LCL_VAR long V03 tmp2 d:7 rdi REG rdi
N159 ( 5, 5) [000081] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N161 ( 1, 1) [000077] ------------ t77 = LCL_VAR int V04 tmp3 u:7 rcx REG rcx $20c
N163 ( 1, 1) [000078] -c---------- t78 = CNS_INT int 0 REG NA $40
/--* t77 int
+--* t78 int
N165 ( 3, 3) [000079] J------N---- * GT void REG NA $20d
N167 ( 5, 5) [000080] ------------ * JTRUE void REG NA
------------ BB05 [000..001) (return), preds={BB03,BB04} succs={}
N001 ( 0, 0) [000234] ------------ t234 = PHI_ARG int V05 tmp4 u:3 rsi
N002 ( 0, 0) [000230] ------------ t230 = PHI_ARG int V05 tmp4 u:2 rsi $281
/--* t234 int
+--* t230 int
N005 ( 2, 2) [000191] ------------ t191 = * PHI int
/--* t191 int
N007 ( 2, 3) [000192] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4 rsi
N001 ( 0, 0) [000236] ------------ t236 = PHI_ARG long V03 tmp2 u:7 rdi
N002 ( 0, 0) [000232] ------------ t232 = PHI_ARG long V03 tmp2 u:5 rdi $146
/--* t236 long
+--* t232 long
N005 ( 2, 2) [000183] ------------ t183 = * PHI long
/--* t183 long
N007 ( 2, 3) [000184] DA---------- * STORE_LCL_VAR long V03 tmp2 d:8 rdi
N171 ( 3, 3) [000111] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N173 ( 1, 1) [000105] ------------ t105 = LCL_VAR long V03 tmp2 u:8 rdi (last use) REG rdi $149
N175 ( 1, 1) [000107] -c---------- t107 = CNS_INT long -8 REG NA $345
/--* t105 long
+--* t107 long
N177 ( 3, 3) [000108] ------------ t108 = * ADD long REG rdi $247
/--* t108 long
N179 ( 3, 3) [000110] DA---------- * STORE_LCL_VAR long V03 tmp2 d:9 rdi REG rdi
N181 ( 16, 13) [000127] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N183 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:4 rsi (last use) REG rsi $283
N185 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 REG NA $41
/--* t114 int
+--* t115 int
N187 ( 3, 3) [000116] ------------ t116 = * ADD int REG rcx $20f
N189 ( 1, 1) [000113] ------------ t113 = CNS_INT long 1 REG rsi $346
/--* t113 long
+--* t116 int
N191 ( 10, 7) [000119] ------------ t119 = * LSH long REG rsi $248
N193 ( 1, 1) [000120] ------------ t120 = LCL_VAR long V03 tmp2 u:9 rdi REG rdi $247
/--* t120 long
N195 ( 3, 2) [000121] *c-XG------- t121 = * IND long REG NA <l:$14a, c:$184>
/--* t119 long
+--* t121 long
N197 ( 14, 10) [000122] ---XG------- t122 = * HWIntrinsic long ParallelBitDeposit REG rsi $480
/--* t122 long
N199 ( 15, 11) [000123] ---XG------- t123 = * HWIntrinsic long TrailingZeroCount REG rsi $481
/--* t123 long
N201 ( 16, 13) [000124] ---XG------- t124 = * CAST int <- long REG rsi $211
/--* t124 int
N203 ( 16, 13) [000126] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2 rsi REG rsi
N205 ( 1, 1) [000128] ------------ t128 = LCL_VAR long V03 tmp2 u:9 rdi (last use) REG rdi $247
N207 ( 1, 1) [000129] ------------ t129 = LCL_VAR long V02 tmp1 u:2 rax (last use) REG rax <l:$140, c:$180>
/--* t128 long
+--* t129 long
N209 ( 3, 3) [000130] ------------ t130 = * SUB long REG rdi <l:$249, c:$24a>
/--* t130 long
N211 (???,???) [000246] DA---------- * STORE_LCL_VAR long V07 rat0 rdi REG rdi
N213 ( 1, 1) [000247] ------------ t247 = LCL_VAR long V07 rat0 rdi REG rdi
N215 ( 1, 1) [000248] -c---------- t248 = CNS_INT int 63 REG NA
/--* t247 long
+--* t248 int
N217 ( 3, 3) [000249] ------------ t249 = * RSH long REG rax
N219 ( 1, 1) [000250] -c---------- t250 = CNS_INT long 7 REG NA
/--* t249 long
+--* t250 long
N221 ( 5, 5) [000251] ------------ t251 = * AND long REG rax
N223 ( 1, 1) [000252] ------------ t252 = LCL_VAR long V07 rat0 rdi (last use) REG rdi
/--* t251 long
+--* t252 long
N225 ( 7, 7) [000253] ------------ t253 = * ADD long REG rax
N227 ( 1, 1) [000132] -c---------- t132 = CNS_INT long 3 REG NA $340
/--* t253 long
+--* t132 long
N229 ( 9, 9) [000254] ------------ t254 = * RSH long REG rax
/--* t254 long
N231 ( 25, 9) [000166] ------------ t166 = * CAST int <- long REG rax <l:$212, c:$213>
N233 ( 1, 1) [000135] -c---------- t135 = CNS_INT int 6 REG NA $4b
/--* t166 int
+--* t135 int
N235 ( 27, 11) [000136] ------------ t136 = * LSH int REG rax <l:$214, c:$215>
N237 ( 1, 1) [000138] ------------ t138 = LCL_VAR int V06 tmp5 u:2 rsi (last use) REG rsi $211
/--* t136 int
+--* t138 int
N239 ( 29, 13) [000139] ------------ t139 = * ADD int REG rax <l:$216, c:$217>
/--* t139 int
N241 ( 30, 14) [000010] ------------ * RETURN int REG NA $1c3
-------------------------------------------------------------------------------------------------------------------
Final allocation
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
0.#0 V0 Parm Alloc rdi | | | | | |V0 a| | |
1.#1 BB1 PredBB0 | | | | | |V0 a| | |
6.#2 C7 Def Alloc rcx | |C7 a| | | |V0 a| | |
7.#3 C7 Use * Keep rcx | |C7 i| | | |V0 a| | |
8.#4 I8 Def Alloc rax |I8 a| | | | |V0 a| | |
9.#5 I8 Use * Keep rax |I8 i| | | | |V0 a| | |
10.#6 V2 Def Alloc rax |V2 a| | | | |V0 a| | |
15.#7 V0 Use * Keep rdi |V2 a| | | | |V0 i| | |
16.#8 V4 Def Alloc rcx |V2 a|V4 a| | | | | | |
21.#9 V2 Use Keep rax |V2 a|V4 a| | | | | | |
22.#10 V3 Def Alloc rdi |V2 a|V4 a| | | |V3 a| | |
29.#11 V4 Use Keep rcx |V2 a|V4 a| | | |V3 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
33.#12 BB2 PredBB1 |V2 a|V4 a| | | |V3 a| | |
41.#13 V3 Use Keep rdi |V2 a|V4 a| | | |V3 a| | |
42.#14 I9 Def Alloc rsi |V2 a|V4 a| | |I9 a|V3 a| | |
43.#15 I9 Use * Keep rsi |V2 a|V4 a| | |I9 i|V3 a| | |
44.#16 I10 Def Alloc rsi |V2 a|V4 a| | |I10a|V3 a| | |
51.#17 V3 Use Keep rdi |V2 a|V4 a| | |I10a|V3 a| | |
52.#18 I11 Def Alloc rdx |V2 a|V4 a|I11a| |I10a|V3 a| | |
53.#19 I11 Use * Keep rdx |V2 a|V4 a|I11i| |I10a|V3 a| | |
54.#20 I12 Def Alloc rdx |V2 a|V4 a|I12a| |I10a|V3 a| | |
55.#21 I10 Use * Keep rsi |V2 a|V4 a|I12a| |I10i|V3 a| | |
55.#22 I12 Use * Keep rdx |V2 a|V4 a|I12i| | |V3 a| | |
56.#23 I13 Def Alloc rsi |V2 a|V4 a| | |I13a|V3 a| | |
63.#24 V3 Use Keep rdi |V2 a|V4 a| | |I13a|V3 a| | |
64.#25 I14 Def Alloc rdx |V2 a|V4 a|I14a| |I13a|V3 a| | |
65.#26 I14 Use * Keep rdx |V2 a|V4 a|I14i| |I13a|V3 a| | |
66.#27 I15 Def Alloc rdx |V2 a|V4 a|I15a| |I13a|V3 a| | |
67.#28 I13 Use * Keep rsi |V2 a|V4 a|I15a| |I13i|V3 a| | |
67.#29 I15 Use * Keep rdx |V2 a|V4 a|I15i| | |V3 a| | |
68.#30 I16 Def Alloc rsi |V2 a|V4 a| | |I16a|V3 a| | |
75.#31 V3 Use Keep rdi |V2 a|V4 a| | |I16a|V3 a| | |
76.#32 I17 Def Alloc rdx |V2 a|V4 a|I17a| |I16a|V3 a| | |
77.#33 I17 Use * Keep rdx |V2 a|V4 a|I17i| |I16a|V3 a| | |
78.#34 I18 Def Alloc rdx |V2 a|V4 a|I18a| |I16a|V3 a| | |
79.#35 I16 Use * Keep rsi |V2 a|V4 a|I18a| |I16i|V3 a| | |
79.#36 I18 Use * Keep rdx |V2 a|V4 a|I18i| | |V3 a| | |
80.#37 I19 Def Alloc rsi |V2 a|V4 a| | |I19a|V3 a| | |
83.#38 V4 Use * Keep rcx |V2 a|V4 i| | |I19a|V3 a| | |
83.#39 I19 Use *D Keep rsi |V2 a| | | |I19i|V3 a| | |
84.#40 I20 Def Alloc rcx |V2 a|I20a| | | |V3 a| | |
85.#41 I20 Use * Keep rcx |V2 a|I20i| | | |V3 a| | |
86.#42 V4 Def Alloc rcx |V2 a|V4 a| | | |V3 a| | |
93.#43 V3 Use * Keep rdi |V2 a|V4 a| | | |V3 i| | |
94.#44 I21 Def Alloc rdi |V2 a|V4 a| | | |I21a| | |
95.#45 I21 Use * Keep rdi |V2 a|V4 a| | | |I21i| | |
96.#46 V3 Def Alloc rdi |V2 a|V4 a| | | |V3 a| | |
103.#47 V4 Use Keep rcx |V2 a|V4 a| | | |V3 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
107.#48 BB3 PredBB2 |V2 a|V4 a| | | |V3 a| | |
113.#49 V4 Use Keep rcx |V2 a|V4 a| | | |V3 a| | |
114.#50 V5 Def Alloc rsi |V2 a|V4 a| | |V5 a|V3 a| | |
121.#51 V5 Use Keep rsi |V2 a|V4 a| | |V5 a|V3 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
125.#52 BB4 PredBB3 |V2 a|V4 a| | | |V3 a| | |
131.#53 V4 Use * Keep rcx |V2 a|V4 i| | | |V3 a| | |
132.#54 V5 Def Alloc rsi |V2 a| | | |V5 a|V3 a| | |
141.#55 V3 Use Keep rdi |V2 a| | | |V5 a|V3 a| | |
142.#56 I22 Def Alloc rcx |V2 a|I22a| | |V5 a|V3 a| | |
143.#57 I22 Use * Keep rcx |V2 a|I22i| | |V5 a|V3 a| | |
144.#58 I23 Def Alloc rcx |V2 a|I23a| | |V5 a|V3 a| | |
145.#59 V5 Use Keep rsi |V2 a|I23a| | |V5 a|V3 a| | |
145.#60 I23 Use *D Keep rcx |V2 a|I23i| | |V5 a|V3 a| | |
146.#61 I24 Def Alloc rdx |V2 a| |I24a| |V5 a|V3 a| | |
147.#62 I24 Use * Keep rdx |V2 a| |I24i| |V5 a|V3 a| | |
148.#63 V4 Def Alloc rcx |V2 a|V4 a| | |V5 a|V3 a| | |
155.#64 V3 Use * Keep rdi |V2 a|V4 a| | |V5 a|V3 i| | |
156.#65 I25 Def Alloc rdi |V2 a|V4 a| | |V5 a|I25a| | |
157.#66 I25 Use * Keep rdi |V2 a|V4 a| | |V5 a|I25i| | |
158.#67 V3 Def Alloc rdi |V2 a|V4 a| | |V5 a|V3 a| | |
165.#68 V4 Use Keep rcx |V2 a|V4 a| | |V5 a|V3 a| | |
|V2 a|V4 a| | |V5 a|V3 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
169.#70 BB5 PredBB4 |V2 a| | | |V5 a|V3 a| | |
177.#71 V3 Use * Keep rdi |V2 a| | | |V5 a|V3 i| | |
178.#72 I26 Def Alloc rdi |V2 a| | | |V5 a|I26a| | |
179.#73 I26 Use * Keep rdi |V2 a| | | |V5 a|I26i| | |
180.#74 V3 Def Alloc rdi |V2 a| | | |V5 a|V3 a| | |
187.#75 V5 Use * Keep rsi |V2 a| | | |V5 i|V3 a| | |
188.#76 I27 Def Alloc rcx |V2 a|I27a| | | |V3 a| | |
190.#77 C28 Def Alloc rsi |V2 a|I27a| | |C28a|V3 a| | |
191.#78 C28 Use * Keep rsi |V2 a|I27a| | |C28i|V3 a| | |
191.#79 rcx Fixd Keep rcx |V2 a|I27a| | | |V3 a| | |
191.#80 I27 Use *D Keep rcx |V2 a|I27i| | | |V3 a| | |
192.#81 rcx Kill Keep rcx |V2 a| | | | |V3 a| | |
192.#82 I29 Def Alloc rsi |V2 a| | | |I29a|V3 a| | |
197.#83 I29 Use * Keep rsi |V2 a| | | |I29i|V3 a| | |
197.#84 V3 Use Keep rdi |V2 a| | | | |V3 a| | |
198.#85 I30 Def Alloc rsi |V2 a| | | |I30a|V3 a| | |
199.#86 I30 Use * Keep rsi |V2 a| | | |I30i|V3 a| | |
200.#87 I31 Def Alloc rsi |V2 a| | | |I31a|V3 a| | |
201.#88 I31 Use * Keep rsi |V2 a| | | |I31i|V3 a| | |
202.#89 I32 Def Alloc rsi |V2 a| | | |I32a|V3 a| | |
203.#90 I32 Use * Keep rsi |V2 a| | | |I32i|V3 a| | |
204.#91 V6 Def Alloc rsi |V2 a| | | |V6 a|V3 a| | |
209.#92 V3 Use * Keep rdi |V2 a| | | |V6 a|V3 i| | |
209.#93 V2 Use *D Keep rax |V2 i| | | |V6 a| | | |
210.#94 I33 Def Alloc rdi | | | | |V6 a|I33a| | |
211.#95 I33 Use * Keep rdi | | | | |V6 a|I33i| | |
212.#96 V7 Def Alloc rdi | | | | |V6 a|V7 a| | |
217.#97 V7 Use Keep rdi | | | | |V6 a|V7 a| | |
218.#98 I34 Def Alloc rax |I34a| | | |V6 a|V7 a| | |
221.#99 I34 Use * Keep rax |I34i| | | |V6 a|V7 a| | |
222.#100 I35 Def Alloc rax |I35a| | | |V6 a|V7 a| | |
225.#101 I35 Use * Keep rax |I35i| | | |V6 a|V7 a| | |
225.#102 V7 Use * Keep rdi | | | | |V6 a|V7 i| | |
226.#103 I36 Def Alloc rax |I36a| | | |V6 a| | | |
229.#104 I36 Use * Keep rax |I36i| | | |V6 a| | | |
230.#105 I37 Def Alloc rax |I37a| | | |V6 a| | | |
231.#106 I37 Use * Keep rax |I37i| | | |V6 a| | | |
232.#107 I38 Def Alloc rax |I38a| | | |V6 a| | | |
235.#108 I38 Use * Keep rax |I38i| | | |V6 a| | | |
236.#109 I39 Def Alloc rax |I39a| | | |V6 a| | | |
239.#110 I39 Use * Keep rax |I39i| | | |V6 a| | | |
239.#111 V6 Use * Keep rsi | | | | |V6 i| | | |
240.#112 I40 Def Alloc rax |I40a| | | | | | | |
241.#113 rax Fixd Keep rax |I40a| | | | | | | |
241.#114 I40 Use * Keep rax |I40i| | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 7
Total Reg Cand Vars: 7
Total number of Intervals: 40
Total number of RefPositions: 114
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V00(rdi)
BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N003. IL_OFFSET IL offset: 0x0 REG NA
N005. rcx* = CNS_INT(h) 0x7f08ab884498 static Fseq[_bits] REG rcx
N007. rax = IND ; rcx*
* N009. V02(rax); rax
N011. IL_OFFSET IL offset: 0x0 REG NA
N013. V00(rdi*)
* N015. V04(rcx); rdi*
N017. IL_OFFSET IL offset: 0x0 REG NA
N019. V02(rax)
* N021. V03(rdi); rax
N023. IL_OFFSET IL offset: 0x0 REG NA
N025. V04(rcx)
N027. CNS_INT 256 REG NA
N029. LT ; rcx
N031. JTRUE
Var=Reg end of BB01: V04=rcx V03=rdi V02=rax
BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB02: V04=rcx V03=rdi V02=rax
N035. IL_OFFSET IL offset: 0x0 REG NA
N037. V03(rdi)
N039. STK = IND ; rdi
N041. rsi = HWIntrinsic; STK
N043. rsi = CAST ; rsi
N045. V03(rdi)
N047. STK = LEA(b+8) ; rdi
N049. STK = IND ; STK
N051. rdx = HWIntrinsic; STK
N053. rdx = CAST ; rdx
N055. rsi = ADD ; rsi,rdx
N057. V03(rdi)
N059. STK = LEA(b+16); rdi
N061. STK = IND ; STK
N063. rdx = HWIntrinsic; STK
N065. rdx = CAST ; rdx
N067. rsi = ADD ; rsi,rdx
N069. V03(rdi)
N071. STK = LEA(b+24); rdi
N073. STK = IND ; STK
N075. rdx = HWIntrinsic; STK
N077. rdx = CAST ; rdx
N079. rsi = ADD ; rsi,rdx
N081. V04(rcx*)
N083. rcx = SUB ; rcx*,rsi
* N085. V04(rcx); rcx
N087. IL_OFFSET IL offset: 0x0 REG NA
N089. V03(rdi*)
N091. CNS_INT 32 REG NA
N093. rdi = ADD ; rdi*
* N095. V03(rdi); rdi
N097. IL_OFFSET IL offset: 0x0 REG NA
N099. V04(rcx)
N101. CNS_INT 256 REG NA
N103. GE ; rcx
N105. JTRUE
Var=Reg end of BB02: V04=rcx V03=rdi V02=rax
BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
=====
Predecessor for variable locations: BB02
Var=Reg beg of BB03: V04=rcx V03=rdi V02=rax
N109. IL_OFFSET IL offset: 0x0 REG NA
N111. V04(rcx)
* N113. V05(rsi); rcx
N115. IL_OFFSET IL offset: 0x0 REG NA
N117. V05(rsi)
N119. CNS_INT 0 REG NA
N121. LE ; rsi
N123. JTRUE
Var=Reg end of BB03: V04=rcx V03=rdi V05=rsi V02=rax
BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04}
=====
Predecessor for variable locations: BB03
Var=Reg beg of BB04: V04=rcx V03=rdi V02=rax
N127. IL_OFFSET IL offset: 0x0 REG NA
N129. V04(rcx*)
* N131. V05(rsi); rcx*
N133. IL_OFFSET IL offset: 0x0 REG NA
N135. V05(rsi)
N137. V03(rdi)
N139. STK = IND ; rdi
N141. rcx = HWIntrinsic; STK
N143. rcx = CAST ; rcx
N145. rdx = SUB ; rsi,rcx
* N147. V04(rcx); rdx
N149. IL_OFFSET IL offset: 0x0 REG NA
N151. V03(rdi*)
N153. CNS_INT 8 REG NA
N155. rdi = ADD ; rdi*
* N157. V03(rdi); rdi
N159. IL_OFFSET IL offset: 0x0 REG NA
N161. V04(rcx)
N163. CNS_INT 0 REG NA
N165. GT ; rcx
N167. JTRUE
Var=Reg end of BB04: V04=rcx V03=rdi V05=rsi V02=rax
BB05 [000..001) (return), preds={BB03,BB04} succs={}
=====
Predecessor for variable locations: BB04
Var=Reg beg of BB05: V03=rdi V05=rsi V02=rax
N171. IL_OFFSET IL offset: 0x0 REG NA
N173. V03(rdi*)
N175. CNS_INT -8 REG NA
N177. rdi = ADD ; rdi*
* N179. V03(rdi); rdi
N181. IL_OFFSET IL offset: 0x0 REG NA
N183. V05(rsi*)
N185. CNS_INT -1 REG NA
N187. rcx = ADD ; rsi*
N189. rsi = CNS_INT 1 REG rsi
N191. rsi = LSH ; rsi,rcx
N193. V03(rdi)
N195. STK = IND ; rdi
N197. rsi = HWIntrinsic; rsi,STK
N199. rsi = HWIntrinsic; rsi
N201. rsi = CAST ; rsi
* N203. V06(rsi); rsi
N205. V03(rdi*)
N207. V02(rax*)
N209. rdi = SUB ; rdi*,rax*
* N211. V07(rdi); rdi
N213. V07(rdi)
N215. CNS_INT 63 REG NA
N217. rax = RSH ; rdi
N219. CNS_INT 7 REG NA
N221. rax = AND ; rax
N223. V07(rdi*)
N225. rax = ADD ; rax,rdi*
N227. CNS_INT 3 REG NA
N229. rax = RSH ; rax
N231. rax = CAST ; rax
N233. CNS_INT 6 REG NA
N235. rax = LSH ; rax
N237. V06(rsi*)
N239. rax = ADD ; rax,rsi*
N241. RETURN ; rax
Var=Reg end of BB05: none
*************** In genGenerateCode()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 2 BB03,BB04 2 [000..001)-> BB04 ( cond ) i Loop Loop0 label target bwd LIR
BB05 [0007] 2 BB03,BB04 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V00(rdi)
Modified regs: [rax rcx rdx rsi rdi]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
; Final local variable assignments
;
; V00 arg0 [V00,T05] ( 3, 3 ) int -> rdi
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
; V02 tmp1 [V02,T03] ( 3, 6 ) long -> rax
; V03 tmp2 [V03,T01] ( 14, 23 ) long -> rdi
; V04 tmp3 [V04,T00] ( 9, 29 ) int -> rcx
; V05 tmp4 [V05,T02] ( 5, 6 ) int -> rsi
; V06 tmp5 [V06,T06] ( 2, 2 ) int -> rsi
; V07 rat0 [V07,T04] ( 3, 6 ) long -> rdi
;
; Lcl frame size = 0
=============== Generating BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03} flags=0x00000000.40030020: i label target LIR
BB01 IN (1)={ V00} + ByrefExposed + GcHeap
OUT(3)={V04 V03 V02 } + ByrefExposed + GcHeap
Recording Var Locations at start of BB01
V00(rdi)
Change life 0000000000000000 {} -> 0000000000000020 {V00}
V00 in reg rdi is becoming live [------]
Live regs: 00000000 {} => 00000080 {rdi}
Live regs: (unchanged) 00000080 {rdi}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M8319_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Setting stack level from -572662307 to 0
Scope info: begin block BB01, IL range [000..011)
Scope info: open scopes =
0 (V00 arg0) [000..011)
Added IP mapping: 0x0000 STACK_EMPTY (G_M8319_IG02,ins#0,ofs#0) label
Generating: N003 ( 5, 12) [000142] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N005 ( 3, 10) [000159] ------------ t159 = CNS_INT(h) long 0x7f08ab884498 static Fseq[_bits] REG rcx $100
IN0001: mov rcx, 0x7F08AB884498
/--* t159 long
Generating: N007 ( 5, 12) [000001] x---G------- t1 = * IND long REG rax <l:$140, c:$180>
IN0002: mov rax, qword ptr [rcx]
/--* t1 long
Generating: N009 ( 5, 12) [000141] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2 rax REG rax
V02 in reg rax is becoming live [000141]
Live regs: 00000080 {rdi} => 00000081 {rax rdi}
Live vars: {V00} => {V00 V02}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N011 ( 1, 3) [000145] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N013 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 rdi (last use) REG rdi $80
/--* t3 int
Generating: N015 ( 1, 3) [000144] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2 rcx REG rcx
V00 in reg rdi is becoming dead [000003]
Live regs: 00000081 {rax rdi} => 00000001 {rax}
Live vars: {V00 V02} => {V02}
IN0003: mov ecx, edi
V04 in reg rcx is becoming live [000144]
Live regs: 00000001 {rax} => 00000003 {rax rcx}
Live vars: {V02} => {V02 V04}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N017 ( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N019 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 rax REG rax <l:$140, c:$180>
/--* t13 long
Generating: N021 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2 rdi REG rdi
IN0004: mov rdi, rax
V03 in reg rdi is becoming live [000015]
Live regs: 00000003 {rax rcx} => 00000083 {rax rcx rdi}
Live vars: {V02 V04} => {V02 V03 V04}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N023 ( 5, 8) [000172] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N025 ( 1, 1) [000169] ------------ t169 = LCL_VAR int V04 tmp3 u:2 rcx REG rcx $80
Generating: N027 ( 1, 4) [000170] -c---------- t170 = CNS_INT int 256 REG NA $43
/--* t169 int
+--* t170 int
Generating: N029 ( 3, 6) [000168] J------N---- * LT void REG NA $200
IN0005: cmp ecx, 256
Generating: N031 ( 5, 8) [000171] ------------ * JTRUE void REG NA
IN0006: jl L_M8319_BB03
Scope info: end block BB01, IL range [000..011)
Scope info: ending scope, LVnum=0 [000..011)
Scope info: open scopes =
<none>
=============== Generating BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} flags=0x00000000.42036020: i Loop Loop0 label target bwd LIR
BB02 IN (3)={V04 V03 V02} + ByrefExposed + GcHeap
OUT(3)={V04 V03 V02} + ByrefExposed + GcHeap
Recording Var Locations at start of BB02
V04(rcx) V03(rdi) V02(rax)
Liveness not changing: 000000000000000B {V02 V03 V04}
Live regs: 00000000 {} => 00000083 {rax rcx rdi}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M8319_BB02:
G_M8319_IG02: ; offs=000000H, funclet=00
Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB02, IL range [000..001)
Scope info: open scopes =
<none>
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N035 ( 28, 31) [000060] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N037 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V03 tmp2 u:3 rdi REG rdi $141
/--* t25 long
Generating: N039 ( 3, 2) [000026] *c-XG------- t26 = * IND long REG NA <l:$142, c:$2c0>
/--* t26 long
Generating: N041 ( 4, 3) [000027] ---XG------- t27 = * HWIntrinsic long PopCount REG rsi $300
IN0007: popcnt rsi, qword ptr [rdi]
/--* t27 long
Generating: N043 ( 5, 5) [000164] ---XG------- t164 = * CAST int <- long REG rsi $201
Generating: N045 ( 1, 1) [000028] ------------ t28 = LCL_VAR long V03 tmp2 u:3 rdi REG rdi $141
/--* t28 long
Generating: N047 (???,???) [000242] -c---------- t242 = * LEA(b+8) long REG NA
/--* t242 long
Generating: N049 ( 4, 4) [000032] *c-XG------- t32 = * IND long REG NA <l:$143, c:$2c1>
/--* t32 long
Generating: N051 ( 5, 5) [000033] ---XG------- t33 = * HWIntrinsic long PopCount REG rdx $301
IN0008: popcnt rdx, qword ptr [rdi+8]
/--* t33 long
Generating: N053 ( 6, 7) [000165] ---XG------- t165 = * CAST int <- long REG rdx $202
/--* t164 int
+--* t165 int
Generating: N055 ( 12, 13) [000034] ---XG------- t34 = * ADD int REG rsi $203
IN0009: add esi, edx
Generating: N057 ( 1, 1) [000035] ------------ t35 = LCL_VAR long V03 tmp2 u:3 rdi REG rdi $141
/--* t35 long
Generating: N059 (???,???) [000243] -c---------- t243 = * LEA(b+16) long REG NA
/--* t243 long
Generating: N061 ( 4, 4) [000042] *c-XG------- t42 = * IND long REG NA <l:$144, c:$2c2>
/--* t42 long
Generating: N063 ( 5, 5) [000043] ---XG------- t43 = * HWIntrinsic long PopCount REG rdx $302
IN000a: popcnt rdx, qword ptr [rdi+16]
/--* t43 long
Generating: N065 ( 6, 7) [000163] ---XG------- t163 = * CAST int <- long REG rdx $204
/--* t34 int
+--* t163 int
Generating: N067 ( 19, 21) [000044] ---XG------- t44 = * ADD int REG rsi $205
IN000b: add esi, edx
Generating: N069 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V03 tmp2 u:3 rdi REG rdi $141
/--* t45 long
Generating: N071 (???,???) [000244] -c---------- t244 = * LEA(b+24) long REG NA
/--* t244 long
Generating: N073 ( 4, 4) [000052] *c-XG------- t52 = * IND long REG NA <l:$145, c:$2c3>
/--* t52 long
Generating: N075 ( 5, 5) [000053] ---XG------- t53 = * HWIntrinsic long PopCount REG rdx $303
IN000c: popcnt rdx, qword ptr [rdi+24]
/--* t53 long
Generating: N077 ( 6, 7) [000161] ---XG------- t161 = * CAST int <- long REG rdx $206
/--* t44 int
+--* t161 int
Generating: N079 ( 26, 29) [000054] ---XG------- t54 = * ADD int REG rsi $207
IN000d: add esi, edx
Generating: N081 ( 1, 1) [000024] ------------ t24 = LCL_VAR int V04 tmp3 u:3 rcx (last use) REG rcx $280
/--* t24 int
+--* t54 int
Generating: N083 ( 28, 31) [000056] ---XG------- t56 = * SUB int REG rcx $208
V04 in reg rcx is becoming dead [000024]
Live regs: 00000083 {rax rcx rdi} => 00000081 {rax rdi}
Live vars: {V02 V03 V04} => {V02 V03}
IN000e: sub ecx, esi
/--* t56 int
Generating: N085 ( 28, 31) [000059] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4 rcx REG rcx
V04 in reg rcx is becoming live [000059]
Live regs: 00000081 {rax rdi} => 00000083 {rax rcx rdi}
Live vars: {V02 V03} => {V02 V03 V04}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N087 ( 3, 3) [000070] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N089 ( 1, 1) [000061] ------------ t61 = LCL_VAR long V03 tmp2 u:3 rdi (last use) REG rdi $141
Generating: N091 ( 1, 1) [000066] -c---------- t66 = CNS_INT long 32 REG NA $344
/--* t61 long
+--* t66 long
Generating: N093 ( 3, 3) [000067] ------------ t67 = * ADD long REG rdi $244
V03 in reg rdi is becoming dead [000061]
Live regs: 00000083 {rax rcx rdi} => 00000003 {rax rcx}
Live vars: {V02 V03 V04} => {V02 V04}
IN000f: add rdi, 32
/--* t67 long
Generating: N095 ( 3, 3) [000069] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4 rdi REG rdi
V03 in reg rdi is becoming live [000069]
Live regs: 00000003 {rax rcx} => 00000083 {rax rcx rdi}
Live vars: {V02 V04} => {V02 V03 V04}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N097 ( 5, 8) [000022] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N099 ( 1, 1) [000018] ------------ t18 = LCL_VAR int V04 tmp3 u:4 rcx REG rcx $208
Generating: N101 ( 1, 4) [000019] -c---------- t19 = CNS_INT int 256 REG NA $43
/--* t18 int
+--* t19 int
Generating: N103 ( 3, 6) [000020] J------N---- * GE void REG NA $209
IN0010: cmp ecx, 256
Generating: N105 ( 5, 8) [000021] ------------ * JTRUE void REG NA
IN0011: jge SHORT L_M8319_BB02
Scope info: end block BB02, IL range [000..001)
Scope info: open scopes =
<none>
=============== Generating BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05} flags=0x00000000.40030020: i label target LIR
BB03 IN (3)={V04 V03 V02} + ByrefExposed + GcHeap
OUT(4)={V04 V03 V05 V02} + ByrefExposed + GcHeap
Recording Var Locations at start of BB03
V04(rcx) V03(rdi) V02(rax)
Liveness not changing: 000000000000000B {V02 V03 V04}
Live regs: 00000000 {} => 00000083 {rax rcx rdi}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M8319_BB03:
G_M8319_IG03: ; offs=00001EH, funclet=00
Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB03, IL range [000..001)
Scope info: open scopes =
<none>
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N109 ( 1, 3) [000075] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N111 ( 1, 1) [000072] ------------ t72 = LCL_VAR int V04 tmp3 u:5 rcx REG rcx $281
/--* t72 int
Generating: N113 ( 1, 3) [000074] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2 rsi REG rsi
IN0012: mov esi, ecx
V05 in reg rsi is becoming live [000074]
Live regs: 00000083 {rax rcx rdi} => 000000C3 {rax rcx rsi rdi}
Live vars: {V02 V03 V04} => {V02 V03 V04 V05}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N115 ( 5, 5) [000177] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N117 ( 1, 1) [000174] ------------ t174 = LCL_VAR int V05 tmp4 u:2 rsi REG rsi $281
Generating: N119 ( 1, 1) [000175] -c---------- t175 = CNS_INT int 0 REG NA $40
/--* t174 int
+--* t175 int
Generating: N121 ( 3, 3) [000173] J------N---- * LE void REG NA $20a
IN0013: test esi, esi
Generating: N123 ( 5, 5) [000176] ------------ * JTRUE void REG NA
IN0014: jle L_M8319_BB05
Scope info: end block BB03, IL range [000..001)
Scope info: open scopes =
<none>
=============== Generating BB04 [000..001) -> BB04 (cond), preds={BB03,BB04} succs={BB05,BB04} flags=0x00000000.42036020: i Loop Loop0 label target bwd LIR
BB04 IN (3)={V04 V03 V02} + ByrefExposed + GcHeap
OUT(4)={V04 V03 V05 V02} + ByrefExposed + GcHeap
Recording Var Locations at start of BB04
V04(rcx) V03(rdi) V02(rax)
Change life 000000000000000F {V02 V03 V04 V05} -> 000000000000000B {V02 V03 V04}
V05 in reg rsi is becoming dead [------]
Live regs: (unchanged) 00000000 {}
Live regs: 00000000 {} => 00000083 {rax rcx rdi}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M8319_BB04:
G_M8319_IG04: ; offs=000049H, funclet=00
Label: IG05, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB04, IL range [000..001)
Scope info: open scopes =
<none>
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N127 ( 1, 3) [000086] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N129 ( 1, 1) [000083] ------------ t83 = LCL_VAR int V04 tmp3 u:6 rcx (last use) REG rcx $282
/--* t83 int
Generating: N131 ( 1, 3) [000085] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3 rsi REG rsi
V04 in reg rcx is becoming dead [000083]
Live regs: 00000083 {rax rcx rdi} => 00000081 {rax rdi}
Live vars: {V02 V03 V04} => {V02 V03}
IN0015: mov esi, ecx
V05 in reg rsi is becoming live [000085]
Live regs: 00000081 {rax rdi} => 000000C1 {rax rsi rdi}
Live vars: {V02 V03} => {V02 V03 V05}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N133 ( 7, 7) [000096] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N135 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V05 tmp4 u:3 rsi REG rsi $282
Generating: N137 ( 1, 1) [000088] ------------ t88 = LCL_VAR long V03 tmp2 u:6 rdi REG rdi $147
/--* t88 long
Generating: N139 ( 3, 2) [000089] *c-XG------- t89 = * IND long REG NA <l:$148, c:$400>
/--* t89 long
Generating: N141 ( 4, 3) [000090] ---XG------- t90 = * HWIntrinsic long PopCount REG rcx $440
IN0016: popcnt rcx, qword ptr [rdi]
/--* t90 long
Generating: N143 ( 5, 5) [000091] ---XG------- t91 = * CAST int <- long REG rcx $20b
/--* t87 int
+--* t91 int
Generating: N145 ( 7, 7) [000092] ---XG------- t92 = * SUB int REG rdx $20c
IN0017: mov edx, esi
IN0018: sub edx, ecx
/--* t92 int
Generating: N147 ( 7, 7) [000095] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:7 rcx REG rcx
IN0019: mov ecx, edx
V04 in reg rcx is becoming live [000095]
Live regs: 000000C1 {rax rsi rdi} => 000000C3 {rax rcx rsi rdi}
Live vars: {V02 V03 V05} => {V02 V03 V04 V05}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N149 ( 3, 3) [000103] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N151 ( 1, 1) [000097] ------------ t97 = LCL_VAR long V03 tmp2 u:6 rdi (last use) REG rdi $147
Generating: N153 ( 1, 1) [000099] -c---------- t99 = CNS_INT long 8 REG NA $340
/--* t97 long
+--* t99 long
Generating: N155 ( 3, 3) [000100] ------------ t100 = * ADD long REG rdi $246
V03 in reg rdi is becoming dead [000097]
Live regs: 000000C3 {rax rcx rsi rdi} => 00000043 {rax rcx rsi}
Live vars: {V02 V03 V04 V05} => {V02 V04 V05}
IN001a: add rdi, 8
/--* t100 long
Generating: N157 ( 3, 3) [000102] DA---------- * STORE_LCL_VAR long V03 tmp2 d:7 rdi REG rdi
V03 in reg rdi is becoming live [000102]
Live regs: 00000043 {rax rcx rsi} => 000000C3 {rax rcx rsi rdi}
Live vars: {V02 V04 V05} => {V02 V03 V04 V05}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N159 ( 5, 5) [000081] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N161 ( 1, 1) [000077] ------------ t77 = LCL_VAR int V04 tmp3 u:7 rcx REG rcx $20c
Generating: N163 ( 1, 1) [000078] -c---------- t78 = CNS_INT int 0 REG NA $40
/--* t77 int
+--* t78 int
Generating: N165 ( 3, 3) [000079] J------N---- * GT void REG NA $20d
IN001b: test ecx, ecx
Generating: N167 ( 5, 5) [000080] ------------ * JTRUE void REG NA
IN001c: jg SHORT L_M8319_BB04
Scope info: end block BB04, IL range [000..001)
Scope info: open scopes =
<none>
=============== Generating BB05 [000..001) (return), preds={BB03,BB04} succs={} flags=0x00000000.40030020: i label target LIR
BB05 IN (3)={V03 V05 V02} + ByrefExposed + GcHeap
OUT(0)={ }
Recording Var Locations at start of BB05
V03(rdi) V05(rsi) V02(rax)
Change life 000000000000000F {V02 V03 V04 V05} -> 000000000000000E {V02 V03 V05}
V04 in reg rcx is becoming dead [------]
Live regs: (unchanged) 00000000 {}
Live regs: 00000000 {} => 000000C1 {rax rsi rdi}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M8319_BB05:
G_M8319_IG05: ; offs=000053H, funclet=00
Label: IG06, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB05, IL range [000..001)
Scope info: open scopes =
<none>
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N171 ( 3, 3) [000111] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N173 ( 1, 1) [000105] ------------ t105 = LCL_VAR long V03 tmp2 u:8 rdi (last use) REG rdi $149
Generating: N175 ( 1, 1) [000107] -c---------- t107 = CNS_INT long -8 REG NA $345
/--* t105 long
+--* t107 long
Generating: N177 ( 3, 3) [000108] ------------ t108 = * ADD long REG rdi $247
V03 in reg rdi is becoming dead [000105]
Live regs: 000000C1 {rax rsi rdi} => 00000041 {rax rsi}
Live vars: {V02 V03 V05} => {V02 V05}
IN001d: add rdi, -8
/--* t108 long
Generating: N179 ( 3, 3) [000110] DA---------- * STORE_LCL_VAR long V03 tmp2 d:9 rdi REG rdi
V03 in reg rdi is becoming live [000110]
Live regs: 00000041 {rax rsi} => 000000C1 {rax rsi rdi}
Live vars: {V02 V05} => {V02 V03 V05}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N181 ( 16, 13) [000127] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N183 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:4 rsi (last use) REG rsi $283
Generating: N185 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 REG NA $41
/--* t114 int
+--* t115 int
Generating: N187 ( 3, 3) [000116] ------------ t116 = * ADD int REG rcx $20f
V05 in reg rsi is becoming dead [000114]
Live regs: 000000C1 {rax rsi rdi} => 00000081 {rax rdi}
Live vars: {V02 V03 V05} => {V02 V03}
IN001e: lea ecx, [rsi-1]
Generating: N189 ( 1, 1) [000113] ------------ t113 = CNS_INT long 1 REG rsi $346
IN001f: mov esi, 1
/--* t113 long
+--* t116 int
Generating: N191 ( 10, 7) [000119] ------------ t119 = * LSH long REG rsi $248
IN0020: shl rsi, cl
Generating: N193 ( 1, 1) [000120] ------------ t120 = LCL_VAR long V03 tmp2 u:9 rdi REG rdi $247
/--* t120 long
Generating: N195 ( 3, 2) [000121] *c-XG------- t121 = * IND long REG NA <l:$14a, c:$184>
/--* t119 long
+--* t121 long
Generating: N197 ( 14, 10) [000122] ---XG------- t122 = * HWIntrinsic long ParallelBitDeposit REG rsi $480
IN0021: vpdep rsi, rsi, qword ptr [rdi]
/--* t122 long
Generating: N199 ( 15, 11) [000123] ---XG------- t123 = * HWIntrinsic long TrailingZeroCount REG rsi $481
IN0022: tzcnt rsi, rsi
/--* t123 long
Generating: N201 ( 16, 13) [000124] ---XG------- t124 = * CAST int <- long REG rsi $211
/--* t124 int
Generating: N203 ( 16, 13) [000126] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2 rsi REG rsi
V06 in reg rsi is becoming live [000126]
Live regs: 00000081 {rax rdi} => 000000C1 {rax rsi rdi}
Live vars: {V02 V03} => {V02 V03 V06}
Generating: N205 ( 1, 1) [000128] ------------ t128 = LCL_VAR long V03 tmp2 u:9 rdi (last use) REG rdi $247
Generating: N207 ( 1, 1) [000129] ------------ t129 = LCL_VAR long V02 tmp1 u:2 rax (last use) REG rax <l:$140, c:$180>
/--* t128 long
+--* t129 long
Generating: N209 ( 3, 3) [000130] ------------ t130 = * SUB long REG rdi <l:$249, c:$24a>
V03 in reg rdi is becoming dead [000128]
Live regs: 000000C1 {rax rsi rdi} => 00000041 {rax rsi}
Live vars: {V02 V03 V06} => {V02 V06}
V02 in reg rax is becoming dead [000129]
Live regs: 00000041 {rax rsi} => 00000040 {rsi}
Live vars: {V02 V06} => {V06}
IN0023: sub rdi, rax
/--* t130 long
Generating: N211 (???,???) [000246] DA---------- * STORE_LCL_VAR long V07 rat0 rdi REG rdi
V07 in reg rdi is becoming live [000246]
Live regs: 00000040 {rsi} => 000000C0 {rsi rdi}
Live vars: {V06} => {V06 V07}
Generating: N213 ( 1, 1) [000247] ------------ t247 = LCL_VAR long V07 rat0 rdi REG rdi
Generating: N215 ( 1, 1) [000248] -c---------- t248 = CNS_INT int 63 REG NA
/--* t247 long
+--* t248 int
Generating: N217 ( 3, 3) [000249] ------------ t249 = * RSH long REG rax
IN0024: mov rax, rdi
IN0025: sar rax, 63
Generating: N219 ( 1, 1) [000250] -c---------- t250 = CNS_INT long 7 REG NA
/--* t249 long
+--* t250 long
Generating: N221 ( 5, 5) [000251] ------------ t251 = * AND long REG rax
IN0026: and rax, 7
Generating: N223 ( 1, 1) [000252] ------------ t252 = LCL_VAR long V07 rat0 rdi (last use) REG rdi
/--* t251 long
+--* t252 long
Generating: N225 ( 7, 7) [000253] ------------ t253 = * ADD long REG rax
V07 in reg rdi is becoming dead [000252]
Live regs: 000000C0 {rsi rdi} => 00000040 {rsi}
Live vars: {V06 V07} => {V06}
IN0027: add rax, rdi
Generating: N227 ( 1, 1) [000132] -c---------- t132 = CNS_INT long 3 REG NA $340
/--* t253 long
+--* t132 long
Generating: N229 ( 9, 9) [000254] ------------ t254 = * RSH long REG rax
IN0028: sar rax, 3
/--* t254 long
Generating: N231 ( 25, 9) [000166] ------------ t166 = * CAST int <- long REG rax <l:$212, c:$213>
Generating: N233 ( 1, 1) [000135] -c---------- t135 = CNS_INT int 6 REG NA $4b
/--* t166 int
+--* t135 int
Generating: N235 ( 27, 11) [000136] ------------ t136 = * LSH int REG rax <l:$214, c:$215>
IN0029: shl eax, 6
Generating: N237 ( 1, 1) [000138] ------------ t138 = LCL_VAR int V06 tmp5 u:2 rsi (last use) REG rsi $211
/--* t136 int
+--* t138 int
Generating: N239 ( 29, 13) [000139] ------------ t139 = * ADD int REG rax <l:$216, c:$217>
V06 in reg rsi is becoming dead [000138]
Live regs: 00000040 {rsi} => 00000000 {}
Live vars: {V06} => {}
IN002a: add eax, esi
/--* t139 int
Generating: N241 ( 30, 14) [000010] ------------ * RETURN int REG NA $1c3
Scope info: end block BB05, IL range [000..001)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M8319_IG06,ins#14,ofs#51) label
Reserving epilog IG for block BB05
G_M8319_IG06: ; offs=000068H, funclet=00
*************** After placeholder IG creation
G_M8319_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M8319_IG02: ; offs=000000H, size=001EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG03: ; offs=00001EH, size=002BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG04: ; offs=000049H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG05: ; offs=000053H, size=0015H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG06: ; offs=000068H, size=0033H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG07: ; epilog placeholder, next placeholder=<END>, BB05 [0007], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 135, compSizeEstimate = 148 Program:IntrinsicsUnrolled(int):int
; Final local variable assignments
;
; V00 arg0 [V00,T05] ( 3, 3 ) int -> rdi
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
; V02 tmp1 [V02,T03] ( 3, 6 ) long -> rax
; V03 tmp2 [V03,T01] ( 14, 23 ) long -> rdi
; V04 tmp3 [V04,T00] ( 9, 29 ) int -> rcx
; V05 tmp4 [V05,T02] ( 5, 6 ) int -> rsi
; V06 tmp5 [V06,T06] ( 2, 2 ) int -> rsi
; V07 rat0 [V07,T04] ( 3, 6 ) long -> rdi
;
; Lcl frame size = 0
*************** Before prolog / epilog generation
G_M8319_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M8319_IG02: ; offs=000000H, size=001EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG03: ; offs=00001EH, size=002BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG04: ; offs=000049H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG05: ; offs=000053H, size=0015H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG06: ; offs=000068H, size=0033H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG07: ; epilog placeholder, next placeholder=<END>, BB05 [0007], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Recording Var Locations at start of BB01
V00(rdi)
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M8319_IG01,ins#0,ofs#0) label
__prolog:
IN002b: push rbp
IN002c: mov rbp, rsp
*************** In genClearStackVec3ArgUpperBits()
*************** In genFnPrologCalleeRegArgs() for int regs
*************** In genEnregisterIncomingStackArgs()
IN002d: nop
G_M8319_IG01: ; offs=000000H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN002e: pop rbp
IN002f: ret
G_M8319_IG07: ; offs=00009BH, funclet=00
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M8319_IG01: ; func=00, offs=000000H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M8319_IG02: ; offs=000005H, size=001EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG03: ; offs=000023H, size=002BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG04: ; offs=00004EH, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG05: ; offs=000058H, size=0015H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG06: ; offs=00006DH, size=0033H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M8319_IG07: ; offs=0000A0H, size=0002H, epilog, nogc, emitadd
*************** In emitJumpDistBind()
Binding: IN0006: 000000 jl L_M8319_BB03
Binding L_M8319_BB03 to G_M8319_IG04
Estimate of fwd jump [024F7F54/006]: 001D -> 004E = 002F
Shrinking jump [024F7F54/006]
Adjusted offset of block 03 from 0023 to 001F
Binding: IN0011: 000000 jge SHORT L_M8319_BB02
Binding L_M8319_BB02 to G_M8319_IG03
Estimate of bwd jump [024F82CC/017]: 0048 -> 001F = 002B
Shrinking jump [024F82CC/017]
Adjusted offset of block 04 from 004E to 004A
Binding: IN0014: 000000 jle L_M8319_BB05
Binding L_M8319_BB05 to G_M8319_IG06
Estimate of fwd jump [024F843C/020]: 004E -> 0069 = 0019
Shrinking jump [024F843C/020]
Adjusted offset of block 05 from 0058 to 0050
Binding: IN001c: 000000 jg SHORT L_M8319_BB04
Binding L_M8319_BB04 to G_M8319_IG05
Estimate of bwd jump [024F86F4/028]: 0063 -> 0050 = 0015
Shrinking jump [024F86F4/028]
Adjusted offset of block 06 from 006D to 0065
Adjusted offset of block 07 from 00A0 to 0098
Total shrinkage = 8, min extra jump size = 4294967295
Hot code size = 0x9A bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x6)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M8319_IG01: ; func=00, offs=000000H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN002b: 000000 55 push rbp
IN002c: 000001 488BEC mov rbp, rsp
IN002d: 000004 90 nop
G_M8319_IG02: ; func=00, offs=000005H, size=001AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0001: 000005 48B9984488AB087F0000 mov rcx, 0x7F08AB884498
IN0002: 00000F 488B01 mov rax, qword ptr [rcx]
IN0003: 000012 8BCF mov ecx, edi
IN0004: 000014 488BF8 mov rdi, rax
IN0005: 000017 81F900010000 cmp ecx, 256
IN0006: 00001D 7C2B jl SHORT G_M8319_IG04
G_M8319_IG03: ; func=00, offs=00001FH, size=002BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0007: 00001F F3480FB837 popcnt rsi, qword ptr [rdi]
IN0008: 000024 F3480FB85708 popcnt rdx, qword ptr [rdi+8]
IN0009: 00002A 03F2 add esi, edx
IN000a: 00002C F3480FB85710 popcnt rdx, qword ptr [rdi+16]
IN000b: 000032 03F2 add esi, edx
IN000c: 000034 F3480FB85718 popcnt rdx, qword ptr [rdi+24]
IN000d: 00003A 03F2 add esi, edx
IN000e: 00003C 2BCE sub ecx, esi
IN000f: 00003E 4883C720 add rdi, 32
IN0010: 000042 81F900010000 cmp ecx, 256
IN0011: 000048 7DD5 jge SHORT G_M8319_IG03
G_M8319_IG04: ; func=00, offs=00004AH, size=0006H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0012: 00004A 8BF1 mov esi, ecx
IN0013: 00004C 85F6 test esi, esi
IN0014: 00004E 7E15 jle SHORT G_M8319_IG06
G_M8319_IG05: ; func=00, offs=000050H, size=0015H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0015: 000050 8BF1 mov esi, ecx
IN0016: 000052 F3480FB80F popcnt rcx, qword ptr [rdi]
IN0017: 000057 8BD6 mov edx, esi
IN0018: 000059 2BD1 sub edx, ecx
IN0019: 00005B 8BCA mov ecx, edx
IN001a: 00005D 4883C708 add rdi, 8
IN001b: 000061 85C9 test ecx, ecx
IN001c: 000063 7FEB jg SHORT G_M8319_IG05
G_M8319_IG06: ; func=00, offs=000065H, size=0033H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN001d: 000065 4883C7F8 add rdi, -8
IN001e: 000069 8D4EFF lea ecx, [rsi-1]
IN001f: 00006C BE01000000 mov esi, 1
IN0020: 000071 48D3E6 shl rsi, cl
IN0021: 000074 C4E2CBF537 vpdep rsi, rsi, qword ptr [rdi]
IN0022: 000079 F3480FBCF6 tzcnt rsi, rsi
IN0023: 00007E 482BF8 sub rdi, rax
IN0024: 000081 488BC7 mov rax, rdi
IN0025: 000084 48C1F83F sar rax, 63
IN0026: 000088 4883E007 and rax, 7
IN0027: 00008C 4803C7 add rax, rdi
IN0028: 00008F 48C1F803 sar rax, 3
IN0029: 000093 C1E006 shl eax, 6
IN002a: 000096 03C6 add eax, esi
G_M8319_IG07: ; func=00, offs=000098H, size=0002H, epilog, nogc, emitadd
IN002e: 000098 5D pop rbp
IN002f: 000099 C3 ret
Allocated method code size = 154 , actual size = 154
*************** After end code gen, before unwindEmit()
G_M8319_IG01: ; func=00, offs=000000H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN002b: 000000 push rbp
IN002c: 000001 mov rbp, rsp
IN002d: 000004 nop
G_M8319_IG02: ; offs=000005H, size=001AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0001: 000005 mov rcx, 0x7F08AB884498
IN0002: 00000F mov rax, qword ptr [rcx]
IN0003: 000012 mov ecx, edi
IN0004: 000014 mov rdi, rax
IN0005: 000017 cmp ecx, 256
IN0006: 00001D jl SHORT G_M8319_IG04
G_M8319_IG03: ; offs=00001FH, size=002BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0007: 00001F popcnt rsi, qword ptr [rdi]
IN0008: 000024 popcnt rdx, qword ptr [rdi+8]
IN0009: 00002A add esi, edx
IN000a: 00002C popcnt rdx, qword ptr [rdi+16]
IN000b: 000032 add esi, edx
IN000c: 000034 popcnt rdx, qword ptr [rdi+24]
IN000d: 00003A add esi, edx
IN000e: 00003C sub ecx, esi
IN000f: 00003E add rdi, 32
IN0010: 000042 cmp ecx, 256
IN0011: 000048 jge SHORT G_M8319_IG03
G_M8319_IG04: ; offs=00004AH, size=0006H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0012: 00004A mov esi, ecx
IN0013: 00004C test esi, esi
IN0014: 00004E jle SHORT G_M8319_IG06
G_M8319_IG05: ; offs=000050H, size=0015H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0015: 000050 mov esi, ecx
IN0016: 000052 popcnt rcx, qword ptr [rdi]
IN0017: 000057 mov edx, esi
IN0018: 000059 sub edx, ecx
IN0019: 00005B mov ecx, edx
IN001a: 00005D add rdi, 8
IN001b: 000061 test ecx, ecx
IN001c: 000063 jg SHORT G_M8319_IG05
G_M8319_IG06: ; offs=000065H, size=0033H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN001d: 000065 add rdi, -8
IN001e: 000069 lea ecx, [rsi-1]
IN001f: 00006C mov esi, 1
IN0020: 000071 shl rsi, cl
IN0021: 000074 vpdep rsi, rsi, qword ptr [rdi]
IN0022: 000079 tzcnt rsi, rsi
IN0023: 00007E sub rdi, rax
IN0024: 000081 mov rax, rdi
IN0025: 000084 sar rax, 63
IN0026: 000088 and rax, 7
IN0027: 00008C add rax, rdi
IN0028: 00008F sar rax, 3
IN0029: 000093 shl eax, 6
IN002a: 000096 add eax, esi
G_M8319_IG07: ; offs=000098H, size=0002H, epilog, nogc, emitadd
IN002e: 000098 pop rbp
IN002f: 000099 ret
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x00009a (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x01
CountOfUnwindCodes: 1
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
allocUnwindInfo(pHotCode=0x00007F08AC9FFEA0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x9a, unwindSize=0x6, pUnwindBlock=0x00000000024DACA2, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 3
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000005 ( STACK_EMPTY )
IL offs EPILOG : 0x00000098 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 2
*************** Variable debug info
2 vars
0( UNKNOWN) : From 00000000h to 00000005h, in rdi
0( UNKNOWN) : From 00000005h to 00000012h, in rdi
*************** In gcInfoBlockHdrSave()
Set code length to 154.
Set ReturnKind to Scalar.
Set stack base register to rbp.
Set Outgoing stack arg area size to 0.
Defining interruptible range: [0x5, 0x98).
Method code size: 154
Allocations for Program:IntrinsicsUnrolled(int):int (MethodHash=6b9d3a1b)
count: 1770, size: 144830, max = 3072
allocateMemory: 196608, nraUsed: 150504
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 6460 | 4.46%
ASTNode | 35600 | 24.58%
InstDesc | 5176 | 3.57%
ImpStack | 384 | 0.27%
BasicBlock | 3160 | 2.18%
fgArgInfo | 0 | 0.00%
fgArgInfoPtrArr | 0 | 0.00%
FlowList | 512 | 0.35%
TreeStatementList | 0 | 0.00%
SiScope | 192 | 0.13%
FlatFPStateX87 | 0 | 0.00%
DominatorMemory | 208 | 0.14%
LSRA | 3424 | 2.36%
LSRA_Interval | 3280 | 2.26%
LSRA_RefPosition | 7360 | 5.08%
Reachability | 16 | 0.01%
SSA | 2108 | 1.46%
ValueNumber | 13846 | 9.56%
LvaTable | 4216 | 2.91%
UnwindInfo | 0 | 0.00%
hashBv | 360 | 0.25%
bitset | 408 | 0.28%
FixedBitVect | 0 | 0.00%
Generic | 2794 | 1.93%
IndirAssignMap | 0 | 0.00%
FieldSeqStore | 176 | 0.12%
ZeroOffsetFieldMap | 40 | 0.03%
ArrayInfoMap | 40 | 0.03%
MemoryPhiArg | 0 | 0.00%
CSE | 3344 | 2.31%
GC | 1328 | 0.92%
CorSig | 104 | 0.07%
Inlining | 808 | 0.56%
ArrayStack | 384 | 0.27%
DebugInfo | 168 | 0.12%
DebugOnly | 43284 | 29.89%
Codegen | 1144 | 0.79%
LoopOpt | 2560 | 1.77%
LoopHoist | 288 | 0.20%
Unknown | 386 | 0.27%
RangeCheck | 0 | 0.00%
CopyProp | 1272 | 0.88%
SideEffects | 0 | 0.00%
****** DONE compiling Program:IntrinsicsUnrolled(int):int
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment