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Christopher Felton cfelton

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cfelton / ivs_mem.py
Created Mar 9, 2018
initial value support conversion error
View ivs_mem.py
import myhdl as hdl
from myhdl import Signal, ResetSignal, intbv, always_seq
@hdl.block
def test_mem_ivs_convert(clock, reset, wr, wrd, rdd, addr):
return memory(clock, reset, wr, wrd, rdd, addr)
@hdl.block
def memory(clock, reset, wr, wrd, rdd, addr):
mem = [Signal(intbv(0, min=wrd.min, max=wrd.max))
@cfelton
cfelton / bit_length.py
Last active Jul 5, 2016
Generic module that determines the number of bits for a value (limited to 32), uses 5 LUTs on an Artix7
View bit_length.py
from random import randint
import myhdl
from myhdl import Signal, intbv, always, delay, instance, StopSimulation
def bit_length(num):
"""Determine the number of bits required to represent a value
@cfelton
cfelton / los_intf.py
Last active Jun 23, 2016
another interface example (gsoc 2016)
View los_intf.py
from random import randint
import myhdl
from myhdl import Signal, ResetSignal, intbv, always_seq, always_comb
from myhdl import instance, delay, StopSimulation
from myhdl.conversion import verify
try:
from rhea import Signals
View transactors_examples.py
from myhdl import Signal, intbv
class SomeInterface(object):
def __init__(self, clock):
self.clock = clock
self.datain = Signa(intbv(0)[8:])
self.dataout = Signal(intbv(0)[8:])
self.data_valid = Signal(bool(0))
View FIFOBus.py
class FIFOBus(object):
def __init__(self, size=16, width=8):
"""
"""
self.name = "fifobus{0}".format(_fb_num)
# @todo: add write clock and read clock to the interface!
# @todo: use longer names read, read_valid, read_data,
# @todo: write, write_data, etc.!
View ram_rom_compare1.py
def ram_rom_compare1(xram, yrom, num_matches):
assert len(xram) == len(yrom)
numitems = len(xram)
@always_comb
def compare():
count = 0
for ii in range(numitems):
if xram[ii] == yrom[ii]:
count = count + 1
num_matches.next = count
@cfelton
cfelton / myhdl_issue_nnn.py
Created Feb 25, 2016
The following demonstrates a top-level interface conversion issue.
View myhdl_issue_nnn.py
import myhdl
from myhdl import Signal, intbv, always_comb
class Intf1(object):
def __init__(self):
self.a = Signal(intbv(0, min=0, max=2))
self.b = Signal(intbv(0, min=0, max=4))
self.c = Signal(intbv(0, min=0, max=8))
@cfelton
cfelton / test_simulation_pause.py
Created Feb 23, 2016
Tests that should pass with myhdl simulation pause and quit
View test_simulation_pause.py
import myhdl
from myhdl import instance, delay, now
def test():
@instance
def tbstim():
yield delay(10)
print("{:<8d} ".format(now()))
yield delay(1000)
View fpga631_snip1.py
@always_seq(clock.posedge, reset=reset)
def beh_sop():
# tap update loop
xd[0].next = x
for ii in range(1, len(h)):
xd[ii].next = xd[ii-1]
# sum-of-products loop
sop = 0
for ii in range(len(h)):
@cfelton
cfelton / constant_type.py
Last active Jan 26, 2016
using constants in myhdl
View constant_type.py
import argparse
from argparse import Namespace
from myhdl import *
class Constants(object):
def __init__(self, **constargs):
# the const can contain int and str convert all to int
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