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@cfelton
cfelton / counter.py
Last active September 13, 2019 11:09
MyHDL simple counter.
from myhdl import *
# counter with assign
def m_counter(i_clk, i_reset, o_count):
#s_count = Signal(modbv(0, min=0, max=256))
@always_seq(i_clk.posedge, reset=i_reset)
def rtl_count():
o_count.next = o_count + 1
# following doesnt' convert with 0.8.1, sims ok
from myhdl import *
def top(sda, scl, sda_i, sda_o, scl_i, scl_o):
"""Simple I2C bi-dir converter.
This example will break the I2C bi-directional signals into
uni-dir explicit signals.
"""
sda_d = sda.driver()
scl_d = scl.driver()
@cfelton
cfelton / ivs_mem.py
Created March 9, 2018 11:56
initial value support conversion error
import myhdl as hdl
from myhdl import Signal, ResetSignal, intbv, always_seq
@hdl.block
def test_mem_ivs_convert(clock, reset, wr, wrd, rdd, addr):
return memory(clock, reset, wr, wrd, rdd, addr)
@hdl.block
def memory(clock, reset, wr, wrd, rdd, addr):
mem = [Signal(intbv(0, min=wrd.min, max=wrd.max))
@cfelton
cfelton / sigmat.py
Last active February 14, 2018 01:10
Signal Matrix implemented in myhdl
from myhdl import *
class SignalMatrix(object):
def __init__(self, size=(4,4,), stype=intbv(0)[9:]):
# the size of the matrix
self.size = size
nrows, ncols = size
@cfelton
cfelton / fpga25_snip1.py
Last active May 11, 2017 06:38
Code snips for http://www.fpgarelated.com/showarticle/25.php, see the link for description
from myhdl import Signal, intbv, always_seq
def shift_reg(clock, reset, y):
shift = Signal(intbv(0)[len(y):])
mask = shift.max - 1
@always_seq(clock.posedge, reset=reset)
@cfelton
cfelton / MemTest_commented.vhd
Last active October 20, 2016 23:56
MemTest VHDL to Verilog conversion example.
--**********************************************************************
-- Copyright (c) 1997-2014 by XESS Corp <http://www.xess.com>.
-- All rights reserved.
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 3.0 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
@cfelton
cfelton / bit_length.py
Last active July 5, 2016 16:17
Generic module that determines the number of bits for a value (limited to 32), uses 5 LUTs on an Artix7
from random import randint
import myhdl
from myhdl import Signal, intbv, always, delay, instance, StopSimulation
def bit_length(num):
"""Determine the number of bits required to represent a value
@cfelton
cfelton / los_intf.py
Last active June 23, 2016 15:57
another interface example (gsoc 2016)
from random import randint
import myhdl
from myhdl import Signal, ResetSignal, intbv, always_seq, always_comb
from myhdl import instance, delay, StopSimulation
from myhdl.conversion import verify
try:
from rhea import Signals
def rgb2ycbcr(rgb, ycbcr, clock, reset):
""" A RGB to YCbCr converter with reset.
Arguments:
rgb: red, green, blue interface
r: input 8-bit unsigned value in range of 0-255
g: input 8-bit unsigned value in range of 0-255
b: input 8-bit unsigned value in range of 0-255
@cfelton
cfelton / testbench_template.py
Last active June 2, 2016 12:28
A template for MyHDL testbenchds
import myhdl
from myhdl import Signal, intbv, instance, delay, StopSimulation
def testbench_template(args=None):
# any code to extract argument for what is desired to be tested
# instantiate all signals and interface