proc-v7.S

/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
/* Also save registers PMINTENCLR,  PMUSEREN, PMCCNTR, PMCR, PMCNTENSET for Performance monitoring unit  */
.globl  cpu_v7_suspend_size
.equ    cpu_v7_suspend_size, 4 * 14
#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_v7_do_suspend)
        stmfd   sp!, {r4 - r11, lr}
        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
        mrc     p15, 0, r5, c13, c0, 3  @ User r/o thread ID

        mrc     p15, 0, r6, c9, c14, 2  @ PMINTENCLR
        mrc     p15, 0, r7, c9, c14, 0  @ PMUSEREN
        mrc     p15, 0, r8, c9, c13, 0  @ PMCCNTR, cycle counter
        mrc     p15, 0, r9, c9, c12, 0  @ PMCR, control register
        mrc     p15, 0, r10, c9, c12, 1 @ PMCNTENSET, counter enable set
        stmia   r0!, {r4 - r10}
#ifdef CONFIG_MMU
        mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
#ifdef CONFIG_ARM_LPAE
        mrrc    p15, 1, r5, r7, c2      @ TTB 1
#else
        mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
#endif
        mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
#endif
        mrc     p15, 0, r8, c1, c0, 0   @ Control register
        mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
        mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
        stmia   r0, {r5 - r11}
        ldmfd   sp!, {r4 - r11, pc}
ENDPROC(cpu_v7_do_suspend)

ENTRY(cpu_v7_do_resume)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
        mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
        ldmia   r0!, {r4 - r10}
        mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
        mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID

        mcr     p15, 0, r6, c9, c14, 2  @ PMINTENCLR
        mcr     p15, 0, r7, c9, c14, 0  @ PMUSEREN
        mcr     p15, 0, r8, c9, c13, 0  @ PMCCNTR, cycle counter
        mcr     p15, 0, r9, c9, c12, 0 @ PMCR, control register
        mcr     p15, 0, r10, c9, c12, 1 @ PMCNTENSET, counter enable set
        ldmia   r0, {r5 - r11}
#ifdef CONFIG_MMU
        mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
        mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
#ifdef CONFIG_ARM_LPAE
        mcrr    p15, 0, r1, ip, c2      @ TTB 0
        mcrr    p15, 1, r5, r7, c2      @ TTB 1
#else
        ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
        ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
        mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
        mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
#endif
        mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
        ldr     r4, =PRRR               @ PRRR
        ldr     r5, =NMRR               @ NMRR
        mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
        mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
#endif  /* CONFIG_MMU */
        mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
        teq     r4, r9                  @ Is it already set?
        mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
        mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
        isb
        dsb
        mov     r0, r8                  @ control register
        b       cpu_resume_mmu
ENDPROC(cpu_v7_do_resume)
#endif