Which RISC-V instructions does the ET-SoC-1 give us?

confirm_isa.c

#include <errno.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
#include <time.h>
#include <unistd.h>

#include <et_ioctl.h>
#include <esperanto/device-apis/operations-api/device_ops_api_spec.h>
#include <esperanto/device-apis/operations-api/device_ops_api_rpc_types.h>

#define FATAL(fmt, ...) do {fprintf(stderr, "FATAL ERROR: " fmt " (raised at %s:%d)\n",##__VA_ARGS__,__FILE__,__LINE__); exit(1);} while(0)

const struct insn_entry {
  const char* name;
  uint32_t encoding;
} g_insns[] = {
#include "confirm_isa_insns.h"
  {NULL, 0},
};

static uint16_t sq_push(int fd, struct cmn_header_t* msg, uint8_t flags) {
  struct cmd_desc msg_desc = {
    .cmd = msg,
    .size = msg->size,
    .flags = flags,
  };
  uint16_t tag = msg->tag_id = (uint16_t)rand();
  for (;;) {
    if (ioctl(fd, ETSOC1_IOCTL_PUSH_SQ, &msg_desc) < 0) {
      if (errno == EAGAIN) continue;
      FATAL("Could not issue ETSOC1_IOCTL_PUSH_SQ");
    }
    return tag;
  }
}

static void cq_pop_until(int fd, struct rsp_desc* dst, uint16_t kind, uint16_t tag) {
  for (;;) {
    if (ioctl(fd, ETSOC1_IOCTL_POP_CQ, dst) < 0) {
      if (errno == EAGAIN) continue;
      FATAL("Could not issue ETSOC1_IOCTL_POP_CQ");
    }
    struct cmn_header_t* hdr = (struct cmn_header_t*)dst->rsp;
    if (hdr->msg_id == kind && hdr->tag_id == tag) break;
  }
}

static uint16_t async_memcpy_from_device(int fd, void* dst, uint64_t src, size_t size) {
  struct {
    struct cmn_header_t header;
    struct dma_read_node node;
  } __attribute__((packed, aligned(8))) dma_cmd = {
    .header = {
      .size = sizeof(dma_cmd),
      .msg_id = DEV_OPS_API_MID_DEVICE_OPS_DMA_READLIST_CMD,
    },
    .node = {
      .dst_host_virt_addr = (uint64_t)(uintptr_t)dst,
      .src_device_phy_addr = src,
      .size = size,
    }
  };
  return sq_push(fd, &dma_cmd.header, CMD_DESC_FLAG_DMA);
}

typedef struct execution_context_t {
    uint64_t type;
    uint64_t cycles;
    uint64_t hart_id;
    uint64_t sepc;
    uint64_t sstatus;
    uint64_t stval;
    uint64_t scause;
    int64_t user_error;
    uint64_t gpr[31];
} __attribute__((packed, aligned(64))) execution_context_t;

int main() {
  srand(time(NULL));

  int fd = open("/dev/et0_ops", O_RDWR | O_CLOEXEC);
  if (fd < 0) FATAL("Could not open PCIe device");

  struct dram_info dram_info;
  if (ioctl(fd, ETSOC1_IOCTL_GET_USER_DRAM_INFO, &dram_info) < 0) FATAL("Could not issue ETSOC1_IOCTL_GET_USER_DRAM_INFO");
  printf("Have %llu bytes of DRAM starting at 0x%llx\n", (long long unsigned)dram_info.size, (long long unsigned)dram_info.base);

  struct {
    struct device_ops_kernel_launch_cmd_t launch;
    uint32_t rv_code[3];
  } __attribute__((packed, aligned(8))) launch_cmd = {
    .launch = {
      .command_info = {
        .cmd_hdr = {
          .size = sizeof(launch_cmd),
          .msg_id = DEV_OPS_API_MID_DEVICE_OPS_KERNEL_LAUNCH_CMD,
          .flags = CMD_FLAGS_KERNEL_LAUNCH_ARGS_EMBEDDED,
        }
      },
      .code_start_address = dram_info.base,
      .pointer_to_args = dram_info.base,
      .exception_buffer = dram_info.base + 64,
      .shire_mask = 0x1,
    },
    .rv_code = {
      0x00000013, // nop
      0x00800513, // li	a0, 8
      0x00000073, // ecall
    },
  };
  uint16_t tag = sq_push(fd, &launch_cmd.launch.command_info.cmd_hdr, 0);

  char rsp_buf[256];
  struct rsp_desc rsp_desc = {
    .rsp = rsp_buf,
    .size = sizeof(rsp_buf),
  };
  cq_pop_until(fd, &rsp_desc, DEV_OPS_API_MID_DEVICE_OPS_KERNEL_LAUNCH_RSP, tag);
  printf("Kernel launch status: %u\n", ((struct device_ops_kernel_launch_rsp_t*)rsp_buf)->status);

  launch_cmd.rv_code[0] = 0x1234deaf;
  tag = sq_push(fd, &launch_cmd.launch.command_info.cmd_hdr, 0);
  cq_pop_until(fd, &rsp_desc, DEV_OPS_API_MID_DEVICE_OPS_KERNEL_LAUNCH_RSP, tag);
  printf("Faulty launch status: %u\n", ((struct device_ops_kernel_launch_rsp_t*)rsp_buf)->status);

  const size_t contexts_size = sizeof(execution_context_t) * 64;
  void* dma_buf = mmap(NULL, contexts_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
  if (dma_buf == MAP_FAILED) FATAL("Could not allocate %llu byte DMA buffer", (long long unsigned)contexts_size);
  tag = async_memcpy_from_device(fd, dma_buf, launch_cmd.launch.exception_buffer, contexts_size);
  cq_pop_until(fd, &rsp_desc, DEV_OPS_API_MID_DEVICE_OPS_DMA_READLIST_RSP, tag);
  printf("Faulty launch scause: %u\n", (unsigned)((execution_context_t*)dma_buf)->scause);

  for (const struct insn_entry* i = g_insns; i->name; ++i) {
    launch_cmd.rv_code[0] = i->encoding;
    tag = sq_push(fd, &launch_cmd.launch.command_info.cmd_hdr, 0);
    cq_pop_until(fd, &rsp_desc, DEV_OPS_API_MID_DEVICE_OPS_KERNEL_LAUNCH_RSP, tag);
    const char* status = "OK";
    if (((struct device_ops_kernel_launch_rsp_t*)rsp_buf)->status != DEV_OPS_API_KERNEL_LAUNCH_RESPONSE_KERNEL_COMPLETED) {
      tag = async_memcpy_from_device(fd, dma_buf, launch_cmd.launch.exception_buffer, contexts_size);
      cq_pop_until(fd, &rsp_desc, DEV_OPS_API_MID_DEVICE_OPS_DMA_READLIST_RSP, tag);
      switch (((execution_context_t*)dma_buf)->scause) {
      case  2: status = "Invalid"; break;
      case 30: status = "Emulate"; break;
      }
    }
    printf("%-8s -> %s\n", i->name, status);
  }

  munmap(dma_buf, contexts_size);
  close(fd);
  return 0;
}

confirm_isa_insns.h

// RV32
{"addi", 0x13},
{"slti", 0x2013},
{"sltiu", 0x3013},
{"andi", 0x7013},
{"ori", 0x6013},
{"xori", 0x4013},
{"slli", 0x1013},
{"srli", 0x5013},
{"srai", 0x40005013},
{"lui", 0x37},
{"auipc", 0x17},
{"add", 0x33},
{"slt", 0x2033},
{"sltu", 0x3033},
{"and", 0x7033},
{"or", 0x6033},
{"xor", 0x4033},
{"sll", 0x1033},
{"srl", 0x5033},
{"sub", 0x40000033},
{"sra", 0x40005033},
{"lw", 0x2003},
{"lh", 0x1003},
{"lhu", 0x5003},
{"lb", 0x3},
{"lbu", 0x4003},
{"sw", 0x2023},
{"sh", 0x1023},
{"sb", 0x23},
{"fence", 0xf},
// RV64
{"addiw", 0x1b},
{"slliw", 0x101b},
{"srliw", 0x501b},
{"sraiw", 0x4000501b},
{"addw", 0x3b},
{"subw", 0x4000003b},
{"sllw", 0x103b},
{"srlw", 0x503b},
{"sraw", 0x4000503b},
{"ld", 0x3003},
{"lwu", 0x6003},
{"sd", 0x3023},
// M
{"mul", 0x2000033},
{"mulh", 0x2001033},
{"mulhsu", 0x2002033},
{"mulhu", 0x2003033},
{"mulw", 0x200003b},
{"div", 0x2004033},
{"divu", 0x2005033},
{"rem", 0x2006033},
{"remu", 0x2007033},
{"divw", 0x200403b},
{"divuw", 0x200503b},
{"remw", 0x200603b},
{"remuw", 0x200703b},
// B
{"add.uw", 0x800003b},
{"andn", 0x40007033},
{"clmul", 0xa001033},
{"clmulh", 0xa003033},
{"clmulr", 0xa002033},
{"clz", 0x60001013},
{"clzw", 0x6000101b},
{"cpop", 0x60201013},
{"cpopw", 0x6020101b},
{"ctz", 0x60101013},
{"ctzw", 0x6010101b},
{"max", 0xa006033},
{"maxu", 0xa007033},
{"min", 0xa004033},
{"minu", 0xa005033},
{"gorci", 0x28005013},
{"orn", 0x40006033},
{"grevi", 0x68005013},
{"rol", 0x60001033},
{"rolw", 0x6000103b},
{"ror", 0x60005033},
{"rori", 0x60005013},
{"rorw", 0x6000503b},
{"roriw", 0x6000501b},
{"bclr", 0x48001033},
{"bclri", 0x48001013},
{"bext", 0x48005033},
{"bexti", 0x48005013},
{"binv", 0x68001033},
{"binvi", 0x68001013},
{"bset", 0x28001033},
{"bseti", 0x28001013},
{"sext.b", 0x60401013},
{"sext.h", 0x60501013},
{"sh1add", 0x20002033},
{"sh1add.uw", 0x2000203b},
{"sh2add", 0x20004033},
{"sh2add.uw", 0x2000403b},
{"sh3add", 0x20006033},
{"sh3add.uw", 0x2000603b},
{"slli.uw", 0x800101b},
{"xnor", 0x40004033},
{"pack", 0x8004033},
{"packh", 0x8007033},
{"packw", 0x800403b},
{"xperm4", 0x28002033},
{"xperm8", 0x28004033},
{"shfli", 0x8001013},
{"unshfli", 0x8005013},
// F
{"frcsr", 0x302073},
{"fscsr", 0x301073},
{"frrm", 0x202073},
{"fsrm", 0x201073},
{"fsrmi", 0x205073},
{"frflags", 0x102073},
{"fsflags", 0x101073},
{"fsflagsi", 0x105073},
{"flw", 0x2007},
{"fsw", 0x2027},
{"fadd.s", 0x53},
{"fsub.s", 0x8000053},
{"fmul.s", 0x10000053},
{"fdiv.s", 0x18000053},
{"fsqrt.s", 0x58000053},
{"fmin.s", 0x28000053},
{"fmax.s", 0x28001053},
{"fmadd.s", 0x43},
{"fmsub.s", 0x47},
{"fnmsub.s", 0x4b},
{"fnmadd.s", 0x4f},
{"fcvt.w.s", 0xc0000053},
{"fcvt.wu.s", 0xc0100053},
{"fcvt.l.s", 0xc0200053},
{"fcvt.lu.s", 0xc0300053},
{"fcvt.s.w", 0xd0000053},
{"fcvt.s.wu", 0xd0100053},
{"fcvt.s.l", 0xd0200053},
{"fcvt.s.lu", 0xd0300053},
{"fsgnj.s", 0x20000053},
{"fsgnjn.s", 0x20001053},
{"fsgnjx.s", 0x20002053},
{"fmv.x.s", 0xe0000053},
{"fmv.s.x", 0xf0000053},
{"feq.s", 0xa0002053},
{"flt.s", 0xa0001053},
{"fle.s", 0xa0000053},
{"fclass.s", 0xe0001053},
// D
{"fld", 0x3007},
{"fsd", 0x3027},
{"fadd.d", 0x2000053},
{"fsub.d", 0xa000053},
{"fmul.d", 0x12000053},
{"fdiv.d", 0x1a000053},
{"fsqrt.d", 0x5a000053},
{"fmin.d", 0x2a000053},
{"fmax.d", 0x2a001053},
{"fmadd.d", 0x2000043},
{"fmsub.d", 0x2000047},
{"fnmsub.d", 0x200004b},
{"fnmadd.d", 0x200004f},
{"fcvt.w.d", 0xc2000053},
{"fcvt.wu.d", 0xc2100053},
{"fcvt.l.d", 0xc2200053},
{"fcvt.lu.d", 0xc2300053},
{"fcvt.d.w", 0xd2000053},
{"fcvt.d.wu", 0xd2100053},
{"fcvt.d.l", 0xd2200053},
{"fcvt.d.lu", 0xd2300053},
{"fcvt.s.d", 0x40100053},
{"fcvt.d.s", 0x42000053},
{"fsgnj.d", 0x22000053},
{"fsgnjn.d", 0x22001053},
{"fsgnjx.d", 0x22002053},
{"fmv.x.d", 0xe2000053},
{"fmv.d.x", 0xf2000053},
{"feq.d", 0xa2002053},
{"flt.d", 0xa2001053},
{"fle.d", 0xa2000053},
{"fclass.d", 0xe2001053},
// Q
{"flq", 0x4007},
{"fsq", 0x4027},
{"fadd.q", 0x6000053},
{"fsub.q", 0xe000053},
{"fmul.q", 0x16000053},
{"fdiv.q", 0x1e000053},
{"fsqrt.q", 0x5e000053},
{"fmin.q", 0x2e000053},
{"fmax.q", 0x2e001053},
{"fmadd.q", 0x6000043},
{"fmsub.q", 0x6000047},
{"fnmsub.q", 0x600004b},
{"fnmadd.q", 0x600004f},
{"fcvt.w.q", 0xc6000053},
{"fcvt.wu.q", 0xc6100053},
{"fcvt.l.q", 0xc6200053},
{"fcvt.lu.q", 0xc6300053},
{"fcvt.s.q", 0x40300053},
{"fcvt.q.s", 0x46000053},
{"fcvt.d.q", 0x42300053},
{"fcvt.q.d", 0x46100053},
{"fcvt.q.w", 0xd6000053},
{"fcvt.q.wu", 0xd6100053},
{"fcvt.q.l", 0xd6200053},
{"fcvt.q.lu", 0xd6300053},
{"fsgnj.q", 0x26000053},
{"fsgnjn.q", 0x26001053},
{"fsgnjx.q", 0x26002053},
{"feq.q", 0xa6002053},
{"flt.q", 0xa6001053},
{"fle.q", 0xa6000053},
{"fclass.q", 0xe6001053},
// Zfa
{"fli.s", 0xf0100053},
{"fminm.s", 0x28002053},
{"fmaxm.s", 0x28003053},
{"fround.s", 0x40400053},
{"froundnx.s", 0x40500053},
{"fltq.s", 0xa0005053},
{"fleq.s", 0xa0004053},
{"fli.d", 0xf2100053},
{"fminm.d", 0x2a002053},
{"fmaxm.d", 0x2a003053},
{"fround.d", 0x42400053},
{"froundnx.d", 0x42500053},
{"fmvh.x.d", 0xe2100053},
{"fmvh.x.q", 0xe6100053},
{"fmvp.d.x", 0xb2000053},
{"fmvp.q.x", 0xb6000053},
{"fcvtmod.w.d", 0xc2801053},
{"fltq.d", 0xa2005053},
{"fleq.d", 0xa2004053},
{"fli.q", 0xf6100053},
{"fminm.q", 0x2e002053},
{"fmaxm.q", 0x2e003053},
{"fround.q", 0x46400053},
{"froundnx.q", 0x46500053},
{"fltq.q", 0xa6005053},
{"fleq.q", 0xa6004053},
{"fli.h", 0xf4100053},
{"fminm.h", 0x2c002053},
{"fmaxm.h", 0x2c003053},
{"fround.h", 0x44400053},
{"froundnx.h", 0x44500053},
{"fltq.h", 0xa4005053},
{"fleq.h", 0xa4004053},
// Zfh
{"flh", 0x1007},
{"fsh", 0x1027},
{"fadd.h", 0x4000053},
{"fsub.h", 0xc000053},
{"fmul.h", 0x14000053},
{"fdiv.h", 0x1c000053},
{"fmin.h", 0x2c000053},
{"fmax.h", 0x2c001053},
{"fsqrt.h", 0x5c000053},
{"fmadd.h", 0x4000043},
{"fmsub.h", 0x4000047},
{"fnmsub.h", 0x400004b},
{"fnmadd.h", 0x400004f},
{"fcvt.w.h", 0xc4000053},
{"fcvt.wu.h", 0xc4100053},
{"fcvt.l.h", 0xc4200053},
{"fcvt.lu.h", 0xc4300053},
{"fcvt.h.w", 0xd4000053},
{"fcvt.h.wu", 0xd4100053},
{"fcvt.h.l", 0xd4200053},
{"fcvt.h.lu", 0xd4300053},
{"fcvt.h.s", 0x44000053},
{"fcvt.s.h", 0x40200053},
{"fcvt.h.d", 0x44100053},
{"fcvt.d.h", 0x42200053},
{"fcvt.h.q", 0x44300053},
{"fcvt.q.h", 0x46200053},
{"fsgnj.h", 0x24000053},
{"fsgnjn.h", 0x24001053},
{"fsgnjx.h", 0x24002053},
{"fmv.x.h", 0xe4000053},
{"fmv.h.x", 0xf4000053},
{"feq.h", 0xa4002053},
{"flt.h", 0xa4001053},
{"fle.h", 0xa4000053},
{"fclass.h", 0xe4001053},
// BF16
{"fcvt.bf16.s", 0x44800053},
{"fcvt.s.bf16", 0x40600053},
// Zifencei
{"fence.i", 0x100f},
// Zicntr
{"rdcycle", 0xc0002073},
{"rdtime", 0xc0102073},
{"rdinstret", 0xc0202073},
{"rdcycleh", 0xc8002073},
{"rdtimeh", 0xc8102073},
{"rdinstreth", 0xc8202073},
// Zicond
{"czero.eqz", 0xe005033},
{"czero.nez", 0xe007033},
// Zalrsc
{"lr.w", 0x1000202f},
{"sc.w", 0x1800202f},
{"lr.d", 0x1000302f},
{"sc.d", 0x1800302f},
// Misc standard
{"sfence.vma", 0x12000073},
{"wfi", 0x10500073},
// Custom integer arithmetic
{"packb", 0x8000603b},
{"bitmixb", 0x8000703b},
// Custom store
{"shl", 0x1800303b},
{"shg", 0x1a00303b},
{"sbl", 0x1000303b},
{"sbg", 0x1200303b},
// Custom scalar AMO
{"amoaddg.d", 0x0200303b},
{"amoaddg.w", 0x0200203b},
{"amoaddl.d", 0x0000303b},
{"amoaddl.w", 0x0000203b},
{"amoandg.d", 0x6200303b},
{"amoandg.w", 0x6200203b},
{"amoandl.d", 0x6000303b},
{"amoandl.w", 0x6000203b},
{"amocmpswapg.d", 0xf200303b},
{"amocmpswapg.w", 0xf200203b},
{"amocmpswapl.d", 0xf000303b},
{"amocmpswapl.w", 0xf000203b},
{"amomaxg.d", 0xa200303b},
{"amomaxg.w", 0xa200203b},
{"amomaxl.d", 0xa000303b},
{"amomaxl.w", 0xa000203b},
{"amomaxug.d", 0xe200303b},
{"amomaxug.w", 0xe200203b},
{"amomaxul.d", 0xe000303b},
{"amomaxul.w", 0xe000203b},
{"amoming.d", 0x8200303b},
{"amoming.w", 0x8200203b},
{"amominl.d", 0x8000303b},
{"amominl.w", 0x8000203b},
{"amominug.d", 0xc200303b},
{"amominug.w", 0xc200203b},
{"amominul.d", 0xc000303b},
{"amominul.w", 0xc000203b},
{"amoorg.d", 0x4200303b},
{"amoorg.w", 0x4200203b},
{"amoorl.d", 0x4000303b},
{"amoorl.w", 0x4000203b},
{"amoswapg.d", 0x0a00303b},
{"amoswapg.w", 0x0a00203b},
{"amoswapl.d", 0x0800303b},
{"amoswapl.w", 0x0800203b},
{"amoxorg.d", 0x2200303b},
{"amoxorg.w", 0x2200203b},
{"amoxorl.d", 0x2000303b},
{"amoxorl.w", 0x2000203b},
// Custom SIMD AMO, integer
{"famoaddg.pi", 0x8600400b},
{"famoaddl.pi", 0x0600400b},
{"famoandg.pi", 0x9600400b},
{"famoandl.pi", 0x1600400b},
{"famomaxg.pi", 0xb600400b},
{"famomaxl.pi", 0x3600400b},
{"famomaxug.pi", 0xc600400b},
{"famomaxul.pi", 0x4600400b},
{"famoming.pi", 0xae00400b},
{"famominl.pi", 0x2e00400b},
{"famominug.pi", 0xbe00400b},
{"famominul.pi", 0x3e00400b},
{"famoorg.pi", 0x9e00400b},
{"famoorl.pi", 0x1e00400b},
{"famoswapg.pi", 0x8e00400b},
{"famoswapl.pi", 0x0e00400b},
{"famoxorg.pi", 0xa600400b},
{"famoxorl.pi", 0x2600400b},
// Custom SIMD AMO, FP32
{"famominl.ps", 0x3000400b},
{"famoming.ps", 0xb000400b},
{"famomaxl.ps", 0x2800400b},
{"famomaxg.ps", 0xa800400b},
// SIMD scatter
{"fscw.ps", 0xe000100b},
{"fscwl.ps", 0xd000700b},
{"fscwg.ps", 0xd200700b},
{"fsch.ps", 0xd000100b},
{"fschl.ps", 0xc800700b},
{"fschg.ps", 0xca00700b},
{"fscb.ps", 0xc800100b},
{"fscbl.ps", 0xc000700b},
{"fscbg.ps", 0xc200700b},
{"fsc32w.ps", 0xa000100b},
{"fsc32h.ps", 0x9000100b},
{"fsc32b.ps", 0x8800100b},
// SIMD gather
{"fgw.ps", 0x6000100b},
{"fgwl.ps", 0x9000700b},
{"fgwg.ps", 0x9200700b},
{"fgh.ps", 0x5000100b},
{"fghl.ps", 0x8800700b},
{"fghg.ps", 0x8a00700b},
{"fgb.ps", 0x4800100b},
{"fgbl.ps", 0x8000700b},
{"fgbg.ps", 0x8200700b},
{"fg32w.ps", 0x2000100b},
{"fg32h.ps", 0x1000100b},
{"fg32b.ps", 0x0800100b},
// SIMD load / store
{"flq2", 0x00005007},
{"flw.ps", 0x0000200b},
{"flwl.ps", 0x1000700b},
{"flwg.ps", 0x1200700b},
{"fsq2", 0x00005027},
{"fsw.ps", 0x0000600b},
{"fswl.ps", 0x5000700b},
{"fswg.ps", 0x5200700b},
{"fbc.ps", 0x0000000b},
// SIMD broadcast / shuffle / data movement
{"fbci.pi", 0x0000005f},
{"fbci.ps", 0x0000001f},
{"fbcx.ps", 0x0000300b},
{"fmvs.x.ps", 0xe000207b},
{"fmvz.x.ps", 0xe000007b},
{"fswizz.ps", 0xe600007b},
{"fcmov.ps", 0x0400203f},
{"fcmovm.ps", 0x00000077},
// Custom mask
{"maskand", 0x6600707b},
{"maskor", 0x6600607b},
{"maskxor", 0x6600407b},
{"masknot", 0x6600207b},
{"mov.m.x", 0x5600007b},
{"mova.m.x", 0xd600107b},
{"mova.x.m", 0xd600007b},
{"maskpopc", 0x5200007b},
{"maskpopcz", 0x5400007b},
{"maskpopc.rast", 0x5e00007b},
// Integer SIMD, arithmetic
{"fadd.pi", 0x0600007b},
{"faddi.pi", 0x0400003f},
{"fsub.pi", 0x0e00007b},
{"fmul.pi", 0x1600007b},
{"fmulh.pi", 0x1600107b},
{"fmulhu.pi", 0x1600207b},
{"fdiv.pi", 0x1e00007b},
{"fdivu.pi", 0x1e00107b},
{"frem.pi", 0x1e00207b},
{"fremu.pi", 0x1e00307b},
{"fmin.pi", 0x2e00007b},
{"fminu.pi", 0x2e00207b},
{"fmax.pi", 0x2e00107b},
{"fmaxu.pi", 0x2e00307b},
// Integer SIMD, bitwise
{"fand.pi", 0x0600707b},
{"fandi.pi", 0x0400103f},
{"for.pi", 0x0600607b},
{"fxor.pi", 0x0600407b},
{"fnot.pi", 0x0600207b},
{"fsll.pi", 0x0600107b},
{"fslli.pi", 0x4e00107b},
{"fslloi.pi", 0xe800007b},
{"fsra.pi", 0x0e00507b},
{"fsrai.pi", 0x4e00707b},
{"fsrl.pi", 0x0600507b},
{"fsrli.pi", 0x4e00507b},
// Integer SIMD, misc
{"fsat8.pi", 0x0600307b},
{"fsatu8.pi", 0x0610307b},
{"fpackreph.pi", 0x2600107b},
{"fpackrepb.pi", 0x2600007b},
// Integer SIMD, comparisons
{"feq.pi", 0xa600207b},
{"fle.pi", 0xa600007b},
{"flt.pi", 0xa600107b},
{"fltu.pi", 0xa600307b},
{"fltm.pi", 0x3e00007b},
{"fsetm.pi", 0xa600407b},
// FP32 SIMD, arithmetic
{"fadd.ps", 0x0000007b},
{"fsub.ps", 0x0800007b},
{"fmul.ps", 0x1000007b},
{"fdiv.ps", 0x1800007b},
{"fsqrt.ps", 0x5800007b},
{"fmin.ps", 0x2800007b},
{"fmax.ps", 0x2800107b},
{"fmadd.ps", 0x0000005b},
{"fmsub.ps", 0x0200005b},
{"fnmadd.ps", 0x0600005b},
{"fnmsub.ps", 0x0400005b},
{"fsgnj.ps", 0x2000007b},
{"fsgnjn.ps", 0x2000107b},
{"fsgnjx.ps", 0x2000207b},
{"fclass.ps", 0xe000107b},
{"frcp.ps", 0x5870007b},
{"frcp.fix.rast", 0x3000007b},
{"fexp.ps", 0x5840007b},
{"flog.ps", 0x5830007b},
{"fsin.ps", 0x5860007b},
{"frsq.ps", 0x5880007b},
{"fround.ps", 0x5810007b},
{"ffrc.ps", 0x5820007b},
// FP32 SIMD, comparisons
{"feq.ps", 0xa000207b},
{"flt.ps", 0xa000107b},
{"fle.ps", 0xa000007b},
{"feqm.ps", 0xa000607b},
{"fltm.ps", 0xa000507b},
{"flem.ps", 0xa000407b},
// FP32 SIMD, conversions
{"fcvt.f10.ps", 0xd8b0007b},
{"fcvt.f11.ps", 0xd880007b},
{"fcvt.f16.ps", 0xd890007b},
{"fcvt.ps.f10", 0xd080007b},
{"fcvt.ps.f11", 0xd090007b},
{"fcvt.ps.f16", 0xd0a0007b},
{"fcvt.ps.pw", 0xd000007b},
{"fcvt.ps.pwu", 0xd010007b},
{"fcvt.ps.rast", 0xd020007b},
{"fcvt.ps.sn16", 0xd190007b},
{"fcvt.ps.sn8", 0xd1b0007b},
{"fcvt.ps.un10", 0xd120007b},
{"fcvt.ps.un16", 0xd110007b},
{"fcvt.ps.un2", 0xd170007b},
{"fcvt.ps.un24", 0xd100007b},
{"fcvt.ps.un8", 0xd130007b},
{"fcvt.pw.ps", 0xc000007b},
{"fcvt.pwu.ps", 0xc010007b},
{"fcvt.rast.ps", 0xc020007b},
{"fcvt.sn16.ps", 0xd990007b},
{"fcvt.sn8.ps", 0xd9b0007b},
{"fcvt.un10.ps", 0xd920007b},
{"fcvt.un16.ps", 0xd910007b},
{"fcvt.un2.ps", 0xd970007b},
{"fcvt.un24.ps", 0xd900007b},
{"fcvt.un8.ps", 0xd930007b},
// FP32 graphics misc
{"cubeface.ps", 0x8800007b},
{"cubefaceidx.ps", 0x8800107b},
{"cubesgnsc.ps", 0x8800207b},
{"cubesgntc.ps", 0x8800307b},