Skip to content

Instantly share code, notes, and snippets.

@cr1901
cr1901 / .env.sample
Last active August 27, 2022 22:25
FOSS FPGA Toolchain Build Script
PREFIX=/path/to/install
FPGA_ROOT=/root/of/repos
NUM_JOBS=4
# If non-zero, enable sscache optimizations. Need to set CC and CXX as well.
SCCACHE=0
CC=gcc
CXX=g++
# If non-zero, use chipdbs built on another machine.
@cr1901
cr1901 / genmake.m4
Last active July 3, 2022 21:21
m4 (simple) Makefile generator
dnl http://mbreen.com/m4.html#toc19
define(`LQ',`changequote(<,>)`dnl'
changequote`'')dnl
define(`RQ',`changequote(<,>)dnl`
'changequote`'')dnl
define(`for',`ifelse($#,0,``$0'',`ifelse(eval($2<=$3),1,
`pushdef(`$1',$2)$4`'popdef(`$1')$0(`$1',incr($2),$3,`$4')')')')dnl
define(`foreach',`ifelse(eval($#>2),1,
`pushdef(`$1',`$3')$2`'popdef(`$1')dnl
`'ifelse(eval($#>3),1,`$0(`$1',`$2',shift(shift(shift($@))))')')')dnl
@cr1901
cr1901 / clock_domains.md
Last active July 4, 2021 07:14
Migen Clock Domain Summary

Migen Clock Domains Summary

Terminology

  • Declaring a clock domain:
    • self.clock_domains.cd_mycd = ClockDomain()
  • Referencing a clock domain:
    • self.sync.mycd += []
    • ClockSignal("mycd")
  • Requesting an I/O signal:
  • platform.request("clk12")
@cr1901
cr1901 / rot.py
Last active July 9, 2020 19:50
Migen IceStorm Code Sample
#!/usr/bin/env python3
from migen import *
from migen.build.platforms import icestick
class Rot(Module):
def __init__(self):
self.clk_freq = 12000000
self.ready = Signal()
self.rot = Signal(4)
@cr1901
cr1901 / fm-py.ipynb
Created February 20, 2020 03:37
FM Synthesis Class Proof-of-Concept
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
@cr1901
cr1901 / Cargo.toml
Last active December 25, 2019 07:46
RefCell Misoptimization
[package]
name = "take-api"
version = "0.1.0"
authors = ["William D. Jones <thor0505@comcast.net>"]
edition = "2018"
[dependencies]
bare-metal = {version = "0.2.5", optional = true }
[dependencies.msp430-rt]
@cr1901
cr1901 / async.py
Last active January 11, 2019 17:34
quamash asyncio sample
import asyncio
import atexit
from quamash import QEventLoop, QtGui, QtCore
from pyqtgraph import dockarea # Will import PyQt5.QtGui.QApplication
class MainWindow(QtGui.QMainWindow):
def __init__(self, app, server):
QtGui.QMainWindow.__init__(self)
@cr1901
cr1901 / boneless.rtlil
Created January 1, 2019 07:13
Boneless Formal Example
# Generated by Yosys 0.8+29 (git sha1 d86ea6ba, x86_64-w64-mingw32-g++ 7.3.0 -Os)
autoidx 712
attribute \cells_not_processed 1
attribute \src "boneless.v:3"
module \boneless_formal
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:161$14_CHECK[0:0]$116
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:161$14_EN[0:0]$117
attribute \src "boneless.v:161"
@cr1901
cr1901 / signed-cmp.md
Last active December 10, 2018 09:46
Signed Subtraction Flags Cheat Sheet

Flags table for the operation: a - b

Flag Legend

  • Z- Is the result zero?
  • S- Is the top bit of the result set?
  • C- Did a borrow not occur (see Subtraction on the 6502)?
    • For architectures with a true borrow flag, invert the C bit.
  • V- Does the result of a - b fit within signed 16-bit range?

Other notes

@cr1901
cr1901 / Makefile
Last active September 5, 2018 22:39
NetBSD RPi i2c sample code
CFLAGS=
CPPFLAGS=
LDFLAGS=
LIBS=
RM=rm
RMFLAGS=-f
INSTALL=install
i2ceprog: i2ceprog.c